2018-04-02 22:34:32 +00:00
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2014-2018 Broadcom
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* All rights reserved.
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2016-06-15 21:23:11 +00:00
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*/
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#include <inttypes.h>
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#include <rte_malloc.h>
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#include "bnxt.h"
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#include "bnxt_filter.h"
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#include "bnxt_hwrm.h"
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#include "bnxt_ring.h"
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#include "bnxt_rxq.h"
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2016-06-15 21:23:14 +00:00
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#include "bnxt_rxr.h"
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2016-06-15 21:23:11 +00:00
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#include "bnxt_vnic.h"
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#include "hsi_struct_def_dpdk.h"
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/*
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* RX Queues
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*/
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void bnxt_free_rxq_stats(struct bnxt_rx_queue *rxq)
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{
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2018-05-01 01:06:09 +00:00
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if (rxq && rxq->cp_ring && rxq->cp_ring->hw_stats)
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rxq->cp_ring->hw_stats = NULL;
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2016-06-15 21:23:11 +00:00
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}
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int bnxt_mq_rx_configure(struct bnxt *bp)
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{
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struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
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2017-10-05 15:06:44 +00:00
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const struct rte_eth_vmdq_rx_conf *conf =
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&dev_conf->rx_adv_conf.vmdq_rx_conf;
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2017-09-28 21:43:26 +00:00
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unsigned int i, j, nb_q_per_grp = 1, ring_idx = 0;
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int start_grp_id, end_grp_id = 1, rc = 0;
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2016-06-15 21:23:11 +00:00
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struct bnxt_vnic_info *vnic;
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struct bnxt_filter_info *filter;
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2019-11-13 08:29:42 +00:00
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enum rte_eth_nb_pools pools = 1, max_pools = 0;
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2016-06-15 21:23:11 +00:00
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struct bnxt_rx_queue *rxq;
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bp->nr_vnics = 0;
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/* Single queue mode */
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if (bp->rx_cp_nr_rings < 2) {
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2018-09-29 01:59:52 +00:00
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vnic = &bp->vnic_info[0];
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2016-06-15 21:23:11 +00:00
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if (!vnic) {
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2018-01-26 17:31:55 +00:00
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PMD_DRV_LOG(ERR, "VNIC alloc failed\n");
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2016-06-15 21:23:11 +00:00
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rc = -ENOMEM;
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goto err_out;
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}
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2017-06-01 17:07:22 +00:00
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vnic->flags |= BNXT_VNIC_INFO_BCAST;
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2016-06-15 21:23:11 +00:00
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bp->nr_vnics++;
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rxq = bp->eth_dev->data->rx_queues[0];
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rxq->vnic = vnic;
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vnic->func_default = true;
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2017-06-01 17:07:09 +00:00
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vnic->start_grp_id = 0;
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vnic->end_grp_id = vnic->start_grp_id;
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2016-06-15 21:23:11 +00:00
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filter = bnxt_alloc_filter(bp);
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if (!filter) {
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2018-01-26 17:31:55 +00:00
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PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
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2016-06-15 21:23:11 +00:00
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rc = -ENOMEM;
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goto err_out;
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}
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2019-11-04 10:02:37 +00:00
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filter->mac_index = 0;
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2019-10-02 23:25:45 +00:00
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filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
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2016-06-15 21:23:11 +00:00
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STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
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goto out;
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}
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/* Multi-queue mode */
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2017-09-28 21:43:26 +00:00
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if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_DCB_RSS) {
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2016-06-15 21:23:11 +00:00
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/* VMDq ONLY, VMDq+RSS, VMDq+DCB, VMDq+DCB+RSS */
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switch (dev_conf->rxmode.mq_mode) {
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case ETH_MQ_RX_VMDQ_RSS:
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case ETH_MQ_RX_VMDQ_ONLY:
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2019-10-04 03:48:58 +00:00
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case ETH_MQ_RX_VMDQ_DCB_RSS:
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2018-05-22 18:13:41 +00:00
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/* FALLTHROUGH */
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2017-09-28 21:43:26 +00:00
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/* ETH_8/64_POOLs */
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pools = conf->nb_queue_pools;
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/* For each pool, allocate MACVLAN CFA rule & VNIC */
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max_pools = RTE_MIN(bp->max_vnics,
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RTE_MIN(bp->max_l2_ctx,
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RTE_MIN(bp->max_rsscos_ctx,
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ETH_64_POOLS)));
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2018-09-29 01:59:52 +00:00
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PMD_DRV_LOG(DEBUG,
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"pools = %u max_pools = %u\n",
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pools, max_pools);
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2017-09-28 21:43:26 +00:00
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if (pools > max_pools)
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pools = max_pools;
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break;
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case ETH_MQ_RX_RSS:
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2019-10-04 03:48:58 +00:00
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pools = bp->rx_cosq_cnt ? bp->rx_cosq_cnt : 1;
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2017-09-28 21:43:26 +00:00
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break;
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2016-06-15 21:23:11 +00:00
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default:
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2018-01-26 17:31:55 +00:00
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PMD_DRV_LOG(ERR, "Unsupported mq_mod %d\n",
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2016-06-15 21:23:11 +00:00
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dev_conf->rxmode.mq_mode);
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rc = -EINVAL;
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goto err_out;
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}
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2019-11-13 08:29:42 +00:00
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} else if (!dev_conf->rxmode.mq_mode) {
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pools = bp->rx_cosq_cnt ? bp->rx_cosq_cnt : pools;
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2017-09-28 21:43:26 +00:00
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}
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2019-11-13 08:29:42 +00:00
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pools = RTE_MIN(pools, bp->rx_cp_nr_rings);
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2017-09-28 21:43:26 +00:00
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nb_q_per_grp = bp->rx_cp_nr_rings / pools;
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2019-10-02 23:25:43 +00:00
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bp->rx_num_qs_per_vnic = nb_q_per_grp;
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2019-03-14 21:32:14 +00:00
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PMD_DRV_LOG(DEBUG, "pools = %u nb_q_per_grp = %u\n",
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pools, nb_q_per_grp);
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2017-09-28 21:43:26 +00:00
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start_grp_id = 0;
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end_grp_id = nb_q_per_grp;
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for (i = 0; i < pools; i++) {
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2018-09-29 01:59:52 +00:00
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vnic = &bp->vnic_info[i];
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2017-09-28 21:43:26 +00:00
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if (!vnic) {
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2018-01-26 17:31:55 +00:00
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PMD_DRV_LOG(ERR, "VNIC alloc failed\n");
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2017-09-28 21:43:26 +00:00
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rc = -ENOMEM;
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goto err_out;
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2016-06-15 21:23:11 +00:00
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}
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2017-09-28 21:43:26 +00:00
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vnic->flags |= BNXT_VNIC_INFO_BCAST;
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bp->nr_vnics++;
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2016-06-15 21:23:11 +00:00
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2017-10-24 21:19:42 +00:00
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for (j = 0; j < nb_q_per_grp; j++, ring_idx++) {
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2017-09-28 21:43:26 +00:00
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rxq = bp->eth_dev->data->rx_queues[ring_idx];
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rxq->vnic = vnic;
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2018-09-29 01:59:52 +00:00
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PMD_DRV_LOG(DEBUG,
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"rxq[%d] = %p vnic[%d] = %p\n",
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ring_idx, rxq, i, vnic);
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2016-06-15 21:23:11 +00:00
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}
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2017-10-05 15:06:44 +00:00
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if (i == 0) {
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if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_DCB) {
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bp->eth_dev->data->promiscuous = 1;
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vnic->flags |= BNXT_VNIC_INFO_PROMISC;
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}
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2017-09-28 21:43:26 +00:00
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vnic->func_default = true;
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2017-10-05 15:06:44 +00:00
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}
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2017-09-28 21:43:26 +00:00
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vnic->start_grp_id = start_grp_id;
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vnic->end_grp_id = end_grp_id;
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2017-10-24 21:19:42 +00:00
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if (i) {
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if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_VMDQ_DCB ||
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!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS))
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vnic->rss_dflt_cr = true;
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2017-09-28 21:43:26 +00:00
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goto skip_filter_allocation;
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}
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filter = bnxt_alloc_filter(bp);
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if (!filter) {
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2018-01-26 17:31:55 +00:00
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PMD_DRV_LOG(ERR, "L2 filter alloc failed\n");
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2017-09-28 21:43:26 +00:00
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rc = -ENOMEM;
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goto err_out;
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}
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2019-11-04 10:02:37 +00:00
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filter->mac_index = 0;
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2019-10-02 23:25:45 +00:00
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filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST;
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2017-09-28 21:43:26 +00:00
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/*
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* TODO: Configure & associate CFA rule for
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* each VNIC for each VMDq with MACVLAN, MACVLAN+TC
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*/
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STAILQ_INSERT_TAIL(&vnic->filter, filter, next);
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2016-06-15 21:23:11 +00:00
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2017-09-28 21:43:26 +00:00
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skip_filter_allocation:
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start_grp_id = end_grp_id;
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end_grp_id += nb_q_per_grp;
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2016-06-15 21:23:11 +00:00
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}
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out:
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2017-09-28 21:43:26 +00:00
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if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
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struct rte_eth_rss_conf *rss = &dev_conf->rx_adv_conf.rss_conf;
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2020-05-15 11:25:11 +00:00
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if (bp->flags & BNXT_FLAG_UPDATE_HASH)
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2017-09-28 21:43:33 +00:00
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bp->flags &= ~BNXT_FLAG_UPDATE_HASH;
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2017-09-28 21:43:26 +00:00
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for (i = 0; i < bp->nr_vnics; i++) {
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2018-09-29 01:59:52 +00:00
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vnic = &bp->vnic_info[i];
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2019-10-02 23:25:43 +00:00
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vnic->hash_type =
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bnxt_rte_to_hwrm_hash_types(rss->rss_hf);
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2017-09-28 21:43:26 +00:00
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/*
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* Use the supplied key if the key length is
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* acceptable and the rss_key is not NULL
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*/
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if (rss->rss_key &&
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rss->rss_key_len <= HW_HASH_KEY_SIZE)
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memcpy(vnic->rss_hash_key,
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rss->rss_key, rss->rss_key_len);
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}
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}
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2016-06-15 21:23:11 +00:00
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return rc;
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err_out:
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/* Free allocated vnic/filters */
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return rc;
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}
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2018-06-28 20:15:35 +00:00
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void bnxt_rx_queue_release_mbufs(struct bnxt_rx_queue *rxq)
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2016-06-15 21:23:11 +00:00
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{
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2016-06-15 21:23:14 +00:00
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struct bnxt_sw_rx_bd *sw_ring;
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2017-06-01 17:07:10 +00:00
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struct bnxt_tpa_info *tpa_info;
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2016-06-15 21:23:14 +00:00
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uint16_t i;
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2019-10-02 17:17:41 +00:00
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if (!rxq)
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return;
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2018-06-28 20:15:35 +00:00
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rte_spinlock_lock(&rxq->lock);
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2019-10-02 17:17:41 +00:00
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sw_ring = rxq->rx_ring->rx_buf_ring;
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if (sw_ring) {
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for (i = 0;
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i < rxq->rx_ring->rx_ring_struct->ring_size; i++) {
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if (sw_ring[i].mbuf) {
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rte_pktmbuf_free_seg(sw_ring[i].mbuf);
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sw_ring[i].mbuf = NULL;
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2016-06-15 21:23:14 +00:00
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}
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}
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2019-10-02 17:17:41 +00:00
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}
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/* Free up mbufs in Agg ring */
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sw_ring = rxq->rx_ring->ag_buf_ring;
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if (sw_ring) {
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for (i = 0;
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i < rxq->rx_ring->ag_ring_struct->ring_size; i++) {
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if (sw_ring[i].mbuf) {
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rte_pktmbuf_free_seg(sw_ring[i].mbuf);
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sw_ring[i].mbuf = NULL;
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2017-06-01 17:07:09 +00:00
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}
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}
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2019-10-02 17:17:41 +00:00
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}
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2017-06-01 17:07:10 +00:00
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2019-10-02 17:17:41 +00:00
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/* Free up mbufs in TPA */
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tpa_info = rxq->rx_ring->tpa_info;
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if (tpa_info) {
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2019-10-04 03:48:57 +00:00
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int max_aggs = BNXT_TPA_MAX_AGGS(rxq->bp);
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for (i = 0; i < max_aggs; i++) {
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2019-10-02 17:17:41 +00:00
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if (tpa_info[i].mbuf) {
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rte_pktmbuf_free_seg(tpa_info[i].mbuf);
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tpa_info[i].mbuf = NULL;
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2017-06-01 17:07:10 +00:00
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}
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}
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2016-06-15 21:23:14 +00:00
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}
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2018-06-28 20:15:35 +00:00
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rte_spinlock_unlock(&rxq->lock);
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2016-06-15 21:23:11 +00:00
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}
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void bnxt_free_rx_mbufs(struct bnxt *bp)
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{
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struct bnxt_rx_queue *rxq;
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int i;
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for (i = 0; i < (int)bp->rx_nr_rings; i++) {
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rxq = bp->rx_queues[i];
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bnxt_rx_queue_release_mbufs(rxq);
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}
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}
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void bnxt_rx_queue_release_op(void *rx_queue)
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{
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struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue;
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if (rxq) {
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2019-10-02 01:23:22 +00:00
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if (is_bnxt_in_error(rxq->bp))
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return;
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2016-06-15 21:23:11 +00:00
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bnxt_rx_queue_release_mbufs(rxq);
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2016-06-15 21:23:14 +00:00
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/* Free RX ring hardware descriptors */
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bnxt_free_ring(rxq->rx_ring->rx_ring_struct);
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2017-06-01 17:07:09 +00:00
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/* Free RX Agg ring hardware descriptors */
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bnxt_free_ring(rxq->rx_ring->ag_ring_struct);
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2016-06-15 21:23:14 +00:00
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/* Free RX completion ring hardware descriptors */
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bnxt_free_ring(rxq->cp_ring->cp_ring_struct);
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bnxt_free_rxq_stats(rxq);
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2018-04-17 01:11:25 +00:00
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rte_memzone_free(rxq->mz);
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rxq->mz = NULL;
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2016-06-15 21:23:11 +00:00
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rte_free(rxq);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int bnxt_rx_queue_setup_op(struct rte_eth_dev *eth_dev,
|
|
|
|
uint16_t queue_idx,
|
|
|
|
uint16_t nb_desc,
|
|
|
|
unsigned int socket_id,
|
|
|
|
const struct rte_eth_rxconf *rx_conf,
|
|
|
|
struct rte_mempool *mp)
|
|
|
|
{
|
2019-05-29 19:14:53 +00:00
|
|
|
struct bnxt *bp = eth_dev->data->dev_private;
|
2018-04-07 17:40:55 +00:00
|
|
|
uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
|
2016-06-15 21:23:11 +00:00
|
|
|
struct bnxt_rx_queue *rxq;
|
2016-06-15 21:23:15 +00:00
|
|
|
int rc = 0;
|
2018-06-28 20:15:35 +00:00
|
|
|
uint8_t queue_state;
|
2016-06-15 21:23:11 +00:00
|
|
|
|
2019-10-02 01:23:22 +00:00
|
|
|
rc = is_bnxt_in_error(bp);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
2019-11-13 08:29:41 +00:00
|
|
|
if (queue_idx >= BNXT_MAX_RINGS(bp)) {
|
2018-01-26 17:31:55 +00:00
|
|
|
PMD_DRV_LOG(ERR,
|
2018-01-08 20:24:37 +00:00
|
|
|
"Cannot create Rx ring %d. Only %d rings available\n",
|
|
|
|
queue_idx, bp->max_rx_rings);
|
2018-05-01 01:06:08 +00:00
|
|
|
return -EINVAL;
|
2018-01-08 20:24:37 +00:00
|
|
|
}
|
|
|
|
|
2016-06-15 21:23:11 +00:00
|
|
|
if (!nb_desc || nb_desc > MAX_RX_DESC_CNT) {
|
2018-01-26 17:31:55 +00:00
|
|
|
PMD_DRV_LOG(ERR, "nb_desc %d is invalid\n", nb_desc);
|
2016-06-15 21:23:15 +00:00
|
|
|
rc = -EINVAL;
|
|
|
|
goto out;
|
2016-06-15 21:23:11 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
if (eth_dev->data->rx_queues) {
|
|
|
|
rxq = eth_dev->data->rx_queues[queue_idx];
|
|
|
|
if (rxq)
|
|
|
|
bnxt_rx_queue_release_op(rxq);
|
|
|
|
}
|
|
|
|
rxq = rte_zmalloc_socket("bnxt_rx_queue", sizeof(struct bnxt_rx_queue),
|
|
|
|
RTE_CACHE_LINE_SIZE, socket_id);
|
|
|
|
if (!rxq) {
|
2018-01-26 17:31:55 +00:00
|
|
|
PMD_DRV_LOG(ERR, "bnxt_rx_queue allocation failed!\n");
|
2016-06-15 21:23:15 +00:00
|
|
|
rc = -ENOMEM;
|
|
|
|
goto out;
|
2016-06-15 21:23:11 +00:00
|
|
|
}
|
|
|
|
rxq->bp = bp;
|
|
|
|
rxq->mb_pool = mp;
|
|
|
|
rxq->nb_rx_desc = nb_desc;
|
|
|
|
rxq->rx_free_thresh = rx_conf->rx_free_thresh;
|
|
|
|
|
2018-01-26 17:31:55 +00:00
|
|
|
PMD_DRV_LOG(DEBUG, "RX Buf MTU %d\n", eth_dev->data->mtu);
|
2017-06-01 17:07:09 +00:00
|
|
|
|
2016-06-15 21:23:15 +00:00
|
|
|
rc = bnxt_init_rx_ring_struct(rxq, socket_id);
|
|
|
|
if (rc)
|
|
|
|
goto out;
|
2016-06-15 21:23:11 +00:00
|
|
|
|
2019-10-02 17:17:31 +00:00
|
|
|
PMD_DRV_LOG(DEBUG, "RX Buf size is %d\n", rxq->rx_buf_size);
|
2016-06-15 21:23:11 +00:00
|
|
|
rxq->queue_id = queue_idx;
|
|
|
|
rxq->port_id = eth_dev->data->port_id;
|
2018-09-04 10:12:56 +00:00
|
|
|
if (rx_offloads & DEV_RX_OFFLOAD_KEEP_CRC)
|
2019-05-21 16:13:05 +00:00
|
|
|
rxq->crc_len = RTE_ETHER_CRC_LEN;
|
2018-09-04 10:12:56 +00:00
|
|
|
else
|
|
|
|
rxq->crc_len = 0;
|
2016-06-15 21:23:11 +00:00
|
|
|
|
|
|
|
eth_dev->data->rx_queues[queue_idx] = rxq;
|
2016-06-15 21:23:14 +00:00
|
|
|
/* Allocate RX ring hardware descriptors */
|
2019-10-04 03:48:59 +00:00
|
|
|
if (bnxt_alloc_rings(bp, queue_idx, NULL, rxq, rxq->cp_ring, NULL,
|
|
|
|
"rxr")) {
|
2018-01-26 17:31:55 +00:00
|
|
|
PMD_DRV_LOG(ERR,
|
2017-06-01 17:07:22 +00:00
|
|
|
"ring_dma_zone_reserve for rx_ring failed!\n");
|
2016-06-15 21:23:14 +00:00
|
|
|
bnxt_rx_queue_release_op(rxq);
|
2016-06-15 21:23:15 +00:00
|
|
|
rc = -ENOMEM;
|
|
|
|
goto out;
|
2016-06-15 21:23:14 +00:00
|
|
|
}
|
2018-04-17 01:11:21 +00:00
|
|
|
rte_atomic64_init(&rxq->rx_mbuf_alloc_fail);
|
2016-06-15 21:23:11 +00:00
|
|
|
|
2019-10-02 17:17:32 +00:00
|
|
|
/* rxq 0 must not be stopped when used as async CPR */
|
|
|
|
if (!BNXT_NUM_ASYNC_CPR(bp) && queue_idx == 0)
|
|
|
|
rxq->rx_deferred_start = false;
|
|
|
|
else
|
|
|
|
rxq->rx_deferred_start = rx_conf->rx_deferred_start;
|
|
|
|
|
|
|
|
if (rxq->rx_deferred_start) {
|
|
|
|
queue_state = RTE_ETH_QUEUE_STATE_STOPPED;
|
|
|
|
rxq->rx_started = false;
|
|
|
|
} else {
|
|
|
|
queue_state = RTE_ETH_QUEUE_STATE_STARTED;
|
|
|
|
rxq->rx_started = true;
|
|
|
|
}
|
2018-06-28 20:15:35 +00:00
|
|
|
eth_dev->data->rx_queue_state[queue_idx] = queue_state;
|
|
|
|
rte_spinlock_init(&rxq->lock);
|
2019-05-29 21:02:23 +00:00
|
|
|
|
2019-10-24 07:44:27 +00:00
|
|
|
/* Configure mtu if it is different from what was configured before */
|
|
|
|
if (!queue_idx)
|
|
|
|
bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu);
|
|
|
|
|
2016-06-15 21:23:15 +00:00
|
|
|
out:
|
|
|
|
return rc;
|
2016-06-15 21:23:11 +00:00
|
|
|
}
|
2017-09-28 21:43:45 +00:00
|
|
|
|
|
|
|
int
|
|
|
|
bnxt_rx_queue_intr_enable_op(struct rte_eth_dev *eth_dev, uint16_t queue_id)
|
|
|
|
{
|
2019-10-02 01:23:22 +00:00
|
|
|
struct bnxt *bp = eth_dev->data->dev_private;
|
2017-09-28 21:43:45 +00:00
|
|
|
struct bnxt_rx_queue *rxq;
|
|
|
|
struct bnxt_cp_ring_info *cpr;
|
|
|
|
int rc = 0;
|
|
|
|
|
2019-10-02 01:23:22 +00:00
|
|
|
rc = is_bnxt_in_error(bp);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
2017-09-28 21:43:45 +00:00
|
|
|
if (eth_dev->data->rx_queues) {
|
|
|
|
rxq = eth_dev->data->rx_queues[queue_id];
|
2019-10-10 01:41:53 +00:00
|
|
|
if (!rxq)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2017-09-28 21:43:45 +00:00
|
|
|
cpr = rxq->cp_ring;
|
2019-07-19 06:19:03 +00:00
|
|
|
B_CP_DB_REARM(cpr, cpr->cp_raw_cons);
|
2017-09-28 21:43:45 +00:00
|
|
|
}
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
bnxt_rx_queue_intr_disable_op(struct rte_eth_dev *eth_dev, uint16_t queue_id)
|
|
|
|
{
|
2019-10-02 01:23:22 +00:00
|
|
|
struct bnxt *bp = eth_dev->data->dev_private;
|
2017-09-28 21:43:45 +00:00
|
|
|
struct bnxt_rx_queue *rxq;
|
|
|
|
struct bnxt_cp_ring_info *cpr;
|
|
|
|
int rc = 0;
|
|
|
|
|
2019-10-02 01:23:22 +00:00
|
|
|
rc = is_bnxt_in_error(bp);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
2017-09-28 21:43:45 +00:00
|
|
|
if (eth_dev->data->rx_queues) {
|
|
|
|
rxq = eth_dev->data->rx_queues[queue_id];
|
2019-10-10 01:41:53 +00:00
|
|
|
if (!rxq)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2017-09-28 21:43:45 +00:00
|
|
|
cpr = rxq->cp_ring;
|
|
|
|
B_CP_DB_DISARM(cpr);
|
|
|
|
}
|
|
|
|
return rc;
|
|
|
|
}
|
2018-01-26 17:31:58 +00:00
|
|
|
|
|
|
|
int bnxt_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
|
|
|
|
{
|
2019-05-29 19:14:53 +00:00
|
|
|
struct bnxt *bp = dev->data->dev_private;
|
2018-01-26 17:31:58 +00:00
|
|
|
struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
|
|
|
|
struct bnxt_rx_queue *rxq = bp->rx_queues[rx_queue_id];
|
|
|
|
struct bnxt_vnic_info *vnic = NULL;
|
2018-06-28 20:15:35 +00:00
|
|
|
int rc = 0;
|
2018-01-26 17:31:58 +00:00
|
|
|
|
2019-10-02 01:23:22 +00:00
|
|
|
rc = is_bnxt_in_error(bp);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
2018-01-26 17:31:58 +00:00
|
|
|
if (rxq == NULL) {
|
|
|
|
PMD_DRV_LOG(ERR, "Invalid Rx queue %d\n", rx_queue_id);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2019-10-02 17:17:32 +00:00
|
|
|
/* Set the queue state to started here.
|
|
|
|
* We check the status of the queue while posting buffer.
|
|
|
|
* If queue is it started, we do not post buffers for Rx.
|
|
|
|
*/
|
|
|
|
rxq->rx_started = true;
|
2019-11-04 20:27:45 +00:00
|
|
|
dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
|
|
|
|
|
2018-06-28 20:15:35 +00:00
|
|
|
bnxt_free_hwrm_rx_ring(bp, rx_queue_id);
|
2019-07-24 16:49:32 +00:00
|
|
|
rc = bnxt_alloc_hwrm_rx_ring(bp, rx_queue_id);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
2019-11-04 20:27:47 +00:00
|
|
|
if (BNXT_CHIP_THOR(bp)) {
|
|
|
|
/* Reconfigure default receive ring and MRU. */
|
|
|
|
bnxt_hwrm_vnic_cfg(bp, rxq->vnic);
|
|
|
|
}
|
2018-01-26 17:31:58 +00:00
|
|
|
PMD_DRV_LOG(INFO, "Rx queue started %d\n", rx_queue_id);
|
2018-06-28 20:15:35 +00:00
|
|
|
|
2018-01-26 17:31:58 +00:00
|
|
|
if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
|
|
|
|
vnic = rxq->vnic;
|
2018-06-28 20:15:35 +00:00
|
|
|
|
2019-06-02 17:42:44 +00:00
|
|
|
if (BNXT_HAS_RING_GRPS(bp)) {
|
|
|
|
if (vnic->fw_grp_ids[rx_queue_id] != INVALID_HW_RING_ID)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
vnic->fw_grp_ids[rx_queue_id] =
|
|
|
|
bp->grp_info[rx_queue_id].fw_grp_id;
|
2019-10-02 17:17:32 +00:00
|
|
|
PMD_DRV_LOG(DEBUG,
|
|
|
|
"vnic = %p fw_grp_id = %d\n",
|
|
|
|
vnic, bp->grp_info[rx_queue_id].fw_grp_id);
|
2019-06-02 17:42:44 +00:00
|
|
|
}
|
2018-06-28 20:15:35 +00:00
|
|
|
|
2019-10-02 23:25:43 +00:00
|
|
|
PMD_DRV_LOG(DEBUG, "Rx Queue Count %d\n", vnic->rx_queue_cnt);
|
2019-11-04 20:27:44 +00:00
|
|
|
rc = bnxt_vnic_rss_configure(bp, vnic);
|
2018-01-26 17:31:58 +00:00
|
|
|
}
|
|
|
|
|
2019-11-04 20:27:45 +00:00
|
|
|
if (rc != 0) {
|
2019-07-24 16:49:32 +00:00
|
|
|
dev->data->rx_queue_state[rx_queue_id] =
|
2019-11-04 20:27:45 +00:00
|
|
|
RTE_ETH_QUEUE_STATE_STOPPED;
|
2019-10-02 17:17:32 +00:00
|
|
|
rxq->rx_started = false;
|
2019-11-04 20:27:45 +00:00
|
|
|
}
|
2019-07-24 16:49:32 +00:00
|
|
|
|
|
|
|
PMD_DRV_LOG(INFO,
|
|
|
|
"queue %d, rx_deferred_start %d, state %d!\n",
|
|
|
|
rx_queue_id, rxq->rx_deferred_start,
|
|
|
|
bp->eth_dev->data->rx_queue_state[rx_queue_id]);
|
2018-06-28 20:15:35 +00:00
|
|
|
|
|
|
|
return rc;
|
2018-01-26 17:31:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int bnxt_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
|
|
|
|
{
|
2019-05-29 19:14:53 +00:00
|
|
|
struct bnxt *bp = dev->data->dev_private;
|
2018-01-26 17:31:58 +00:00
|
|
|
struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
|
|
|
|
struct bnxt_vnic_info *vnic = NULL;
|
2018-06-28 20:15:35 +00:00
|
|
|
struct bnxt_rx_queue *rxq = NULL;
|
2019-11-04 20:27:47 +00:00
|
|
|
int active_queue_cnt = 0;
|
|
|
|
int i, rc = 0;
|
2018-06-28 20:15:35 +00:00
|
|
|
|
2019-10-02 01:23:22 +00:00
|
|
|
rc = is_bnxt_in_error(bp);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
2019-07-24 16:49:32 +00:00
|
|
|
/* For the stingray platform and other platforms needing tighter
|
|
|
|
* control of resource utilization, Rx CQ 0 also works as
|
|
|
|
* Default CQ for async notifications
|
|
|
|
*/
|
|
|
|
if (!BNXT_NUM_ASYNC_CPR(bp) && !rx_queue_id) {
|
2018-06-28 20:15:35 +00:00
|
|
|
PMD_DRV_LOG(ERR, "Cannot stop Rx queue id %d\n", rx_queue_id);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
rxq = bp->rx_queues[rx_queue_id];
|
2019-11-13 08:29:45 +00:00
|
|
|
if (!rxq) {
|
2018-01-26 17:31:58 +00:00
|
|
|
PMD_DRV_LOG(ERR, "Invalid Rx queue %d\n", rx_queue_id);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2019-11-13 08:29:45 +00:00
|
|
|
vnic = rxq->vnic;
|
|
|
|
if (!vnic) {
|
|
|
|
PMD_DRV_LOG(ERR, "VNIC not initialized for RxQ %d\n",
|
|
|
|
rx_queue_id);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2018-01-26 17:31:58 +00:00
|
|
|
dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
|
2019-10-02 17:17:32 +00:00
|
|
|
rxq->rx_started = false;
|
2018-01-26 17:31:58 +00:00
|
|
|
PMD_DRV_LOG(DEBUG, "Rx queue stopped\n");
|
|
|
|
|
|
|
|
if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) {
|
2019-06-02 17:42:44 +00:00
|
|
|
if (BNXT_HAS_RING_GRPS(bp))
|
|
|
|
vnic->fw_grp_ids[rx_queue_id] = INVALID_HW_RING_ID;
|
2019-10-02 23:25:43 +00:00
|
|
|
|
|
|
|
PMD_DRV_LOG(DEBUG, "Rx Queue Count %d\n", vnic->rx_queue_cnt);
|
2019-11-04 20:27:44 +00:00
|
|
|
rc = bnxt_vnic_rss_configure(bp, vnic);
|
2018-01-26 17:31:58 +00:00
|
|
|
}
|
2018-06-28 20:15:35 +00:00
|
|
|
|
2019-11-04 20:27:47 +00:00
|
|
|
if (BNXT_CHIP_THOR(bp)) {
|
|
|
|
/* Compute current number of active receive queues. */
|
|
|
|
for (i = vnic->start_grp_id; i < vnic->end_grp_id; i++)
|
|
|
|
if (bp->rx_queues[i]->rx_started)
|
|
|
|
active_queue_cnt++;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* For Thor, we need to ensure that the VNIC default receive
|
|
|
|
* ring corresponds to an active receive queue. When no queue
|
|
|
|
* is active, we need to temporarily set the MRU to zero so
|
|
|
|
* that packets are dropped early in the receive pipeline in
|
|
|
|
* order to prevent the VNIC default receive ring from being
|
|
|
|
* accessed.
|
|
|
|
*/
|
|
|
|
if (active_queue_cnt == 0) {
|
|
|
|
uint16_t saved_mru = vnic->mru;
|
|
|
|
|
|
|
|
vnic->mru = 0;
|
|
|
|
/* Reconfigure default receive ring and MRU. */
|
|
|
|
bnxt_hwrm_vnic_cfg(bp, vnic);
|
|
|
|
vnic->mru = saved_mru;
|
|
|
|
} else {
|
|
|
|
/* Reconfigure default receive ring. */
|
|
|
|
bnxt_hwrm_vnic_cfg(bp, vnic);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-06-28 20:15:35 +00:00
|
|
|
if (rc == 0)
|
|
|
|
bnxt_rx_queue_release_mbufs(rxq);
|
|
|
|
|
|
|
|
return rc;
|
2018-01-26 17:31:58 +00:00
|
|
|
}
|