Commit Graph

883 Commits

Author SHA1 Message Date
Bruce Richardson
e83d41f069 mailmap: add list of contributors
Since a number of contributors to DPDK have submitted patches to DPDK
under more than one email address, we should maintain a mailmap file
to properly track their commits using "shortlog",
and to do accurate automatic Cc with "get_maintainer.pl".

It also helps fix up any mangled names, for example, with
surname/firstname reversed, or with incorrect capitalization.
By keeping this file in the DPDK repository,
rather than committers maintaining their own copies,
it allows individual contributors to edit it
to update their own email address preferences if so desired.

While at it, update our checkpatches.sh script
and add some documentation to help new contributors.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
2022-11-27 11:26:08 +01:00
Fan Zhang
1f0d0752bc maintainers: update for crypto and compressdev
Update email address.

Signed-off-by: Fan Zhang <fanzhang.oss@gmail.com>
2022-11-15 09:35:42 +01:00
Anoob Joseph
1f5cfe964e app/security-perf: add session performance test
Add performance application to test security session create & destroy
rates supported by the security enabled cryptodev PMD. The
application would create specified number of sessions and captures the
time taken for the same before proceeding to destroy of the same. When
operating on multi-core, the number of sessions would be evenly
distributed across all cores.

The application would test with all combinations of cipher & auth
algorithms supported by the PMD.

Signed-off-by: Aakash Sasidharan <asasidharan@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
2022-11-03 13:48:37 +01:00
Thomas Monjalon
d7b705b47f maintainers: update for pmdinfo tool
The original maintainer of pmdinfo/pmdinfogen
did not send an email for 2 years.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: David Marchand <david.marchand@redhat.com>
2022-11-14 11:30:39 +01:00
Thomas Monjalon
04fd724416 maintainers: group service cores files
Move example with library files, all with the same maintainer.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Harry van Haaren <harry.van.haaren@intel.com>
2022-11-14 11:30:39 +01:00
Juraj Linkeš
724b8a37be dts: add code formatting and check
The devtools that check Python code are Black and Isort to format the
code and Pylama to do static analysis.

Signed-off-by: Owen Hilyard <ohilyard@iol.unh.edu>
Signed-off-by: Juraj Linkeš <juraj.linkes@pantheon.tech>
2022-11-09 18:07:56 +01:00
Juraj Linkeš
bb5f299066 dts: add tools configuration
Add configuration for Python tools used in DTS:
Poetry, dependency and package manager
Black, formatter
Pylama, static analysis
Isort, import sorting

Signed-off-by: Owen Hilyard <ohilyard@iol.unh.edu>
Signed-off-by: Juraj Linkeš <juraj.linkes@pantheon.tech>
2022-11-09 18:07:56 +01:00
Jay Jayatheerthan
6a88cbc541 maintainers: update for eventdev Rx/Tx adapters
Harish is the new maintainer of Rx/Tx adapters due to role change of Jay.

Signed-off-by: Jay Jayatheerthan <jay.jayatheerthan@intel.com>
Acked-by: Naga Harish K S V <s.v.naga.harish.k@intel.com>
2022-10-31 17:17:02 +01:00
Junfeng Guo
549343c25d net/idpf: support device initialization
Support device init and add the following dev ops:
 - dev_configure
 - dev_close
 - dev_infos_get

Signed-off-by: Beilei Xing <beilei.xing@intel.com>
Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
2022-10-31 14:29:55 +01:00
Zhangfei Gao
8c515d9680 crypto/uadk: introduce HiSilicon UADK crypto driver
Introduce a new crypto PMD for hardware accelerators based on UADK [1].

UADK is a framework for user applications to access hardware accelerators.
UADK relies on IOMMU SVA (Shared Virtual Address) feature, which share
the same page table between IOMMU and MMU.
Thereby user application can directly use virtual address for device dma,
which enhances the performance as well as easy usability.

This patch adds the basic framework.

[1] https://github.com/Linaro/uadk

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: Akhil Goyal <gakhil@marvell.com>
2022-10-29 13:01:41 +02:00
Nicolas Chautru
c2d93488c7 baseband/acc200: introduce ACC200
Introduced stubs for device driver for the ACC200
integrated VRAN accelerator on SPR-EEC

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:38 +02:00
Nicolas Chautru
dcf43d2412 baseband/acc: rename directory from acc100 to acc
Used a common directory for the ACC PMDs

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-10-29 13:01:38 +02:00
Stephen Hemminger
7e017238f4 maintainers: update for Microsoft vmbus and netvsc
These are my last couple of days at Microsoft.
Remove the old email from MAINTAINERS.
Will no longer have free access to Azure to work on Netvsc.

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
2022-10-30 09:47:17 +01:00
David Marchand
9f81548430 flow_classify: mark library as deprecated
This library has no maintainer and, for now, nobody expressed interest
in taking over.
Mark this experimental library as deprecated and announce plan for
removal in v23.11.

Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Ferruh Yigit <ferruh.yigit@amd.com>
Acked-by: Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
2022-10-28 16:20:59 +02:00
Bruce Richardson
2993c839f5 maintainers: update for flow classification and IPsec
Bernard is no longer with Intel and is no longer involved in the DPDK
community, so remove him from the MAINTAINERS file.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: John McNamara <john.mcnamara@intel.com>
2022-10-28 16:20:57 +02:00
Ferruh Yigit
578e37908d net/mana: disable driver by default
Driver is disabled by default because its dependencies are not
upstreamed yet, code is available for development and investigation.

When all dependencies are upstreamed, driver can be enabled back.

Fixes: 517ed6e2d5 ("net/mana: add basic driver with build environment")

Signed-off-by: Ferruh Yigit <ferruh.yigit@amd.com>
Acked-by: Long Li <longli@microsoft.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
2022-10-27 10:54:53 +02:00
Junfeng Guo
457967cd2b net/gve: support device initialization
Support device init and add following devops skeleton:
 - dev_configure
 - dev_start
 - dev_stop
 - dev_close

Note that build system (including doc) is also added in this patch.

Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
2022-10-25 14:30:28 +02:00
Andrew Boyer
a5205992d9 net/ionic: update documentation and copyrights
Pensando Systems has been acquired by AMD.
Update all copyright strings and email addresses.

Signed-off-by: Andrew Boyer <andrew.boyer@amd.com>
2022-10-18 23:38:25 +02:00
Ray Kinsella
168a07eb97 maintainers: update for ABI management
Developer tools associated with ABI are maintained with as part of
developer tooling, EAL ABI headers are maintained with EAL,
ABI build scripts are maintained with the build system
and ABI policy and version documents along with rest of the documentation.

Major change is that individual components maintainers become
responsible for ensuring correctness of their map file(s).

Signed-off-by: Ray Kinsella <mdr@ashroe.eu>
2022-10-11 02:30:06 +02:00
Jasvinder Singh
f5dc752e6a maintainers: update for sched and softnic
I am removing myself as the maintainer of the sched library,
and softnic driver.

Signed-off-by: Jasvinder Singh <jasvinder.singh@intel.com>
2022-10-09 19:36:57 +02:00
Long Li
517ed6e2d5 net/mana: add basic driver with build environment
MANA is a PCI device. It uses IB verbs to access hardware through the
kernel RDMA layer. This patch introduces build environment and basic
device probe functions.

Signed-off-by: Long Li <longli@microsoft.com>
2022-10-06 10:49:00 +02:00
Min Zhou
29631ee5c8 eal/loongarch: support LoongArch architecture
Add all necessary elements for DPDK to compile and run EAL on
LoongArch64 Soc.

This includes:

- EAL library implementation for LoongArch ISA.
- meson build structure for 'loongarch' architecture.
  RTE_ARCH_LOONGARCH define is added for architecture identification.
- xmm_t structure operation stubs as there is no vector support in
  the current version for LoongArch.

Compilation was tested on Debian and CentOS using loongarch64
cross-compile toolchain from x86 build hosts. Functions were tested
on Loongnix and Kylin which are two Linux distributions supported
LoongArch host based on Linux 4.19 maintained by Loongson
Corporation.

We also tested DPDK on LoongArch with some external applications,
including: Pktgen-DPDK, OVS, VPP.

The platform is currently marked as linux-only because there is no
other OS than Linux support LoongArch host currently.

The i40e PMD driver is disabled on LoongArch because of the absence
of vector support in the current version.

Similar to RISC-V, the compilation of following modules has been
disabled by this commit and will be re-enabled in later commits as
fixes are introduced:
net/ixgbe, net/memif, net/tap, example/l3fwd.

Signed-off-by: Min Zhou <zhoumin@loongson.cn>
2022-10-06 12:45:05 +02:00
Bruce Richardson
3aaa46977d examples/kni: remove deprecated example
As part of the agreed process for deprecating KNI in DPDK, the example
app is scheduled for removal as part of the 22.11 release.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Stephen Hemminger <stephen@networkplumber.org>
2022-10-03 18:24:24 +02:00
Thomas Monjalon
0f91f952be replace Mellanox with NVIDIA
NVIDIA acquired Mellanox Technologies in 2020.
The DPDK documentation and code might still include instances
of or references to Mellanox trademarks (like BlueField and ConnectX)
that are now NVIDIA trademarks.

The PCI IDs and copyrights are unchanged.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Gal Cohen <galco@nvidia.com>
2022-10-03 16:01:56 +02:00
Bruce Richardson
8c76e2f693 raw/ioat: remove deprecated driver
The ioat driver has been superseded by the ioat and idxd dmadev drivers,
and has been deprecated for some time, so remove it.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
2022-09-28 14:41:07 +02:00
Ferruh Yigit
8841fbadda maintainers: update email address
Updating @xilinx.com domain to @amd.com domain.

Signed-off-by: Ferruh Yigit <ferruh.yigit@amd.com>
2022-09-28 14:19:59 +02:00
Sunil Uttarwar
12914ce519 maintainers: update for AMD CCP
Updating AMD CCP crypto maintainer

Signed-off-by: Sunil Uttarwar <sunilprakashrao.uttarwar@amd.com>
2022-09-28 14:19:59 +02:00
Fan Zhang
9f5f141627 maintainers: update for crypto and compressdev
Update maintainer and email address.

Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com>
Signed-off-by: Kai Ji <kai.ji@intel.com>
2022-09-28 14:19:54 +02:00
Stephen Hemminger
f3cd6803ac maintainers: update for Arm v7
Going over list of active DPDK developers and MAINTAINERS
and noticed that Jan's email was not active.

His response was:
"
The viktorin@rehivetech.com is no longer under my control.
As there is already another maintainer (Ruifeng Wang),
I would prefer and suggest to remove my address
from the maintainers entirely.
"

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
2022-09-28 13:24:41 +02:00
Sathesh Edara
423c8a2905 net/octeon_ep: rename octeontx_ep
This patch renames octeon end point driver from octeontx_ep to
octeon_ep to enable single unified driver to support current
OcteonTx and future Octeon PCI endpoint NICs to reflect common
driver for all Octeon based PCI endpoint NICs.

Signed-off-by: Sathesh Edara <sedara@marvell.com>
Acked-by: Veerasenareddy Burru <vburru@marvell.com>
2022-09-22 10:43:42 +02:00
Mattias Rönnblom
89832b4778 test/cksum: add checksum performance test
Add performance test for the rte_raw_cksum() function, which delegates
the actual work to __rte_raw_cksum(), which in turn is used by other
functions in need of Internet checksum calculation.

Signed-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
Acked-by: Olivier Matz <olivier.matz@6wind.com>
2022-09-20 18:09:16 +02:00
Veerasenareddy Burru
b3c781dbde maintainers: update for octeontx_ep driver
Remove Nalla Pradeep as co-maintainer of octeontx_ep driver.
Add Sathesh Edara as co-maintainer of octeontx_ep driver.

Signed-off-by: Veerasenareddy Burru <vburru@marvell.com>
2022-07-13 13:49:33 +02:00
Rahul Bhansali
732115ce38 examples/l3fwd: move packet group function in common
This will make the packet grouping function common, so
that other examples can utilize as per need.

For each architecture sse/neon/altivec, port group
headers will be created under examples/common/<arch>.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
Tested-by: Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>
Acked-by: Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>
2022-06-30 06:54:21 +02:00
Dongdong Liu
91c12c4a4a maintainers: update for hns3
Lijun Ou and Min Hu currently do not work for the hns3 PMD.
I will do the work, so update the hns3 maintainers.

Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
Acked-by: Yisen Zhuang <yisen.zhuang@huawei.com>
2022-06-24 13:10:01 +02:00
Nicolas Chautru
e466581254 baseband/acc100: introduce PMD for ACC101
Added support for ACC101 as a derivative of ACC100.
Integrated in unified driver and reusing existing code when possible.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
2022-06-21 20:04:49 +02:00
Xiaoyun Li
4ca8ee21b0 maintainers: update for testpmd
Resigning my maintainership for testpmd.

Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Acked-by: Yuying Zhang <yuying.zhang@intel.com>
2022-06-20 17:31:44 +02:00
David Marchand
e5e613f05b eal: remove unused arch-specific headers for locks
MCS lock, PF lock and Ticket lock have no arch specific implementation,
there is no need for the extra redirection in headers.

Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Stephen Hemminger <stephen@networkplumber.org>
Acked-by: Stanislaw Kardach <kda@semihalf.com>
2022-06-08 15:44:20 +02:00
Sean Morrissey
6de0ea50e9 examples/l3fwd: merge l3fwd-acl example
l3fwd-acl contains duplicate functions to l3fwd.
For this reason we merge l3fwd-acl code into l3fwd
with '--lookup acl' cmdline option to run ACL.

Signed-off-by: Sean Morrissey <sean.morrissey@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
2022-06-08 12:09:05 +02:00
Michal Mazurek
f22e705ebf eal/riscv: support RISC-V architecture
Add all necessary elements for DPDK to compile and run EAL on SiFive
Freedom U740 SoC which is based on SiFive U74-MC (ISA: rv64imafdc)
core complex.

This includes:

- EAL library implementation for rv64imafdc ISA.
- meson build structure for 'riscv' architecture. RTE_ARCH_RISCV define
  is added for architecture identification.
- xmm_t structure operation stubs as there is no vector support in the
  U74 core.

Compilation was tested on Ubuntu and Arch Linux using riscv64 toolchain.
Clang compilation currently not supported due to issues with missing
relocation relaxation.

Two rte_rdtsc() schemes are provided: stable low-resolution using rdtime
(default) and unstable high-resolution using rdcycle. User can override
the scheme by defining RTE_RISCV_RDTSC_USE_HPM=1 during compile time of
both DPDK and the application. The reasoning for this is as follows.
The RISC-V ISA mandates that clock read by rdtime has to be of constant
period and synchronized between all hardware threads within 1 tick
(chapter 10.1 in version 20191213 of RISC-V spec).
However this clock may not be of high-enough frequency for dataplane
uses. I.e. on HiFive Unmatched (FU740) it is 1MHz.
There is a high-resolution alternative in form of rdcycle which is
clocked at the core clock frequency. The drawbacks are that it may be
disabled during sleep (WFI), its frequency might change due to DVFS and
it is core-local and therefore cannot be used as a wall-clock. It can
however be used for micro-benchmarking user applications, similarly to
Aarch64's PMCCNTR PMU counter.

The platform is currently marked as linux-only because rte_cycles
implementation uses the timebase-frequency device-tree node read through
the proc file system. Such approach was chosen because Linux kernel
depends on the presence of this device-tree node.

The i40e PMD driver is disabled on RISC-V as the rv64gc ISA has no vector
operations.

The compilation of following modules has been disabled by this commit
and will be re-enabled in later commits as fixes are introduced:
net/ixgbe, net/memif, net/tap, example/l3fwd.

Sponsored-by: Frank Zhao <frank.zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
Signed-off-by: Michal Mazurek <maz@semihalf.com>
Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
2022-06-08 11:26:20 +02:00
Nipun Gupta
f434288d31 maintainers: update for NXP devices
Update and add maintainers for NXP devices and RAW device API.

Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
2022-06-07 20:49:20 +02:00
Mattias Rönnblom
0bee070907 eal: add seqlock
A sequence lock (seqlock) is a synchronization primitive which allows
for data-race free, low-overhead, high-frequency reads, suitable for
data structures shared across many cores and which are updated
relatively infrequently.

A seqlock permits multiple parallel readers. A spinlock is used to
serialize writers. In cases where there is only a single writer, or
writer-writer synchronization is done by some external means, the
"raw" sequence counter type (and accompanying rte_seqcount_*()
functions) may be used instead.

To avoid resource reclamation and other issues, the data protected by
a seqlock is best off being self-contained (i.e., no pointers [except
to constant data]).

One way to think about seqlocks is that they provide means to perform
atomic operations on data objects larger than what the native atomic
machine instructions allow for.

DPDK seqlocks (and the underlying sequence counters) are not
preemption safe on the writer side. A thread preemption affects
performance, not correctness.

A seqlock contains a sequence number, which can be thought of as the
generation of the data it protects.

A reader will
  1. Load the sequence number (sn).
  2. Load, in arbitrary order, the seqlock-protected data.
  3. Load the sn again.
  4. Check if the first and second sn are equal, and even numbered.
     If they are not, discard the loaded data, and restart from 1.

The first three steps need to be ordered using suitable memory fences.

A writer will
  1. Take the spinlock, to serialize writer access.
  2. Load the sn.
  3. Store the original sn + 1 as the new sn.
  4. Perform load and stores to the seqlock-protected data.
  5. Store the original sn + 2 as the new sn.
  6. Release the spinlock.

Proper memory fencing is required to make sure the first sn store, the
data stores, and the second sn store appear to the reader in the
mentioned order.

The sn loads and stores must be atomic, but the data loads and stores
need not be.

The original seqlock design and implementation was done by Stephen
Hemminger. This is an independent implementation, using C11 atomics.

For more information on seqlocks, see
https://en.wikipedia.org/wiki/Seqlock

Acked-by: Morten Brørup <mb@smartsharesystems.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Reviewed-by: Ola Liljedahl <ola.liljedahl@arm.com>
Reviewed-by: Chengwen Feng <fengchengwen@huawei.com>
Signed-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
2022-06-07 13:33:14 +02:00
Akhil Goyal
86e2487c5f test/security: add cases for inline IPsec offload
A new test suite is added in test app to test inline IPsec protocol
offload. In this patch, predefined vectors from Lookaside IPsec test
are used to verify the IPsec functionality without the need of
external traffic generators. The sent packet is loopbacked onto the same
interface which is received and matched with the expected output.
The test suite can be updated further with other functional test cases.
In this patch encap only cases are added.
The testsuite can be run using:
RTE> inline_ipsec_autotest

Signed-off-by: Akhil Goyal <gakhil@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
2022-06-01 16:26:34 +02:00
Chaoyong He
d7c455232a maintainers: update for nfp
Add Chaoyong as nfp maintainer.

Signed-off-by: Chaoyong He <chaoyong.he@corigine.com>
Signed-off-by: Niklas Söderlund <niklas.soderlund@corigine.com>
2022-06-01 08:58:27 +02:00
Nipun Gupta
8caf8427f8 dma/dpaa2: introduce driver skeleton
The DPAA2 DMA  driver is an implementation of the dmadev APIs,
that provide means to initiate a DMA transaction from CPU.
Earlier this was part of RAW driver, but with DMA drivers
added as separate flavor of drivers, this driver is being
moved to DMA drivers.

Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
2022-06-01 08:58:27 +02:00
Nipun Gupta
33584c19dd raw/dpaa2_qdma: remove driver
With DMA devices supported as a separate flavor of devices,
the DPAA2 QDMA driver is moved in the DMA devices.

This change removes the DPAA2 QDMA driver from raw devices.

Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
2022-06-01 08:58:27 +02:00
Tyler Retzlaff
04e53de9e5 test/threads: add unit test
Establish unit test for testing thread api. Initial unit tests
for rte_thread_{get,set}_affinity_by_id().

Signed-off-by: Narcisa Vasile <navasile@linux.microsoft.com>
Signed-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
2022-05-19 16:45:07 +02:00
Beilei Xing
36db4a1ad4 maintainers: update for Intel i40e
Add Yuying as Intel i40e maintainer.

Signed-off-by: Beilei Xing <beilei.xing@intel.com>
Acked-by: Yuying Zhang <yuying.zhang@intel.com>
2022-05-10 11:32:39 +02:00
Haiyue Wang
cbfcdb37af maintainers: update for Intel igc
Junfeng and Simei have been appointed the new maintainers for the igc
PMD. Update the MAINTAINERS file to reflect this.

Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Simei Su <simei.su@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2022-05-10 11:32:37 +02:00
Haiyue Wang
f014ad9953 maintainers: update for Intel ixgbe
Qiming and Wenjun have been appointed the new maintainers for the ixgbe
PMD. Update the MAINTAINERS file to reflect this.

Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Acked-by: Wenjun Wu <wenjun1.wu@intel.com>
2022-05-10 11:32:36 +02:00
Haiyue Wang
789106f008 maintainers: update for Intel e1000
Simei and Wenjun have been appointed the new maintainers for the e1000
PMD. Update the MAINTAINERS file to reflect this.

Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Simei Su <simei.su@intel.com>
Acked-by: Wenjun Wu <wenjun1.wu@intel.com>
2022-05-10 11:32:31 +02:00