Starting with commit 9aa2053c6e81493b23346ff4e387903560de5c81
EXTRA_CFLAGS is sometimes being passed to the compiler without
WERROR_FLAGS which can cause spurious warnings by the dozen,
for example with when compiling with EXTRA_CFLAGS="-Wformat-security":
cc1: warning: -Wformat-security ignored without -Wformat [-Wformat-security]
Passing WERROR_FLAGS to AUTO_CPU helper makes the warning flag usage
consistent throughout the codebase, silencing the warnings.
Fixes: 9aa2053c6e81 ("mk: influence CPU flags with user input")
Signed-off-by: Panu Matilainen <pmatilai@redhat.com>
Acked-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
We have encountered a CPU where the AES-NI instruction set is disabled
due to export restrictions. Since the build machine and target machine
is different, using -native configs doesn't work, and on this CPU, the
application refuses to run due to the AES CPU flags being amiss.
The patch passes EXTRA_CFLAGS to the figure-out-cpu-flags helper,
which allows us to add -mno-aes to the compile flags and resolve this
problem.
Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
Acked-by: Olivier Matz <olivier.matz@6wind.com>
armv8-a has optional CRC32 extension, march=armv8-a+crc enables code
generation for the ARMv8-A architecture together with
the optional CRC32 extensions.
added RTE_MACHINE_CPUFLAG_CRC32 to detect the availability of
CRC32 extension in compile time. At run-time, The RTE_CPUFLAG_CRC32
can be used to find the availability.
armv8-a+crc target support added in GCC 4.9,
Used inline assembly and emulated __ARM_FEATURE_CRC32 to work
with tool-chain < 4.9
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
This implementation is based on IBM POWER version of
rte_cpuflags. We use software emulation of HW capability
registers, because those are usually not directly accessible
from userspace on ARM.
Signed-off-by: Vlastimil Kosar <kosar@rehivetech.com>
Signed-off-by: Jan Viktorin <viktorin@rehivetech.com>
Acked-by: David Marchand <david.marchand@6wind.com>
IBM Power processor doesn't have CPU flag hardware registers. This patch
uses aux vector software register to get CPU flags and add CPU flag
checking support for IBM Power architecture.
Signed-off-by: Chao Zhu <chaozhu@linux.vnet.ibm.com>
Acked-by: David Marchand <david.marchand@6wind.com>
This commit removes trailing whitespace from lines in files. Almost all
files are affected, as the BSD license copyright header had trailing
whitespace on 4 lines in it [hence the number of files reporting 8 lines
changed in the diffstat].
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Neil Horman <nhorman@tuxdriver.com>
[Thomas: remove spaces before tabs in libs]
[Thomas: remove more trailing spaces in non-C files]
Signed-off-by: Thomas Monjalon <thomas.monjalon@6wind.com>
For cases where the compilation microarchitecture is explicitly given, we
extract the cpu-flags to use from the compiler rather than hard-coding. This
means that we will only ever use instruction sets supported by the compiler,
rather than having a case where the uarch and the Intel DPDK both support a
given instruction-set, but the compiler does not.
In the case where 'native' uarch support is requested, the same mechanism is
also used to detect the instruction-sets supported
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Signed-off-by: David Marchand <david.marchand@6wind.com>
