The new software manged entity is introduced in Tx datapath
- free on completion queue. This queue keeps the information
how many buffers stored in elts array must freed on send
completion. Each element of the queue contains transmitting
descriptor index to be in synch with completion entries (in
debug build only) and the index in elts array to free buffers.
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
This is preparation step, we are going to store the index
of elts to free on completion in the dedicated free on
completion queue, this patch updates the elts freeing routine
and updates Tx error handling routine to be synced with
coming new queue.
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
The complete request flag is set once per Tx burst call,
the code of appropriate routine moved to the end of sending
loop. This is preparation step to remove WQE reserved field
usage to store index of elts to free.
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Add support for reading the firmware version.
Signed-off-by: Alfredo Cardigliano <cardigliano@ntop.org>
Reviewed-by: Shannon Nelson <snelson@pensando.io>
Add basic, per queue and extended statistics for
RX and TX, both from the adapter and the driver.
Signed-off-by: Alfredo Cardigliano <cardigliano@ntop.org>
Reviewed-by: Shannon Nelson <snelson@pensando.io>
Add code to manipulate the RSS configuration
used by the adapter.
Signed-off-by: Alfredo Cardigliano <cardigliano@ntop.org>
Reviewed-by: Shannon Nelson <snelson@pensando.io>
Add support for managing RX filters based on MAC and VLAN.
Hardware cannot provide the list of filters, thus we keep
a local list.
Add support for promisc and allmulticast modes.
Signed-off-by: Alfredo Cardigliano <cardigliano@ntop.org>
Reviewed-by: Shannon Nelson <snelson@pensando.io>
Add support for port start/stop and handle basic features
including MTU and link up/down.
Signed-off-by: Alfredo Cardigliano <cardigliano@ntop.org>
Reviewed-by: Shannon Nelson <snelson@pensando.io>
Add support for the notify queue, which is used for events
published by the NIC.
Signed-off-by: Alfredo Cardigliano <cardigliano@ntop.org>
Reviewed-by: Shannon Nelson <snelson@pensando.io>
Add support for the admin queue, which is used for most
of the NIC configurations.
Signed-off-by: Alfredo Cardigliano <cardigliano@ntop.org>
Reviewed-by: Shannon Nelson <snelson@pensando.io>
Doorbell registers are used by the driver to signal to the NIC
that requests are waiting on the message queues.
Signed-off-by: Alfredo Cardigliano <cardigliano@ntop.org>
Reviewed-by: Shannon Nelson <snelson@pensando.io>
Initialize LIFs (Logical Interfaces) which represents
external connections. The NIC can multiplex many LIFs
to a single port, but in most setups, LIF0 is the
primary control for the port.
Create a device for each LIF.
Signed-off-by: Alfredo Cardigliano <cardigliano@ntop.org>
Reviewed-by: Shannon Nelson <snelson@pensando.io>
Add port management commands that apply to the physical
ports associated with the PCI device, which might be
shared among several logical interfaces.
Signed-off-by: Alfredo Cardigliano <cardigliano@ntop.org>
Reviewed-by: Shannon Nelson <snelson@pensando.io>
Register the Pensando ionic PMD (net_ionic) and define initial probe
and remove callbacks with adapter initialization.
Signed-off-by: Alfredo Cardigliano <cardigliano@ntop.org>
Reviewed-by: Shannon Nelson <snelson@pensando.io>
Add debug options to the config file.
Define macros used for logs and make use of config file options
to enable them.
Signed-off-by: Alfredo Cardigliano <cardigliano@ntop.org>
Reviewed-by: Shannon Nelson <snelson@pensando.io>
Add makefile and config file options to compile the Pensando ionic PMD.
Add feature and version map file.
Update maintainers file.
Signed-off-by: Alfredo Cardigliano <cardigliano@ntop.org>
Reviewed-by: Shannon Nelson <snelson@pensando.io>
V1000/R1000 processors are using the same PCI ids for the network
device as SNOWYOWL processor but has altered register definitions
for determining the window settings for the indirect PCS access.
Add support to check for this hardware and if found use the new
register values.
Signed-off-by: Selwin Sebastian <selwin.sebastian@amd.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
In the Rx datapath the flags in the newly allocated mbufs
are all explicitly cleared but the EXT_ATTACHED_MBUF must be
preserved. It would allow to use mbuf pools with pre-attached
external data buffers.
The vectorized rx_burst routines are updated in order to
inherit the EXT_ATTACHED_MBUF from mbuf pool private
RTE_PKTMBUF_POOL_F_PINNED_EXT_BUF flag.
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Use new marker typedef available in EAL.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Acked-by: Matan Azrad <matan@mellanox.com>
The version of the PMD should not be overwritten with LIBABIVER.
All internal libs must have the same version.
Moreover, specifying LIBABIVER in the driver causes a symbolic link loop:
librte_rawdev_octeontx2_ep.so.1 -> librte_rawdev_octeontx2_ep.so.1
Fixes: 56d46d13f736 ("raw/octeontx2_ep: add build infra and device probe")
Reported-by: Ferruh Yigit <ferruh.yigit@intel.com>
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Tested-by: Ferruh Yigit <ferruh.yigit@intel.com>
All buffers and ring info should be written before tail register update.
This patch relocates the write memory barrier before updating tail register
to avoid potential issues.
Fixes: 11b5c7daf019 ("raw/ntb: add enqueue and dequeue functions")
Cc: stable@dpdk.org
Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Acked-by: Jingjing Wu <jingjing.wu@intel.com>
Add rawdev's selftest feature in SDP VF driver, which
verifies the EP mode functionality test.
Signed-off-by: Mahipal Challa <mchalla@marvell.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Register "dev_configure" API to configure/initialize the SDP
VF PCIe devices.
Signed-off-by: Mahipal Challa <mchalla@marvell.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Add the OCTEON TX2 SDP EP device probe along with the
build infrastructure for Make and meson builds.
Signed-off-by: Mahipal Challa <mchalla@marvell.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Add pmd unix socket server to enable external tool applications to
trigger flow dump.
Socket path:
/var/tmp/dpdk_mlx5_<pid>
Socket format:
io_raw: port_id of uint16
file: file descriptor of int
Signed-off-by: Xueming Li <xuemingl@mellanox.com>
Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Dump fdb/nic_rx/nic_tx raw flow data into specified file.
Signed-off-by: Xueming Li <xuemingl@mellanox.com>
Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
The mlx5 datapath does not implement any endianness conversions
for the metadata being sent and received to provide the better
performance (because these conversions would be performed for
each packet). These metadata are also involved into flow processing
(there might be some flows matching on metadata patterns or setting
the new metadata values) inside the NIC. It order to configure
hardware in correct way all necessary endianness conversions are
done by rte_flow handling code (only once on flow creation). This
patch fixes one of these conversions for the little-endian hosts
in case if META/MARK items are less than 32 bits.
Fixes: acfcd5c52f94 ("net/mlx5: update meta register matcher set")
Cc: stable@dpdk.org
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Matcher is flow table related structure providing the flow pattern
to be translated directly in hardware controlling data. This structure
includes the metadata register c0 field, that might be engaged to
support META and MARK related flow items and actions. Also, this
register might be used by kernel to specify the source vport index.
In this case (if kernel uses the field) the register c0 is split
into two 16-bit subfields - one for META/MARK items and another
to handle vport.
The actual configuration is queried by PMD from kernel in runtime
and depending on the mask returned by kernel the PMD can use upper
or lower half of register c0 field. This patch adds the missing
support for upper half. This missed support caused the non-operational
META/MARK items on some kernel configurations.
Fixes: e554b672aa05 ("net/mlx5: support flow tag")
Cc: stable@dpdk.org
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Matcher is flow table related structure providing the flow pattern
to be translated directly in hardware controlling data. Some fields
in this structure might be split (by software) between multiple items.
For example, the metadata register c0 field in the matcher might be
split into two independent subfields - the source vport index and
META item value. These subfields have no permanent assigned masks,
the actual configuration is queried from the kernel drivers in
runtime. To handle source vport value (the port of e-Switch which
is origin of the packet) the kernel might use the dedicated vport
field in the matcher or the part of register c0 field, depending
on configuration.
To setup the matcher structure fields the macro MLX5_SET is used.
MLX5_SET configures the specified 32-bit field as whole entity.
For metadata register c0 we should take into account the provided
mask in order to configure the specified subfield bits only,
otherwise setting vport overrides the META values and vice versa.
Fixes: acfcd5c52f94 ("net/mlx5: update meta register matcher set")
Cc: stable@dpdk.org
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Added CL37 Auto-neg support for 1Gbps interface in axgbe DPDK driver
Signed-off-by: Girish Nandibasappa <girish.nandibasappa@amd.com>
Acked-by: Ravi Kumar <ravi1.kumar@amd.com>
Added support for 1Gbps and 2.5Gbps in axgbe dpdk driver
Signed-off-by: Girish Nandibasappa <girish.nandibasappa@amd.com>
Acked-by: Ravi Kumar <ravi1.kumar@amd.com>
Add warning and counter to handle the malicious driver detection (MDD)
event.
When the hardware determines that a malicious driver on VF, this VF will
become unworkable, the PF records and gives a warning message.
Signed-off-by: Tao Zhu <taox.zhu@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
Because the rte layer of DPDK framework has already processed the case
when the idx is zero before calling the '.mac_addr_remove' ops function,
the input parameter named idx can not be zero in the '.mac_addr_remove'
function. This patch removes unnecessary branch process to check whether
input parameter named idx is zero in the '.mac_addr_remove' ops
implementation function named hns3_remove_mac_addr.
Signed-off-by: Lijun Ou <oulijun@huawei.com>
Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
Since the input parameter named dev has been guaranteed not to be NULL
in the rte layer of DPDK framework, it doesn't need to check dev whether
is null in the 'filter_ctrl' ops implementation function named
hns3_dev_filter_ctrl.
Signed-off-by: Lijun Ou <oulijun@huawei.com>
Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
This patch optimizes the Rx performance by using data dependency
ordering to instead of memory barrier which is rte_cio_rmb in the
'.rx_pkt_burst' ops implementation function named hns3_recv_pkts.
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
The JUMBO frame handling in dpaa_dev_mtu_set api was not correct.
When frame_size is greater than RTE_ETHER_MAX_LEN, the
intention is to add JUMBO flag in rx offload while it was resetting
all other flags other than JUMBO as AND operator was used instead of OR.
Fixes: 0ebce6129bc6 ("net/dpaa2: support new ethdev offload APIs")
Cc: stable@dpdk.org
Signed-off-by: Apeksha Gupta <apeksha.gupta@nxp.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
Use PCI_PRI_FMT instead of "%04d:%02d:%02d:%d" print format.
Signed-off-by: Yunjian Wang <wangyunjian@huawei.com>
Acked-by: Heinrich Kuhn <heinrich.kuhn@netronome.com>
add fill_ip6_head()
hardcode udp destination port to 4500
handle ESP and AH pctypes in ESP-AH profile
update the i40e user guide with ESP information.
update release notes for i40e changes
Signed-off-by: Bernard Iremonger <bernard.iremonger@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
Add flow structures for the following patterns in i40e_ethdev files:
eth/ipv4/esp
eth/ipv6/esp
eth/ipv4/udp/esp
eth/ipv6/esp/udp
add oip_type in filter
add is_udp in filter
use tenant_id in filter for spi
Signed-off-by: Bernard Iremonger <bernard.iremonger@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
