Commit Graph

3037 Commits

Author SHA1 Message Date
Jingjing Wu
3c8b18c416 net/i40e/base: avoid reset timeout issue
This patch allows detection of upcoming core reset in case NIC gets
stuck while performing FLR reset. The i40e_pf_reset() function returns
I40E_ERR_NOT_READY when global reset was detected.

Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
2017-07-06 15:00:57 +02:00
Jingjing Wu
156e15b5f7 net/i40e/base: avoid potential null pointer dereference
Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
2017-07-06 15:00:57 +02:00
Jingjing Wu
da499ab41b net/i40e/base: use admin queue for setting LEDs behavior
Instead of accessing register directly, use newly added AQC in
order to blink LEDs. Introduce and utilize a new flag to prevent
excessive API version checking.

Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
2017-07-06 15:00:57 +02:00
Jingjing Wu
6da598714a net/i40e/base: support switch parameters
Adds double VLAN tagging ethertype fields to Set Switch Parameters AQ
command.  These were added in firmware API 1.7.

Callers of i40e_aq_set_switch_config() can specify the ethertypes to
use by filling out the corresponding fields in struct i40e_hw.

Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
2017-07-06 15:00:57 +02:00
Jingjing Wu
7b8a3cc5df net/i40e/base: update FW AQ API version to 1.7
Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
2017-07-06 15:00:57 +02:00
Jingjing Wu
212cd71aac net/i40e/base: track id can be 0
track_id == 0 is valid for “read only” profiles when
profile does not have any “write” commands.

Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
2017-07-06 15:00:57 +02:00
Jingjing Wu
e8228f1a16 net/i40e/base: report supported link modes
Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
2017-07-06 15:00:57 +02:00
Jingjing Wu
aa153cc89f net/i40e/base: add new PHY types for 25G AOC and ACC
This patch adds new phy types for 25G Active Optical Cables (AOC) and
Active Copper Cables (ACC) support.

Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
2017-07-06 15:00:57 +02:00
Jingjing Wu
1216fb9f0c net/i40e/base: store the requested FEC information
Store information about FEC modes, that were requested. It will be used
in printing link status information function and this way there is no
need to call admin queue there.

Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
2017-07-06 15:00:56 +02:00
Jingjing Wu
606fe321ab net/i40e/base: add support for Adaptive Virtual Function
Add device id define and mac_type assignment needed for Adaptive
Virtual Function.

Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
2017-07-06 15:00:56 +02:00
Jingjing Wu
83b0670010 net/i40e/base: add AQ command for read/write PHY registers
This patch adds new additional command for accessing to PHY registers.

Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
2017-07-06 15:00:56 +02:00
Jingjing Wu
671f126978 net/i40e/base: sync nvmupdate command and adminq subtask
During NVMupdate, state machine gets into unrecoverable state because
i40e_clean_adminq_subtask can get scheduled after the admin queue
command but before other state variables are updated.

This patch adds locking around admin queue command and update of
state variables so that adminq_subtask will have accurate information
whenever it gets scheduled.

Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
2017-07-06 15:00:56 +02:00
Jingjing Wu
a58860f689 net/i40e/base: use new virtchnl header file
Modify the necessary files to be compatible with the new virtchnl.h file
instead of relying on i40e_virtchnl.h variant. This mostly changes
references to VIRTCHNL_ variables by removing prefix of I40E_.

Signed-off-by: Jingjing Wu <jingjing.wu@intel.com>
2017-07-06 15:00:56 +02:00
Sha Zhang
95efa3cd64 net/bonding: fix when NTT flag updated
According to the standard, state machine of LACP should transmit lacpdu
when partner's state changes from slow to fast, rather than from fast
to slow.

Fixes: 46fb436836 ("bond: add mode 4")
Cc: stable@dpdk.org

Signed-off-by: Sha Zhang <zhangsha.zhang@huawei.com>
Acked-by: Declan Doherty <declan.doherty@intel.com>
2017-07-06 15:00:56 +02:00
Olivier Matz
2209c3e2c2 net/i40e: avoid PCI probing failure when using bogus SFP
When a port is using a bogus SFP, the PCI probing returns an error,
preventing to register a portid.

To give a better chance to the applications to retry after the SFP is
changed, move this check in eth_i40e_dev_configure(), so that only a
port reconfiguration is needed to retry.

Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
Acked-by: Jingjing Wu <jingjing.wu@intel.com>
2017-07-06 15:00:56 +02:00
Hemant Agrawal
774e9ea919 net/dpaa2: add support for multi seg buffers
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
2017-07-06 15:00:56 +02:00
Hemant Agrawal
29dfa62f5f net/dpaa2: add support for frame based Tx congestion
Change from byte based to frame based.

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
2017-07-06 15:00:56 +02:00
Hemant Agrawal
4260d5038c net/dpaa2: disable Tx congestion notification
Making it off by default.

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
2017-07-06 15:00:56 +02:00
Hemant Agrawal
30db823e04 net/dpaa2: check SoC version for stashing enable
Instead of qbman version, check the SoC version for stashing
enablement decision.

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
2017-07-06 15:00:56 +02:00
Hemant Agrawal
599017a215 net/dpaa2: align the queue numbers with MC firmware
Align dpaa2 PMD driver code to the way MC Firmware manages queues.

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
2017-07-06 15:00:56 +02:00
Hemant Agrawal
7cc4d35af5 net/dpaa2: set data align option in MC firmware
Configuring the MC FW to configure data alignment by default.
This help in improving performance for some of the platform variants.

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
2017-07-06 15:00:56 +02:00
Hemant Agrawal
55fd270311 net/dpaa2: set device driver
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
2017-07-06 15:00:56 +02:00
Beilei Xing
6562269ca6 net/i40e: fix flow director for IPv6
After adding a fdir rule for IPv6 with input set TC, IPv6 packets
with the specific TC can't be assigned the right queue.
The root cause is that TC is parsed wrongly, this patch fixes
TC parsing problem.

Fixes: 7d83c152a2 ("net/i40e: parse flow director filter")
Cc: stable@dpdk.org

Signed-off-by: Beilei Xing <beilei.xing@intel.com>
Tested-by: Yuan Peng <yuan.peng@intel.com>
2017-07-06 15:00:56 +02:00
Xiao Wang
20c0a0c4e8 net/fm10k: initialize link status in device start
Fm10k host driver can't manage PHY directly and provides a fake link
status by always reporting LINK_UP. We should initialize link status
in device start, otherwise application will get LINK_DOWN status
when LSC configured.

Fixes: 9ae6068c86 ("fm10k: add dev start/stop")
Cc: stable@dpdk.org

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Jing Chen <jing.d.chen@intel.com>
2017-07-06 15:00:56 +02:00
Ivan Malov
84a9b48128 net/sfc: support flow API isolated mode
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
2017-07-06 15:00:56 +02:00
Shahaf Shuler
83daf156a9 net/mlx5: fix TSO segment size
In case on multi segment packet, the TSO segment size
was taken from the last segment. This may lead to incorrect
values in case not all segments are initialized with the field.

Fixing it by taking the value from the first segment.

Fixes: 3f13f8c23a ("net/mlx5: support hardware TSO")
Cc: stable@dpdk.org

Signed-off-by: Shahaf Shuler <shahafs@mellanox.com>
Acked-by: Yongseok Koh <yskoh@mellanox.com>
Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
2017-07-06 15:00:56 +02:00
Adrien Mazarguil
2d449f7c52 net/mlx4: fix assertion failure on link update
The interrupt handler can sometimes be triggered for reasons other than a
link status event. An assertion failure happen when such events occur while
an asynchronous link status update is already scheduled.

Address this issue using the same approach as its mlx5 counterpart,
commit a9f2fbc42f ("net/mlx5: fix inconsistent link status")

Fixes: c4da6caa42 ("mlx4: handle link status interrupts")
Cc: stable@dpdk.org

Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
2017-07-06 15:00:56 +02:00
Wei Zhao
d68e62c67b net/igb: fix flex filter length
igb flex filter supports recognizing any arbitrary pattern within first
128 bytes of the packet.

But the macro E1000_FLEX_FILTERS_MASK_SIZE only covers first 64 bytes.

Fixes: 231d43909a ("igb: migrate flex filter to new API")
Cc: stable@dpdk.org

Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
2017-07-06 15:00:56 +02:00
Wei Zhao
b2f68ff876 net/igb: fix flex type filter
There is a bug in flex type filter parsing because of wrong local
variable index usage.

Bug cause filter to fail and wrong mask calculation.

Fixes: 7cd77faf71 ("net/igb: parse flow API flex filter")

Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
2017-07-06 15:00:56 +02:00
Adrien Mazarguil
e1016cb733 net/mlx5: fix Rx interrupts management
This commit addresses various issues that may lead to undefined behavior
when configuring Rx interrupts.

While failure to create a Rx queue completion channel in rxq_ctrl_setup()
prevents that queue from being created, existing queues still have theirs.
Since the error handler disables dev_conf.intr_conf.rxq as well, subsequent
calls to rxq_ctrl_setup() create Rx queues without interrupts. This leads
to a scenario where not all Rx queues support interrupts; missing checks on
the presence of completion channels may crash the application.

Considering that the PMD is not supposed to disable user-provided
configuration parameters (dev_conf.intr_conf.rxq), and that these can
change for subsequent rxq_ctrl_setup() calls anyway, properly supporting a
mixed mode where not all Rx queues have interrupts enabled is a better
approach.

To do so with a minimum set of changes, priv_intr_efd_enable() and
priv_create_intr_vec() are first refactored as a single
priv_rx_intr_vec_enable() function (same for their "disable" counterparts).
Since they had to be used together, there was no point in keeping them
separate.

Remaining changes:

- Always clean up before reconfiguring interrupts to avoid memory leaks.
- Always clean up when closing the device.
- Use malloc()/free() instead of their rte_*() counterparts since there is
  no need to store the vector in huge pages-backed memory.
- Allow more Rx queues than the size of the event file descriptor array as
  long as Rx interrupts are not requested on all of them.
- Properly clean up interrupt handle when disabling Rx interrupts (nb_efd
  and intr_vec reset to 0).
- Check completion channel presence while toggling Rx interrupts on a given
  queue.

Fixes: 3c7d44af25 ("net/mlx5: support user space Rx interrupt event")
Cc: stable@dpdk.org

Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
2017-07-06 15:00:56 +02:00
Adrien Mazarguil
ad883aa293 net/mlx5: fix return value in Rx interrupts code
A negative return value is documented for that function in case of error.

Fixes: 3c7d44af25 ("net/mlx5: support user space Rx interrupt event")
Cc: stable@dpdk.org

Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
2017-07-06 15:00:56 +02:00
Adrien Mazarguil
9f91fb5483 net/mlx5: fix Rx interrupts support checks
Not exposing Rx interrupts callbacks when this feature is unsupported is
less intrusive than having two different versions for these functions.

Fixes: 3c7d44af25 ("net/mlx5: support user space Rx interrupt event")
Cc: stable@dpdk.org

Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
2017-07-06 15:00:56 +02:00
Adrien Mazarguil
b18042fb8f net/mlx5: fix misplaced Rx interrupts functions
These functions do not belong to the data path. Their prototypes are also
misplaced.

Fixes: 3c7d44af25 ("net/mlx5: support user space Rx interrupt event")
Cc: stable@dpdk.org

Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
2017-07-06 15:00:56 +02:00
Adrien Mazarguil
0a2ae70319 net/mlx4: fix Rx interrupts management
This commit addresses various issues that may lead to undefined behavior
when configuring Rx interrupts.

While failure to create a Rx queue completion channel in rxq_setup()
prevents that queue from being created, existing queues still have theirs.
Since the error handler disables dev_conf.intr_conf.rxq as well, subsequent
calls to rxq_setup() create Rx queues without interrupts. This leads to a
scenario where not all Rx queues support interrupts; missing checks on the
presence of completion channels may crash the application.

Considering that the PMD is not supposed to disable user-provided
configuration parameters (dev_conf.intr_conf.rxq), and that these can
change for subsequent rxq_setup() calls anyway, properly supporting a mixed
mode where not all Rx queues have interrupts enabled is a better approach.

To do so with a minimum set of changes, priv_intr_efd_enable() and
priv_create_intr_vec() are first refactored as a single
priv_rx_intr_vec_enable() function (same for their "disable" counterparts).
Since they had to be used together, there was no point in keeping them
separate.

Remaining changes:

- Always clean up before reconfiguring interrupts to avoid memory leaks.
- Always clean up when closing the device.
- Use malloc()/free() instead of their rte_*() counterparts since there is
  no need to store the vector in huge pages-backed memory.
- Allow more Rx queues than the size of the event file descriptor array as
  long as Rx interrupts are not requested on all of them.
- Properly clean up interrupt handle when disabling Rx interrupts (nb_efd
  and intr_vec reset to 0).
- Check completion channel presence while toggling Rx interrupts on a given
  queue.

Fixes: 9f05a4b818 ("net/mlx4: support user space Rx interrupt event")

Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
Acked-by: Moti Haimovsky <motih@mellanox.com>
2017-07-06 15:00:56 +02:00
Adrien Mazarguil
3c560ec3ea net/mlx4: fix Rx interrupts with multiple ports
Several Ethernet device structures are allocated on top of a common PCI
device for mlx4 adapters with multiple ports. These inherit a common
interrupt handle from their parent PCI device, which prevents Rx interrupts
from working properly on all ports as their configuration is overwritten.

Use a local interrupt handle to address this issue.

Fixes: 9f05a4b818 ("net/mlx4: support user space Rx interrupt event")

Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
Acked-by: Moti Haimovsky <motih@mellanox.com>
2017-07-06 15:00:56 +02:00
Adrien Mazarguil
1a3e40d5a4 net/mlx4: fix typos from prior commit
Fixes: 9f05a4b818 ("net/mlx4: support user space Rx interrupt event")

Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
Acked-by: Moti Haimovsky <motih@mellanox.com>
2017-07-06 15:00:56 +02:00
Andrey Chilikin
edeab742ed net/i40e: get information about DDP profile
This patch adds ability to request information about dynamic device
personalization (DDP) profile.

Signed-off-by: Andrey Chilikin <andrey.chilikin@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
2017-07-06 15:00:56 +02:00
Pascal Mazon
f503d26948 net/tap: support flow API isolated mode
With this patch, it is possible to enable or disable the isolate
feature anytime, even immediately after a probe while the tap has not
been configured yet. It will do its job as soon as the netdevice gets
created.

A specific implicit flow rule is created with the lowest priority (all
other flow rules will be evaluated before), at the end of the list. If
isolated mode is enabled, the associated action will be to drop the
packet. Otherwise, the action would be passthrough.

In case of a remote netdevice, implicit rules on it will be removed in
isolated mode, to ensure only actual flow rules redirect packets to the
tap.

Signed-off-by: Pascal Mazon <pascal.mazon@6wind.com>
2017-07-06 15:00:56 +02:00
Nélio Laranjeiro
51d5f8ec95 net/mlx5: implement isolated mode from flow API
Signed-off-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
Acked-by: Shahaf Shuler <shahafs@mellanox.com>
2017-07-06 15:00:56 +02:00
Nélio Laranjeiro
6eddd9d65b net/mlx5: fix creation of drop flows
Drop flows being created when the port is stop should not access to the
drop table hash queues as it is invalid.

Fixes: 028761059a ("net/mlx5: use an RSS drop queue")
Cc: stable@dpdk.org

Signed-off-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
Acked-by: Shahaf Shuler <shahafs@mellanox.com>
2017-07-06 15:00:56 +02:00
Rahul Lakkireddy
a5fce96703 net/cxgbe: fix alignment for data offset in mbuf
Fixup alignment for data offset when refilling mbufs.

Fixes: edd04c6196 ("net/cxgbe: update Rx path for Chelsio T6")

Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
2017-07-06 15:00:56 +02:00
Matej Vido
24d0f5aa6b net/szedata2: use macro from common library
Macro for alignment is defined in the common library.
Use macro from the common library in own macro definition.

Signed-off-by: Matej Vido <vido@cesnet.cz>
2017-07-06 15:00:56 +02:00
Matej Vido
791aa7f4a4 net/szedata2: remove unused macro
Fixes: 2f3193cf0f ("pci: inherit common driver in PCI driver")

Signed-off-by: Matej Vido <vido@cesnet.cz>
2017-07-06 15:00:56 +02:00
Qi Zhang
ee4427e0fe net/ixgbe: support packet type parsing in SSE Rx
Hardware PTYPE in Rx desc will be parsed to fill mbuf's packet_type.

Signed-off-by: Ray Kinsella <ray.kinsella@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
2017-07-06 15:00:56 +02:00
Shachar Beiser
4329cb8111 net/mlx5: implement drop action in hardware classifier
The current drop action is implemented as a queue tail drop,
requiring to instantiate multiple WQs to maintain high drop rate.
This commit, implements the drop action in hardware classifier.
This enables to reduce the amount of contexts needed for the drop,
without affecting the drop rate.

Signed-off-by: Shachar Beiser <shacharbe@mellanox.com>
Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
2017-07-06 15:00:56 +02:00
Stephen Hemminger
463ced957c pci: increase domain storage to 32 bits
In some environments, the PCI domain can be larger than 16 bits.
For example, a PCI device passed through in Azure gets a synthetic domain
id  which is internally generated based on GUID. The PCI standard does
not restrict domain to be 16 bits.

This change breaks ABI for API's that expose PCI address structure.

The printf format for PCI remains unchanged, so that on most
systems (with only 16 bit domain) the output format is unchanged
and is 4 characters wide.  For example: 0000:00:01.0
Only on sysetms with higher bits will the domain take up more
space; example: 12000:00:01.0

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
2017-07-06 01:28:02 +02:00
Ferruh Yigit
4be4659a93 drivers/net: use device name from device structure
Device name resides in two different locations, in rte_device->name and
in ethernet device private data.

For now, the copy in the ethernet device private data is required for
multi process support, the name is the how secondary process finds about
primary process device.

But for drivers there is no reason to use the copy in the ethernet
device private data.

This patch updates PMDs to use only rte_device->name.

Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
2017-07-06 00:17:02 +02:00
Bruce Richardson
5ea4d4688d net/ixgbe: remove fallback code for x86 non-SSE4
Since SSE4 is now part of minimum requirements for DPDK on x86, we no
longer need this fallback code.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
2017-07-04 14:39:18 +02:00
Bruce Richardson
80477544fd net/i40e: remove checks for SSE4
Since SSE4 is now part of the minimum requirements for DPDK, we no longer
need these checks.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
2017-07-04 14:39:18 +02:00
Bruce Richardson
50f0b41f23 net/enic: replace check for SSE4 with check for x86
Since SSE4 is now minimum requirement for x86 platforms we can replace the
check for SSE4 with a check for x86

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
2017-07-04 14:39:18 +02:00