32911 Commits

Author SHA1 Message Date
Stephen Hemminger
555e40752b cocci/nullfree: add more functions
There are more functions in DPDK which have the semantics
as free() when passed NULL pointer. Also, put the checks
in alphabetical order.

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
2022-06-24 14:50:43 +02:00
Stephen Hemminger
448e01f1b5 lib: document free functions
Make sure all functions which use the convention that XXX_free(NULL)
is a nop are all documented.

The wording is chosen to match the documentation of free(3).
"If ptr is NULL, no operation is performed."

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Acked-by: Chengwen Feng <fengchengwen@huawei.com>
[David: squashed with other series updates, unified wording]
2022-06-24 14:50:34 +02:00
Stephen Hemminger
cb68a56343 remove passive voice in function description
Remove extraneous phrase "This API is used to" and use
active instead of passive voice when describing a function.

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Acked-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
[David: for raw/ioat and dmadev parts:]
Acked-by: Chengwen Feng <fengchengwen@huawei.com>
Acked-by: Conor Walsh <conor.walsh@intel.com>
2022-06-24 14:05:54 +02:00
Gregory Etelson
261d96b29e doc: fix flow integrity hardware support in mlx5 guide
Current MLX5 PMD documentation says that entire `ConnectX-6` family
supports flow integrity feature.

Flow integrity offload is not supported on vanilla `ConnectX-6`.
It is available on `ConnectX-6 Dx`, `ConnectX-6 Lx` and
`BlueField 2`.

Fixes: 79f8952783d0 ("net/mlx5: support integrity flow item")
Cc: stable@dpdk.org

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2022-06-23 17:25:08 +02:00
Yunjian Wang
a73b78554a net/mlx5: fix stack buffer overflow in drop action
The mlx5_drop_action_create function use mlx5_malloc for allocating
'hrxq', but don't allocate for 'rss_key'. This is wrong and it can
cause buffer overflow.

Detected with address sanitizer:
0 (/usr/lib64/libasan.so.4+0x7b8e2)
1 in mlx5_devx_tir_attr_set ../drivers/net/mlx5/mlx5_devx.c:765
2 in mlx5_devx_hrxq_new ../drivers/net/mlx5/mlx5_devx.c:800
3 in mlx5_devx_drop_action_create ../drivers/net/mlx5/mlx5_devx.c:1051
4 in mlx5_drop_action_create ../drivers/net/mlx5/mlx5_rxq.c:2846
5 in mlx5_dev_spawn ../drivers/net/mlx5/linux/mlx5_os.c:1743
6 in mlx5_os_pci_probe_pf ../drivers/net/mlx5/linux/mlx5_os.c:2501
7 in mlx5_os_pci_probe ../drivers/net/mlx5/linux/mlx5_os.c:2647
8 in mlx5_os_net_probe ../drivers/net/mlx5/linux/mlx5_os.c:2722
9 in drivers_probe ../drivers/common/mlx5/mlx5_common.c:657
10 in mlx5_common_dev_probe ../drivers/common/mlx5/mlx5_common.c:711
11 in mlx5_common_pci_probe ../drivers/common/mlx5/mlx5_common_pci.c:150
12 in rte_pci_probe_one_driver ../drivers/bus/pci/pci_common.c:269
13 in pci_probe_all_drivers ../drivers/bus/pci/pci_common.c:353
14 in pci_probe ../drivers/bus/pci/pci_common.c:380
15 in rte_bus_probe ../lib/eal/common/eal_common_bus.c:72
16 in rte_eal_init ../lib/eal/linux/eal.c:1286
17 in main ../app/test-pmd/testpmd.c:4112

Fixes: 0c762e81da9b ("net/mlx5: share Rx queue drop action code")
Cc: stable@dpdk.org

Signed-off-by: Yunjian Wang <wangyunjian@huawei.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2022-06-23 17:25:07 +02:00
Shun Hao
92b3c68e9f net/mlx5: fix metering on E-Switch Manager
When meter is used by E-Switch Manager port, there's an error that
cannot get correct port ID.

This patch fixes this by using specific parsing process to get port
ID for E-Switch Manager.

Fixes: 3c481324baf3 ("net/mlx5: fix meter flow direction check")
Cc: stable@dpdk.org

Signed-off-by: Shun Hao <shunh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2022-06-23 17:25:06 +02:00
Shun Hao
68e9925c30 net/mlx5: add limitation for E-Switch Manager match
For BF with old FW which doesn't expose the E-Switch Manager vport ID,
E-Switch Manager port matching works correctly only when BF is in
embedded CPU mode.

This patch adds the limitation description.

Fixes: a564038699f9 ("net/mlx5: support E-Switch manager egress traffic match")
Cc: stable@dpdk.org

Signed-off-by: Shun Hao <shunh@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2022-06-23 17:25:06 +02:00
Gregory Etelson
57d6a458a8 net/mlx5: fix RSS expansion for patterns with ICMP item
MLX5 PMD RSS expansion implementation added L4 UDP or TCP
headers after ICMP.
For example:
ETH / IPv4 / ICMP expanded into  ETH / IPv4 / ICMP / {UDP | TCP}
ETH / IPv6 / ICMPv6 expanded into  ETH / IPv6 / ICMPv6 / {UDP | TCP}

The patch updates PMD expansion scheme to handle ICMP and ICMPv6 types
as non-expandable for RSS.

Fixes: c7870bfe09dc ("ethdev: move RSS expansion code to mlx5 driver")
Cc: stable@dpdk.org

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2022-06-23 17:25:05 +02:00
Spike Du
f41a5092e6 app/testpmd: add host shaper command
Add command line options to support host shaper configure.
- Command syntax:
  mlx5 set port <port_id> host_shaper avail_thresh_triggered <0|1> rate
<rate_num>

- Example commands:
To enable avail_thresh_triggered on port 1 and disable current host
shaper:
testpmd> mlx5 set port 1 host_shaper avail_thresh_triggered 1 rate 0

To disable avail_thresh_triggered and current host shaper on port 1:
testpmd> mlx5 set port 1 host_shaper avail_thresh_triggered 0 rate 0

The rate unit is 100Mbps.
To disable avail_thresh_triggered and configure a shaper of 5Gbps on
port 1:
testpmd> mlx5 set port 1 host_shaper avail_thresh_triggered 0 rate 50

Add sample code to handle rxq available descriptor threshold event, it
delays a while so that rxq empties, then disables host shaper and
rearms available descriptor threshold event.

Signed-off-by: Spike Du <spiked@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2022-06-23 17:25:04 +02:00
Spike Du
2235fcda12 net/mlx5: add API to configure host port shaper
Host port shaper can be configured with QSHR (QoS Shaper Host Register).
Add check in build files to enable this function or not.

The host shaper configuration affects all the ethdev ports belonging to the
same host port.

Host shaper can configure shaper rate and lwm-triggered for a host port.
The shaper limits the rate of traffic from host port to wire port.
If lwm-triggered is enabled, a 100Mbps shaper is enabled automatically
when one of the host port's Rx queues receives available descriptor
threshold event.

Signed-off-by: Spike Du <spiked@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2022-06-23 17:25:04 +02:00
Spike Du
5c9f3294e6 net/mlx5: support Rx descriptor threshold event
Add mlx5 specific available descriptor threshold configuration
and query handler.
In mlx5 PMD, available descriptor threshold is also called
LWM (limit watermark).
While the Rx queue fullness reaches the LWM limit, the driver catches
an HW event and invokes the user callback.
The query handler finds the next Rx queue with pending LWM event
if any, starting from the given Rx queue index.

Signed-off-by: Spike Du <spiked@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2022-06-23 17:25:02 +02:00
Spike Du
25025da3c5 net/mlx5: handle Rx descriptor LWM event
When LWM meets RQ WQE, the kernel driver raises an event to SW.
Use devx event_channel to catch this and to notify the user.
Allocate this channel per shared device.
The channel has a cookie that informs the specific event port and queue.

Signed-off-by: Spike Du <spiked@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2022-06-23 17:25:00 +02:00
Spike Du
72d7efe464 common/mlx5: share interrupt management
There are many duplicate code of creating and initializing rte_intr_handle.
Add a new mlx5_os API to do this, replace all PMD related code with this
API.

Signed-off-by: Spike Du <spiked@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2022-06-23 17:24:59 +02:00
Spike Du
7158e46cb9 net/mlx5: support descriptor LWM for Rx queue
Add LWM (Limit WaterMark) field to Rxq object which indicates the percentage
of Rx queue size used by HW to raise descriptor event to the user.
Allow LWM setting in modify_rq command.
Allow the LWM configuration dynamically by adding RDY2RDY state change.

Signed-off-by: Spike Du <spiked@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2022-06-23 17:23:29 +02:00
Ali Alnubani
bae645a23a net/mlx5: fix build with clang 14
Use fgets instead of fscanf to resolve the following warning
reported by clang 14.0.0 in Fedora 37 (Rawhide):

drivers/net/mlx5/linux/mlx5_ethdev_os.c:1137:52: error:
  'fscanf' may overflow; destination buffer in argument 3 has size 16,
  but the corresponding specifier may require size 17
  [-Werror,-Wfortify-source]
  ret = fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", port_name);

Fixes: 63d1db710fbc ("net/mlx5: fix unlimited parsing of switch info")
Cc: stable@dpdk.org

Signed-off-by: Ali Alnubani <alialnu@nvidia.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2022-06-23 17:23:28 +02:00
Gregory Etelson
1db6848a09 common/mlx5: update log for DevX object creation failure
Application can fetch syndrome value after FW operation failure
starting from Mellanox OFED-5.6.
The patch updates log data after devx_obj_create error.

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2022-06-23 17:23:27 +02:00
Gregory Etelson
b006786095 common/mlx5: update log for DevX general command failure
Application can fetch syndrome value after FW operation failure
starting from Mellanox OFED-5.6.
The patch updates log data issued after devx_general_cmd error.

Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
2022-06-23 17:23:27 +02:00
Sean Zhang
6431068d0f net/mlx5: support field modification in meter rules
This patch introduces MODIFY_FIELD action support in meter. User can
create meter policy with MODIFY_FIELD action in green/yellow action.

For example:

testpmd> add port meter policy 0 21 g_actions modify_field op set
	dst_type ipv4_ecn src_type value src_value 3 width 2 / ...

Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2022-06-23 17:23:26 +02:00
Sean Zhang
76d5756122 net/mlx5: support modifying ECN field
This patch is to support modify ECN field in IPv4/IPv6 header.

Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2022-06-23 17:23:25 +02:00
Sean Zhang
097d84a42a common/mlx5: check ECN modification capability
Flag outer_ip_ecn in header modify capabilities properties layout is
added in order to check if the firmware supports modification of ecn
field.

Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2022-06-23 17:23:24 +02:00
Sean Zhang
e8146c63c3 net/mlx5: support represented port item in flow rules
Add support for represented_port item in pattern. And if the spec and mask
both are NULL, translate function will not add source vport to matcher.

For example, testpmd starts with PF, VF-rep0 and VF-rep1, below command
will redirect packets from VF0 and VF1 to wire:
testpmd> flow create 0 ingress transfer group 0 pattern eth /
represented_port / end actions represented_port ethdev_id is 0 / end

Signed-off-by: Sean Zhang <xiazhang@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2022-06-23 17:23:23 +02:00
Don Wallwork
42fbb8e85d eal/linux: allocate worker lcore stacks in hugepages
Add support for using hugepages for worker lcore stack memory. The
intent is to improve performance by reducing stack memory related TLB
misses and also by using memory local to the NUMA node of each lcore.

EAL option '--huge-worker-stack[=stack-size-in-kbytes]' is added to allow
the feature to be enabled at runtime. If the size is not specified,
the system pthread stack size will be used.

Signed-off-by: Don Wallwork <donw@xsightlabs.com>
Acked-by: Morten Brørup <mb@smartsharesystems.com>
Acked-by: Chengwen Feng <fengchengwen@huawei.com>
2022-06-23 22:36:33 +02:00
Huichao Cai
e1522b328c ip_frag: fix build with GCC 12
GCC 12 raises warnings on usage of rte_memcpy with IPv4 options handling
in fragments for both the ip_frag library and unit tests.

For example in the library:
In function ‘_mm256_storeu_si256’,
    inlined from ‘rte_mov32’ at
        ../lib/eal/x86/include/rte_memcpy.h:347:2,
    inlined from ‘rte_mov128’ at
        ../lib/eal/x86/include/rte_memcpy.h:369:2,
    inlined from ‘rte_memcpy_generic’
        at ../lib/eal/x86/include/rte_memcpy.h:445:4,
    inlined from ‘rte_memcpy’
        at ../lib/eal/x86/include/rte_memcpy.h:851:10,
    inlined from ‘__create_ipopt_frag_hdr’
        at ../lib/ip_frag/rte_ipv4_fragmentation.c:68:4,
    inlined from ‘rte_ipv4_fragment_packet’
        at ../lib/ip_frag/rte_ipv4_fragmentation.c:242:16:
/usr/lib/gcc/x86_64-redhat-linux/12/include/avxintrin.h:935:8: error:
    array subscript ‘__m256i_u[1]’ is partly outside array bounds of
    ‘uint8_t[60]’ {aka ‘unsigned char[60]’} [-Werror=array-bounds]
  935 |   *__P = __A;
      |   ~~~~~^~~~~
../lib/ip_frag/rte_ipv4_fragmentation.c: In function
    ‘rte_ipv4_fragment_packet’:
../lib/ip_frag/rte_ipv4_fragmentation.c:122:17: note: at offset [52, 60]
    into object ‘ipopt_frag_hdr’ of size 60
  122 |         uint8_t ipopt_frag_hdr[IPV4_HDR_MAX_LEN];
      |                 ^~~~~~~~~~~~~~

To resolve the compilation warning, replace the rte_memcpy with memcpy.

Fixes: b50a14a853aa ("ip_frag: add IPv4 options fragment")

Signed-off-by: Huichao Cai <chcchc88@163.com>
2022-06-23 16:32:00 +02:00
Stephen Hemminger
4200c4d625 net/qede: fix build with GCC 12
The x86 version of rte_memcpy can cause warnings. The driver does
not need to use rte_memcpy for everything. Standard memcpy is
just as fast and safer; the compiler and static analysis tools
treat memcpy specially.

Cc: stable@dpdk.org

Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
2022-06-23 16:02:02 +02:00
Wenxuan Wu
3e87e12dc8 net/ice/base: fix build with GCC 12
GCC 12 with -O2 flag would raise the following warning:
../drivers/net/ice/base/ice_switch.c:7220:61: error: writing 1 byte into a
region of size 0 [-Werror=stringop-overflow=]
 7220 |           buf[recps].content.lkup_indx[i + 1] = entry->fv_idx[i];
      |           ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~

This patch changed the type of fv_idx in struct ice_recp_grp_entry to
align with its callers which are also u8 type.

Fixes: 04b8ec1ea807 ("net/ice/base: add protocol structures and defines")
Cc: stable@dpdk.org

Signed-off-by: Wenxuan Wu <wenxuanx.wu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-06-23 11:17:28 +02:00
Kathleen Capella
0581aae1d5 net/iavf: add basic NEON Rx
This patch adds the basic NEON Rx path to the iavf driver. It does not
include scatter or flex varieties.

Tested on N1SDP platform with Intel XL710 NIC and 40G connection.
Tested with a single core and testpmd rxonly mode. Saw no significant
performance difference between scalar and Arm vPMD paths using this test
in iavf and saw the same results when comparing scalar and Arm vPMD
path in i40e.

Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Reviewed-by: Qi Zhang <qi.z.zhang@intel.com>
2022-06-23 07:49:44 +02:00
Robin Zhang
38e9762be1 net/i40e: add outer VLAN processing
Outer VLAN processing is supported after firmware v8.4, kernel driver
also change the default behavior to support this feature. To align with
kernel driver, add support for outer VLAN processing in DPDK.

But it is forbidden for firmware to change the Inner/Outer VLAN
configuration while there are MAC/VLAN filters in the switch table.
Therefore, we need to clear the MAC table before setting config,
and then restore the MAC table after setting.

This will not impact on an old firmware.

Signed-off-by: Robin Zhang <robinx.zhang@intel.com>
Signed-off-by: Kevin Liu <kevinx.liu@intel.com>
Acked-by: Yuying Zhang <yuying.zhang@intel.com>
2022-06-23 07:49:42 +02:00
Steve Yang
8eedf416a7 net/ice: add DDP runtime configuration dump
Dump DDP runtime configure into a binary (package) file from ice PF port.

Add command line:
    ddp dump <port_id> <config_path>

Parameters:
    <port_id>       the PF Port ID
    <config_path>   dumped runtime configure file, if not a absolute path,
                    it will be dumped to testpmd running directory.

For example:
testpmd> ddp dump 0 current.pkg

If you want to dump ice VF DDP runtime configure, you need bind other
unused PF port of the NIC first, and then dump the PF's runtime configure
as target output.

Signed-off-by: Steve Yang <stevex.yang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-06-23 07:49:40 +02:00
Simei Su
3d6502ee01 net/ice: fix race condition in Rx timestamp
In multi-cores cases for Rx timestamp offload, to avoid phc time being
frequently overwritten, move related variables from ice_adapter to
ice_rx_queue structure, and each queue will handle timestamp calculation
by itself.

Fixes: 953e74e6b73a ("net/ice: enable Rx timestamp on flex descriptor")
Fixes: 5543827fc6df ("net/ice: improve performance of Rx timestamp offload")
Cc: stable@dpdk.org

Signed-off-by: Simei Su <simei.su@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-06-23 07:49:38 +02:00
Ferruh Yigit
721ef3f545 net/qede: fix build with GCC 13
Reproduced with "gcc (GCC) 13.0.0 20220616 (experimental)"

Build error:
In file included from ../drivers/net/qede/qede_debug.c:9:
../drivers/net/qede/qede_debug.c: In function ‘qed_grc_dump_addr_range’:
../drivers/net/qede/base/ecore.h:95:17:
	warning: overflow in conversion from ‘int’ to ‘u8’
	{aka ‘unsigned char’} changes value from ‘(int)vf_id << 8 | 128’
	to ‘128’ [-Woverflow]
   95 |                 ((_value & _name##_MASK) << _name##_SHIFT)
      |                 ^
../drivers/net/qede/qede_debug.c:1907:31:
	note: in expansion of macro ‘FIELD_VALUE’
 1907 |         fid = FIELD_VALUE(PXP_PRETEND_CONCRETE_FID_VFVALID, 1)
      |               ^~~~~~~~~~~

To prevent overflow converting 'fib' to uint16_t,
while updating it also updated 'vf_id' to 16 bit too.

Fixes: ec55c118792b ("net/qede: add infrastructure for debug data collection")
Cc: stable@dpdk.org

Signed-off-by: Ferruh Yigit <ferruh.yigit@xilinx.com>
Acked-by: Devendra Singh Rawat <dsinghrawat@marvell.com>
2022-06-20 19:27:03 +02:00
Radha Mohan Chintakuntla
994b7ceb9b net/cnxk: add SDP VF device IDs
Add SDP VF device ID in the table for probe matching.

Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
2022-06-20 19:23:46 +02:00
Nithin Dabilpuram
022f1c1a17 net/cnxk: resize CQ for Rx security for errata
Resize CQ for Rx security offload in case of HW errata.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2022-06-20 19:23:46 +02:00
Harman Kalra
6cef22dcfe net/cnxk: fix PFC class disabling
Disabling a specific PFC class on a SQ is resulting in disabling PFC
on the entire port.

Fixes: 9544713564f5 ("net/cnxk: support priority flow control")
Cc: stable@dpdk.org

Signed-off-by: Harman Kalra <hkalra@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2022-06-20 19:23:35 +02:00
Sunil Kumar Kori
14f7c27aeb net/cnxk: remove restriction on VF for PFC config
Currently PFC configuration is not allowed on VFs.
Patch enables PFC configuration on VFs

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
2022-06-20 19:15:41 +02:00
Satananda Burla
b50f4fbd26 net/cnxk: add SDP link status
Add SDP link status reporting

Signed-off-by: Satananda Burla <sburla@marvell.com>
2022-06-20 19:15:40 +02:00
Nithin Dabilpuram
b2c5ff1bd9 common/cnxk: fix mbox structs to avoid unaligned access
Fix mbox structs to avoid unaligned access as mbox
memory is from BAR space.

Fixes: 503b82de2cbf ("common/cnxk: add mbox request and response definitions")
Fixes: e746aec161cc ("common/cnxk: fix SQ flush sequence")
Cc: stable@dpdk.org

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2022-06-20 19:15:21 +02:00
Nithin Dabilpuram
cdb718b9d1 common/cnxk: enhance CPT parsing header dump
Enhance CPT parse header dump to dump fragment info
and swap pointers before printing.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2022-06-20 19:15:20 +02:00
Harman Kalra
cc90e35b53 common/cnxk: support same TC value across multiple queues
User may want to configure same TC value across multiple queues, but
for that all queues should have a common TL3 where this TC value will
get configured.

Changed the pfc_tc_cq_map/pfc_tc_sq_map array indexing to qid and store
TC values in the array. As multiple queues may have same TC value.

Signed-off-by: Harman Kalra <hkalra@marvell.com>
2022-06-20 19:15:19 +02:00
Sunil Kumar Kori
174f2f3512 common/cnxk: add PFC support for VF
Current PFC implementation does not support VFs.
This patch enables PFC on VFs too.

Also fix the config of aura.bp to be based on number
of buffers(aura.limit) and corresponding shift
value(aura.shift).

Fixes: cb4bfd6e7bdf ("event/cnxk: support Rx adapter")
Cc: stable@dpdk.org

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
2022-06-20 19:15:17 +02:00
Nithin Dabilpuram
9f8f18037d common/cnxk: avoid CPT backpressure due to errata
Avoid enabling CPT backpressure due to errata where
backpressure would block requests from even other
CPT LF's. Also allow CQ size >=16K.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2022-06-20 19:15:16 +02:00
Nithin Dabilpuram
75315881c2 common/cnxk: use computed value for WQE skip
Use computed value for WQE skip instead of a hard-coded value.
WQE skip needs to be number of 128B lines to accommodate rte_mbuf.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2022-06-20 19:15:15 +02:00
Bruce Richardson
3d171da6e7 common/cnxk: add include for macro definition
The header file "roc_io.h" uses the "__plt_always_inline" macro but
don't include "roc_platform.h" to get the definition of it. This
inclusion is not necessary for compilation, but the lack of it can
confuse some indexers - such as those in eclipse, which reports the
lines:

"static __plt_always_inline uint64_t"

as possible definitions of a variable called "uint64_t". This confusion
leads to uint64_t being flagged as an unknown type in all other parts of
the project being indexed, e.g. across all of DPDK code.

Adding in the include of roc_platform.h makes it clear to the indexer
that those lines are  part of a function definition, and that allows
eclipse to correctly recognise uint64_t as a type from stdint.h

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2022-06-17 15:15:19 +02:00
Satheesh Paul
22d9d34882 common/cnxk: add ROC API to free MCAM entry
Add ROC API to free the given MCAM entry. If the MCAM
entry has flow counter associated, this API will clear
and free the flow counter.

Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
2022-06-17 14:52:42 +02:00
Harman Kalra
d41b53c5be common/cnxk: support CNF10KB SoC
Support for CNF10KB SoC by adding its PCI device ID.

Signed-off-by: Harman Kalra <hkalra@marvell.com>
2022-06-17 14:18:33 +02:00
Rahul Bhansali
eeea2f4e17 common/cnxk: fix CN103XX subsystem device ID
Fix the subsystem device ID for CN103XX.

Fixes: dd462f68f04a ("common/cnxk: support CN103XX platform")
Cc: stable@dpdk.org

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
2022-06-17 13:56:13 +02:00
Rakesh Kudurumalla
825bd1d9d8 common/cnxk: update extra stats for inline device
Inline device's NIX RX and RQ stats are updated
on ethdev extra stats

Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
2022-06-16 13:49:52 +02:00
Ashwin Sekhar T K
2d807166e1 mempool/cnxk: support optional wait when counting
When counting the batch allocated pointers in cnxk mempool driver,
currently it always waits for in-flight batch operations to finish.
Add a provision to make this waiting optional.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
2022-06-15 21:32:56 +02:00
Hanumanth Pothula
5f27618bea common/cnxk: handle ROC model init failure
Return with error on fail to initialize ROC model.

Fixes: 014a9e222bac ("common/cnxk: add model init and IO handling API")
Cc: stable@dpdk.org

Signed-off-by: Hanumanth Pothula <hpothula@marvell.com>
2022-06-15 19:55:42 +02:00
Rahul Bhansali
bde0d30aed common/cnxk: print NIX inline outbound CPT LF registers
This add the support to dump NIX inline outbound CPT LF
registers.

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
2022-06-15 14:25:50 +02:00
Rahul Bhansali
9595e3aef6 common/cnxk: fix decrypt packet count register update
Corrects the CPT decrypt packet counter register.

Fixes: b1a22e5d4f ("common/cnxk: add CPT diagnostics")
Cc: stable@dpdk.org

Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
2022-06-15 14:25:23 +02:00