CN98xx SoC comes up with two CPT blocks wrt
CN96xx, CN93xx, to achieve higher performance.
Adding support to allocate all LFs of VF with even BDF from CPT0
and all LFs of VF with odd BDF from CPT1.
If LFs are not available in one block then they will be allocated
from alternate block.
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Set proper bits in the context based on key length for PDCP
algorithms. This is required to support ZUC 256bit key cases.
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Upon MCAM allocation failure, free counters only if counters
were allocated earlier for the flow rule.
Fixes: f9af90807466 ("common/cnxk: add mcam utility API")
Cc: stable@dpdk.org
Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Adds support to update ethertype for mixed IPsec tunnel
versions. And also sets et_overwr for inbound IPsec.
Signed-off-by: Srujana Challa <schalla@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Add support to configure flow rules with inline IPsec action.
Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Currently only NIX0 conf is setup in AURA for backpressure.
This patch adds support for NIX1 as well.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
This patch provides applications to add CQ support
in Tx path. This enables packet completion events on
CQ for requested packets.
Signed-off-by: Kommula Shiva Shankar <kshankar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Restore SQB AURA/POOL limit before destroying SQB to be
able to drain all the buffers from the aura.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
For CPT LF IQ enable, set CPT_LF_CTL[ENA] before setting
CPT_LF_INPROG[EENA] to true.
For CPT LF IQ disable, align sequence to that of HRM.
Also this patch aligns space for instructions in CPT LF
to ROC_ALIGN to make complete memory cache aligned and
has other minor fixes/additions.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Disable CQ drop when inline inbound is enabled. CQ drop
is not supported for second pass IPsec decrypted packets.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Add API to support setting up NIX inline inbound and
NIX inline outbound. In case of inbound, SA base is setup
on NIX PFFUNC and in case of outbound, required number of
CPT LF's are attached to NIX PFFUNC.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Add support to init and fini inline device with NIX LF,
SSO LF and SSOW LF for inline inbound IPSec in CN10K.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Add API to setup NIX inline device IRQ's. This registers
IRQ's for errors in case of NIX, CPT LF, SSOW and get wor
interrupt in case of SSO.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Change NIX debug API and queue API interface for use by
internal NIX inline device initialization.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Rework interface of SSO internal functions to use for NIX inline dev's
SSO LF's.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Add security support to init cn9k fast path SA data
for AES GCM and AES CBC + HMAC SHA1.
Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
An issue exists on some HW revisions whereby if a CQ overflows
NIX may have undefined behavior, e.g. free incorrect buffers.
Implementing a workaround for this known HW issue.
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
As per an known HW issue RVUM interrupts may get dropped, If an RVUM
interrupt event occurs when PCCPF_XXX_MSIX_CAP_HDR[MSIXEN]=0 then no
interrupt is triggered, which is expected. But after MSIXEN is set to
1, subsequently if same interrupts event occurs again, still no
interrupt will be triggered.
As a workaround, all RVUM interrupt lines should be cleared between
MSIXEN=0 and MSIXEN=1.
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
If some of the VA entries of table are somehow not populated and are
NULL, it can add offset to NULL and return the invalid VA in PA to
VA conversion.
In this patch, adding a check if the VA entry has valid address only
then add offset and return VA.
Fixes: 2f3d633aa593 ("common/dpaax: add library for PA/VA translation table")
Cc: stable@dpdk.org
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
A new configuration MMO was added to QP Context.
If set, MMO WQEs are supported on this QP.
For DMA MMO, supported only when dma_mmo_qp==1.
For REGEXP MMO, supported only when regexp_mmo_qp==1.
For COMPRESS MMO, supported only when compress_mmo_qp==1.
For DECOMPRESS MMO, supported only when decompress_mmo_qp==1.
Add support to DevX interface to set MMO bit.
Signed-off-by: Raja Zidane <rzidane@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
New MMO HCA capabilities were added and others were renamed.
Align hca capabilities with new prm.
Add support in DevX interface for changes in HCA capabilities.
Signed-off-by: Raja Zidane <rzidane@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Currently drivers using QP (vDPA, crypto and compress, regex soon)
manage their memory, creation, modification and destruction of the QP,
in almost identical code.
Move QP memory management, creation and destruction to common.
Add common function to change QP state to RTS.
Add user_index attribute to QP creation.
It's for better code maintenance and reuse.
Signed-off-by: Raja Zidane <rzidane@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
In the iavf_init_arq function, if an exception occurs in the
iavf_config_arq_regs function, and the previously applied ARQ (Admin
Receive Queue) bufs resource is released. This patch maintains the same
modification as the iavf_init_asq function to roll back resources.
Fixes: 87aca6d8d8a4 ("net/iavf/base: fix command buffer memory leak")
Cc: stable@dpdk.org
Signed-off-by: Qiming Chen <chenqiming_huawei@163.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
Add IPv4 header checksum field selector, it can be used in creating
FDIR or RSS rules related to IPv4 header checksum.
Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
This patch adds an ROC API to merge base steering rule with rules
added by VF.
Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Reviewed-by: Kiran Kumar K <kirankumark@marvell.com>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
Add support for reading NPA/SSO pf_func which will be used
by a PSM to access NPA/SSO. PSM is a hardware block capable
of dispatching jobs to different blocks within a baseband
module.
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
Due to wrong size of mbox message allocated for sending link status
to the VF, incorrect link status is observed.
Fixes: cb8d769fb6fe ("common/octeontx2: send link event to VF")
Cc: stable@dpdk.org
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
NPC MCAM entry distribution is based on maximum number of PFs and LFs
available. Fixing the max no of PFs and LFs available on cn98xx to
fix the MCAM alloc entry range.
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
In case of cn98xx, 2 NIX blocks and 4 LBK blocks are present. Moreover
AF VFs are alternatively attached to NIX0 and NIX1 to ensure load
balancing. To support loopback functionality between pairs NIX0/NIX1
are attached to LBK1/LBK2 for transmission/reception respectively.
But in this default configuration NIX blocks cannot receive the
packets they sent from the same LBK, which is an important requirement
as some ODP applications only uses one AF VF for loopback functionality.
To support this scenario, NIX0 can use LBK0 (NIX1 - LBK3) by setting a
loop flag while making LF alloc mailbox request.
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
There is an inconsistency in naming interrupt control
functions. This patch aligns names accordingly.
Signed-off-by: Jakub Palider <jpalider@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Some functions are not used outside of local ROC scope. These need
updating classifiers and removal from header.
Signed-off-by: Jakub Palider <jpalider@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
One should only use roc_api.h which exports all internal headers.
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
If particular LMAC does not exist then it's saner to return ENODEV
instead of EINVAL.
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Platform specific TM tree hierarchy details are part of common cnxk
driver. This patch introduces missing HAL APIs to return state of
TM hierarchy required to support ethdev TM operations inside cnxk PMD.
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Different TM handlers returns various platform specific errors,
this patch introduces new API to convert these internal error
types to RTE_TM* error types.
Also updated error message API with missed TM error types.
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add new macros to reflect HW shaper PPS limits. New API to validate
input rates for packet mode. Increase adjust value to support lesser
PPS (<61).
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Each NIX interface had one or more SMQs connected to SQs to send
packets. When flush enabled on SMQ, hardware will push all packets
from SMQ to physical link. This API will enable flush on all SMQs
of an interface.
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
For SDP interface all platforms supports up to 65535 frame size.
Updated API with new check for SDP interface.
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
The common remove function call in a loop to remove function for each
driver which have been registered.
If all removes are succeeded, it return 0 without to free the device
which allocated in probe function. Otherwise, it free the device.
In fact we expect exactly the opposite behavior. If all removes are
failed, it returns error without freeing the device which allocated in
probe function. Otherwise, it free the device and return 0.
Replace it with the correct behavior.
Fixes: 8a41f4deccc3 ("common/mlx5: introduce layer for multiple class drivers")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
The mlx5 common driver has a global list of mlx5 devices which are
probed.
In probe function it creates one and insert it to the list. Similarly it
removes the device in remove function.
These operations are not safe as there can be such operations in
parallel, by different threads.
Add global lock for the list and use it to insert or remove.
Fixes: 8a41f4deccc3 ("common/mlx5: introduce layer for multiple class drivers")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
The common probe function gets as a user argument the classes it should
create, and checks whether the combination is valid.
In case the device already exists, it checks the integration of the
above with the classes that the device has.
However, the function does not check the combination when the device
does not exist and it has to create it.
Check if the combination is valid for all cases.
Fixes: ad435d320473 ("common/mlx5: add bus-agnostic layer")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Network Pool accelerator (NPA) is part of ROC (Rest Of Chip). So
NPA structures should be aligned to ROC Cache line size and not
CPU cache line size.
Non alignment of NPA stack to ROC cache line will result in
undefined runtime NPA behaviour.
Fixes: f765f5611240 ("common/cnxk: add NPA pool HW operations")
Cc: stable@dpdk.org
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Avoid using stashing option of stype in NPA in cn10k-a0 stepping.
This is a workaround for a HW Errata due to which NPA stashing operations
will never result in writing the data into L2 cache. But instead, it will
be written into LLC.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Made following updates to ROC (Rest of Chip) models.
- Use consistent upper/lower case in macros defining different
ROC models.
- Add API to detect cn96 Cx stepping.
- Make all current cn10k models as A0 stepping.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
