This patch removes some some 1GBASE-T PHY access since the FW
configures the PHY. SW shall not configure or initialize link.
Accessing the PHY would require the use of MDI clause 22 which
should be avoided in high layer driver code.
Signed-off-by: Wei Dai <wei.dai@intel.com>
Tx/Rx queue may be already flushed due to Tx/Rx error on the queue or
MC reboot. Caller needs to know that the queue is already flushed to
avoid waiting for flush done event.
Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
MCDI results returned in req.emr_rc have already been translated
from MC_CMD_ERR_* to errno names, so using an MC_CMD_ERR_* value
is incorrect.
Fixes: e7cd430c864f ("net/sfc/base: import SFN7xxx family support")
Cc: stable@dpdk.org
Signed-off-by: Andy Moreton <amoreton@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Add support to configure minimum and maximum PCIe extended tag.
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
rmb before determining rsp_type is a bottleneck.
Once we determine rsp-type is FL, we can directly go ahead and read
packets based on q->stat->pidx and budget_left.
This removes bottleneck of rmb once per every RX packet.
Now, rmb exists once per RX batch.
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Enabling rx queues with default interrupt parameters doesn't happen
for other ports under same PF due to FULL_INIT_DONE flag being set
by the first port.
Fix is to to allow each port to enable its own rx queues with default
parameters.
Fixes: 0462d115441d ("cxgbe: add device related operations")
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
TX coalescing waits for ETH_COALESCE_PKT_NUM packets to be coalesced
across bursts before transmitting them. For slow traffic, such as
100 PPS, this approach increases latency since packets are received
one at a time and tx coalescing has to wait for ETH_COALESCE_PKT
number of packets to arrive before transmitting.
To fix this:
- Update rx path to use status page instead and only receive packets
when either the ingress interrupt timer threshold (5 us) or
the ingress interrupt packet count threshold (32 packets) fires.
(i.e. whichever happens first).
- If number of packets coalesced is <= number of packets sent
by tx burst function, stop coalescing and transmit these packets
immediately.
Also added compile time option to favor throughput over latency by
default.
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Remove RTE_PCI_DRV_INTR_LSC from driver flags, since LSC interrupts
are currently not supported.
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Do not count pause frames as part of normal TX/RX Frame/Byte counts.
Also, switch to using software counters rather than hardware for RX
stats.
Fixes: 856505d303f4 ("cxgbe: add port statistics")
Cc: stable@dpdk.org
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Add support for compressed error vector available in cpl_rx_pkt for
Chelsio T6.
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Update RX path to reflect Chelsio T6 register value changes.
Update ingress pack boundary value based on maximum payload size
that can be accommodated by underlying PCI. Update ingress pad
boundary value based on smallest memory controller bus width
possible. Enforce alignment for free list pointer start address.
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Update informational prints pertaining to underlying hardware.
Add bootstrap firmware version and expansion ROM version prints.
Move the prints to a single function.
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Add 25G and 100G link speeds and update supported port modules.
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Move code to get the available ports from the firmware after it had
been reset. This ensures that driver uses the latest info on available
ports after firmware reset.
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Update flash part identification and decoding to accommodate new
flash parts.
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
Add code to detect and run T6 devices. Update PCI ID Device table
with Chelsio T6 device ids and update documentation.
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
This patch adds basic offloading support, widely expected in a PMD.
Verify IPv4 and UDP/TCP checksums upon packet reception, and set
ol_flags accordingly.
On Tx, set IPv4 and UDP/TCP checksums when required, considering
ol_flags.
Signed-off-by: Pascal Mazon <pascal.mazon@6wind.com>
The following two flow rules (testpmd syntax) should not collide:
flow create 0 priority 1 ingress pattern eth / ipv4 / end actions drop / end
flow create 0 priority 1 ingress pattern eth / ipv6 / end actions drop / end
But the eth_type in the associated TC rule was set to either "ip" or
"ipv6". For TC, they could thus not have the same priority.
Use ETH_P_ALL only in the TC message to make sure those rules can
coexist.
Fixes: de96fe68ae95 ("net/tap: add basic flow API patterns and actions")
Cc: stable@dpdk.org
Signed-off-by: Pascal Mazon <pascal.mazon@6wind.com>
In order to check the congestion state of Egress FQs,
this qbman function will be used by the DPAA2 Ethernet PMD.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Typically when the PMD issues a Rx command to DPAA2 hardware,
the HW writes the available descriptors into the given memory.
The RX function then processes the frames and prepare them as
mbufs.
This patch adds support to issue another pull request to hardware
in another memory location, before we start processing the output
of the first request. This help in controlling the CPU cycles
wasted during the wait for the hardware to write the descriptors.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
DPAA2 hardware support the option to configure
multiple memories for Rx recv buffer (DPAA2-DQRR).
Each Rx request executing is called as 'DQ' request.
This patch adds routines to get information w.r.t each DQ request.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
The DPAA2 driver is not using the DPAA2 frame descriptor
software annotation area. This patch reduces the
PTA length to zero and adjust the RX Buffer Layout
accordingly.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
This code in device init is not required, as the buffer
layout setting is also being programmed during queue configuration.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Add subsystem device id of CN23xx cards and expose speed capability of
devices. Update liquidio feature file to mark support.
Signed-off-by: Shijith Thotton <shijith.thotton@caviumnetworks.com>
Before this patch, flex_filter->index was always zero when it was read
and used after rte_zmalloc. The corresponding code was therefore moved
into the add and delete parts of the if/else statement.
Fixes: 231d43909a31 ("igb: migrate flex filter to new API")
Cc: stable@dpdk.org
Signed-off-by: Markus Theil <markus.theil@tu-ilmenau.de>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
i210/i211 also support flex filters. Tested on i210.
Signed-off-by: Markus Theil <markus.theil@tu-ilmenau.de>
Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
Completion buffer size was computed wrongly, causing
completion polling to wraparound too early and miss entries.
Fixing it by using Direct Verbs to query the CQ info.
Fixes: 6218063b39a6 ("net/mlx5: refactor Rx data path")
Fixes: 1d88ba171942 ("net/mlx5: refactor Tx data path")
Cc: stable@dpdk.org
Signed-off-by: Shahaf Shuler <shahafs@mellanox.com>
Acked-by: Yongseok Koh <yskoh@mellanox.com>
Acked-by: Nelio Laranjeiro <nelio.laranjeiro@6wind.com>
