Add scalar FPM tables to be used for asymmetric crypto
operations.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Microcode AE opcodes support asymmetric operations. Add defines
and structs defined by microcode.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Microcode SE opcodes support symmetric operations. Add defines
and structs defined by microcode.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Add CPT hardware definitions. CPT is the hardware block on
cnxk family of processors, that can be used to offload
cryptographic operations.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
As per the new LMTST design, userspace shall allocate LMT region,
setup the DMA translation and share the IOVA with kernel via MBOX.
Kernel will convert this IOVA to physical memory and update the
LMT table entry with the same.
With this new design also shared mode (i.e. all pci funcs sharing
the LMT region allocated by primary/base pci func) is intact.
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
Add support for device init and fini. It merely saves
baseband phy state container in a globally accessible
resource chest.
Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
Add support for low level initialization and cleanup of baseband
PHY CGX/RPM blocks.
Initialization and cleanup are related hence are in the same patch.
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
Add TIM device init, fini which are used to attach TIM LF
resources to the RVU PF/VF and TIM LF alloc and free.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add SSO device init and fini which attach SSO LF resources to the
RVU PF/VF and SSO HWS and HWGRP LFs alloc, free.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Adding initial support for programming NPC. NPC is Network Parser
and CAM unit that provides Rx and Tx packet parsing and packet
manipulation functionality on Marvell CN9K and CN10K SoC's. It is
mapped to RTE Flow in DPDK.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Add base nix support as ROC(Rest of Chip) API which will
be used by generic ETHDEV PMD(net/cnxk).
This patch adds support to device init, fini, resource
alloc and free API which sets up a ETHDEV PCI device of either
CN9K or CN10K Marvell SoC.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Add base NPA device support. NPA i.e Network Pool Allocator is
HW block that provides HW mempool functionality on Marvell CN9K
and CN10K SoC's. NPA by providing HW mempool support, also
facilitates Rx and Tx packet alloc and packet free by HW without
SW intervention.
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Introduce 'dev' class to hold cnxk PCIe device specific
information and operations.
All PCIe drivers(ethdev, mempool, cryptodev and eventdev) of cnxk
inherits this base object to avail the common functionalities such
as mailbox creation, interrupt registration, LMT setup, VF message
mbox forwarding, etc.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
The admin function driver sits in Linux kernel as mailbox
server. The DPDK AF mailbox client, send the message to mailbox
server to complete the administrative task such as get mac
address.
This patch adds mailbox request and response definition of
existing mailbox defined between AF driver and DPDK driver.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Add routines for SoC model identification and HW IO handling
routines specific to CN9K and CN10K Marvell SoC's.
These are based on arm64 ISA and behaviour specific to
Marvell SoC's.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add meson build infrastructure along with HW definition
header file.
This patch also adds cross-compile configs for arm
for CN9K series and CN10K series of Marvell SoC's.
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
