Commit Graph

174 Commits

Author SHA1 Message Date
Bruce Richardson
4ad4b20a79 drivers: change indentation in build files
Switch from using tabs to 4 spaces for meson.build indentation.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
2021-04-21 14:04:09 +02:00
Bruce Richardson
cf995efc53 drivers: clean up build lists
Ensure all lists of drivers are standardized:
* one driver per line
* lists double-indented with spaces (as they are line continuations)
* elements in alphabetical order
* opening and closing list brackets "[" & "]" on own lines
* last element has trailing comma

Any code snippets in the list files is adjusted to single-indent using
whitespace to correspond to the new style also.

The lists of standard library dependencies per class, and other short
lists are not formatted one-per-line as these lists are not expected to
grow beyond 2 or 3 entries.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
2021-04-21 12:37:55 +02:00
Ashwin Sekhar T K
91531e63f4 mempool/cnxk: add cn10k batch dequeue
Add the implementation for Marvell CN10k mempool batch dequeue op.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
2021-04-09 08:32:24 +02:00
Ashwin Sekhar T K
8f2cd79460 mempool/cnxk: add cn10k get count
Add the implementation for Marvell CN10k get count op.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
2021-04-09 08:32:24 +02:00
Ashwin Sekhar T K
ecbc731a22 mempool/cnxk: add cn10k batch enqueue
Add the implementation for Marvell CN10k mempool batch enqueue op.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
2021-04-09 08:32:24 +02:00
Ashwin Sekhar T K
db2a347a50 mempool/cnxk: add batch operation init
Marvell CN10k mempool supports batch enqueue/dequeue which can
dequeue up to 512 pointers and enqueue up to 15 pointers using
a single instruction.

These batch operations require a DMA memory to enqueue/dequeue
pointers. This patch adds the initialization of this DMA memory.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
2021-04-09 08:32:24 +02:00
Ashwin Sekhar T K
89627db18f mempool/cnxk: add cn10k mempool operations
Add Marvell CN10k mempool ops and implement CN10k mempool alloc.

CN10k has 64 bytes L1D cache line size. Hence the CN10k mempool
alloc does not make the element size an odd multiple L1D cache
line size as NPA requires the element sizes to be multiples of
128 bytes.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
2021-04-09 08:32:24 +02:00
Ashwin Sekhar T K
2655241a7e mempool/cnxk: add cn9k optimized enqueue/dequeue
Add Marvell CN9k mempool enqueue/dequeue. Marvell CN9k
supports burst dequeue which allows to dequeue up to 32
pointers using pipelined casp instructions.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
2021-04-09 08:32:24 +02:00
Ashwin Sekhar T K
e43b51fec3 mempool/cnxk: add cn9k mempool operations
Add Marvell CN9k mempool ops and implement CN9k mempool
alloc which makes sure that the element size always occupy
odd number of cachelines to ensure even distribution among
of elements among L1D cache sets.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
2021-04-09 08:32:24 +02:00
Ashwin Sekhar T K
0ad49b2083 mempool/cnxk: register plt init callback
Register the CNXk mempool plt init callback which will set the
appropriate mempool ops to be used for the platform.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
2021-04-09 08:32:24 +02:00
Ashwin Sekhar T K
bbf19e89b8 mempool/cnxk: add generic operations
Add generic CNXk mempool ops which will enqueue/dequeue
from pool one element at a time.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
2021-04-09 08:32:24 +02:00
Ashwin Sekhar T K
0a50a5aad2 mempool/cnxk: add device probe/remove
Add the implementation for CNXk mempool device
probe and remove.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
2021-04-09 08:32:24 +02:00
Ashwin Sekhar T K
2da3159197 mempool/cnxk: add build infra and doc
Add the meson based build infrastructure for Marvell
CNXK mempool driver along with stub implementations
for mempool device probe.

Also add Marvell CNXK mempool base documentation.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
2021-04-09 08:32:24 +02:00
Nipun Gupta
376fb49ecf net/dpaa: prevent multiple mempool config
The current driver only support single buffer pool on a given
PMD instance. Return error, if trying to configure more.

Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
2021-02-24 18:03:30 +01:00
Hemant Agrawal
da84fa3ef2 mempool/dpaa2: support stats for secondary process
DPAA2 DPBP object access need availability of MCP object
pointer. In case of secondary process, we need to use local
MCP pointer instead of primary process.

Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
2021-02-24 18:03:30 +01:00
Bruce Richardson
df96fd0d73 ethdev: make driver-only headers private
The rte_ethdev_driver.h, rte_ethdev_vdev.h and rte_ethdev_pci.h files are
for drivers only and should be a private to DPDK and not installed.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Steven Webster <steven.webster@windriver.com>
2021-01-29 20:59:09 +01:00
Bruce Richardson
762bfccc8a config: remove compatibility build defines
As announced in the deprecation note, remove all compatibility build
defines from previous make/meson versions and use only the standardized
ones - RTE_LIB_<name> for libraries, and RTE_<CLASS>_<NAME> for drivers.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
2021-01-20 01:43:25 +01:00
Thomas Monjalon
135155a836 build: align wording of non-support reasons
Reasons for building not supported generally start with lowercase
because printed as the second part of a line.

Other changes:
	- "linux" should be "Linux" with a capital letter.
	- ARCH_X86_64 may be simply x86_64.
	- aarch64 is preferred over arm64.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: David Marchand <david.marchand@redhat.com>
2020-11-20 16:05:35 +01:00
Thomas Monjalon
43314d97e2 drivers: disable OCTEON TX2 in 32-bit build
The drivers for OCTEON TX2 are not supported in 32-bit mode.

Suggested-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2020-11-12 16:39:10 +01:00
David Marchand
ea2780632f bus/fslmc: switch sequence number to dynamic mbuf field
The dpaa2 drivers have been hacking the deprecated field seqn for
internal features.
It is moved to a dynamic mbuf field in order to allow removal of seqn.

Signed-off-by: David Marchand <david.marchand@redhat.com>
2020-10-31 22:14:37 +01:00
David Marchand
30105f664f drivers: add headers install helper
A lot of drivers export headers, reproduce the same facility than for
libraries.

Note: this change fixes an issue with the crypto scheduler headers which
were not installed properly. A separate backport will be sent to stable
branches.

Suggested-by: Bruce Richardson <bruce.richardson@intel.com>
Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
2020-10-22 14:16:22 +02:00
Bruce Richardson
a20b2c01a7 build: standardize component names and defines
As discussed on the dpdk-dev mailing list[1], we can make some easy
improvements in standardizing the naming of the various components in DPDK,
and their associated feature-enabled macros.

Following this patch, each library will have the name in format,
'librte_<name>.so', and the macro indicating that library is enabled in the
build will have the form 'RTE_LIB_<NAME>'.

Similarly, for libraries, the equivalent name formats and macros are:
'librte_<class>_<name>.so' and 'RTE_<CLASS>_<NAME>', where class is the
device type taken from the relevant driver subdirectory name, i.e. 'net',
'crypto' etc.

To avoid too many changes at once for end applications, the old macro names
will still be provided in the build in this release, but will be removed
subsequently.

[1] http://inbox.dpdk.org/dev/ef7c1a87-79ab-e405-4202-39b7ad6b0c71@solarflare.com/t/#u

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Luca Boccassi <bluca@debian.org>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Acked-by: Rosen Xu <rosen.xu@intel.com>
2020-10-19 22:15:34 +02:00
Bruce Richardson
63b3907833 build: remove library name from version map file name
Since each version map file is contained in the subdirectory of the library
it refers to, there is no need to include the library name in the filename.
This makes things simpler in case of library renaming.

Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Luca Boccassi <bluca@debian.org>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Acked-by: Rosen Xu <rosen.xu@intel.com>
2020-10-19 22:13:59 +02:00
Harman Kalra
ce8628c66a net/octeontx2: fix jumbo frame crash
Issue has been observed in case of multi segments where mbuf
data gets corrupted due to missing barriers. Changes made to
mbuf just before LMTST by one core gets updatded when the
same mbuf is in use by another core, leading to corruption.
It should be ensured that all changes made to mbuf should be
written before LMTST.

Fixes: cbd5710db4 ("net/octeontx2: add Tx multi segment version")
Cc: stable@dpdk.org

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Harman Kalra <hkalra@marvell.com>
2020-10-15 22:54:21 +02:00
Tal Shnaiderman
ef271860c1 mempool/ring: build on Windows
Build the ring mempool handler for Windows OS.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Ranjit Menon <ranjit.menon@intel.com>
2020-10-05 10:07:17 +02:00
Pavan Nikhilesh
e1712291b1 mempool/octeontx: fix aura to pool mapping
When sending commands to Kernel FPA PF driver, it expects the
aura to be in the range of 0 to 16 for a given FPA pool.
In OCTEON TX we map a pool,aura pair as single mempool handle,
always set the aura id to 0 for a given FPA pool.

Fixes: 179c7e893f ("mempool/octeontx: fix pool to aura mapping")
Cc: stable@dpdk.org

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2020-09-30 19:19:11 +02:00
Ciara Power
3cc6ecfdfe build: remove makefiles
A decision was made [1] to no longer support Make in DPDK, this patch
removes all Makefiles that do not make use of pkg-config, along with
the mk directory previously used by make.

[1] https://mails.dpdk.org/archives/dev/2020-April/162839.html

Signed-off-by: Ciara Power <ciara.power@intel.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
2020-09-08 00:09:50 +02:00
Thomas Monjalon
4f86c0ba19 version: 20.11-rc0
Start a new release cycle with empty release notes.

The ABI version becomes 21.0.
The ABI major is back to normal, having only one number (21 vs 20.0).
The map files are updated to the new ABI major number (21).
The ABI exceptions are dropped.
Travis ABI check is disabled because compatibility is not preserved.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
2020-08-12 11:32:16 +02:00
Konstantin Ananyev
e1187407b4 mempool/ring: support RTS and HTS ring modes
Two new sync modes were introduced into rte_ring:
relaxed tail sync (RTS) and head/tail sync (HTS).
This change provides user with ability to select these
modes for ring based mempool via mempool ops API.

Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Gage Eads <gage.eads@intel.com>
2020-07-21 19:20:00 +02:00
Rohit Raj
e58722218a drivers/dpaa: optimize thread local storage
Minimize the number of different thread variables

Add all the thread specific variables in dpaa_portal
structure to optimize TLS Usage.

Signed-off-by: Rohit Raj <rohit.raj@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
2020-07-11 06:18:52 +02:00
David Marchand
70d4d5f1ac mempool/bucket: handle non-EAL lcores
Convert to new lcore API to support non-EAL lcores.

Signed-off-by: David Marchand <david.marchand@redhat.com>
Reviewed-by: Andrew Rybchenko <arybchenko@solarflare.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
2020-07-08 14:41:06 +02:00
David Marchand
1022ff0c33 drivers: drop workaround for internal libraries version
Now that all libraries have a single version, we can drop the empty
stable blocks that had been added when moving symbols from stable to
internal ABI.

Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
2020-07-07 12:48:59 +02:00
Jerin Jacob
9c99878aa1 log: introduce logtype register macro
Introduce the RTE_LOG_REGISTER macro to avoid the code duplication
in the logtype registration process.

It is a wrapper macro for declaring the logtype, registering it and
setting its level in the constructor context.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Sachin Saxena <sachin.saxena@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-07-03 15:52:51 +02:00
Tal Shnaiderman
33031608e8 bus/pci: introduce Windows support with stubs
Addition of stub eal and bus/pci functions to compile
bus/pci for Windows.

Signed-off-by: Tal Shnaiderman <talshn@mellanox.com>
2020-06-30 00:02:54 +02:00
Pavan Nikhilesh
31246a328f mempool/octeontx2: add devargs to lock context in cache
Add device arguments to lock NPA aura and pool contexts in NDC cache.
The device args take hexadecimal bitmask where each bit represent the
corresponding aura/pool id.
Example:
	-w 0002:02:00.0,npa_lock_mask=0xf // Lock first 4 aura/pool ctx

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2020-05-19 18:28:58 +02:00
Hemant Agrawal
df80d4f87f bus/dpaa: move log types to NXP drivers
This is to reduce the number of variables getting exposed
from the dpaa bus. They are not required to be in bus.

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
2020-05-19 15:49:53 +02:00
Hemant Agrawal
a95e588c07 mempool/dpaa2: install missing header with meson
rte_dpaa2_mempool.h header was missed to be added in meson.build
for header installation.

Fixes: 7ed3599095 ("mempool/dpaa2: add functions for CMDIF")
Cc: stable@dpdk.org

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
2020-05-19 15:49:53 +02:00
Hemant Agrawal
4d1f7981b4 drivers/mempool: mark internal NXP symbols
This patch moves the internal symbols to INTERNAL sections
so that any change in them is not reported as ABI breakage.

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
2020-05-19 15:49:53 +02:00
Pavan Nikhilesh
03a4e635cf mempool/octeontx2: mark internal symbols
Move the internal symbols to INTERNAL sections so that any
change in them is not reported as ABI breakage.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Ray Kinsella <mdr@ashroe.eu>
Signed-off-by: David Marchand <david.marchand@redhat.com>
2020-05-18 17:29:24 +02:00
Nipun Gupta
d527f5d9bb drivers: enhance DPAA2 portal allocation error logs
Update the portal allocation failure log to print the thread id
as well.

Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
2020-05-11 22:27:39 +02:00
Ferruh Yigit
0403b233ee mempool/octeontx2: fix build for gcc O1 optimization
Can be reproduced with "make EXTRA_CFLAGS='-O1'" command using
gcc (GCC) 9.3.1 20200408 (Red Hat 9.3.1-2)

Build error:
In file included from .../drivers/mempool/octeontx2/otx2_mempool.h:13,
                from .../drivers/mempool/octeontx2/otx2_mempool_ops.c:8:
.../drivers/mempool/octeontx2/otx2_mempool_ops.c:
	In function ‘otx2_npa_alloc’:
.../drivers/common/octeontx2/otx2_common.h:94:2:
    error: ‘aura_handle’ may be used uninitialized in this function
           [-Werror=maybe-uninitialized]
   94 |  rte_log(RTE_LOG_DEBUG, otx2_logtype_ ## subsystem,  \
      |  ^~~~~~~
.../drivers/mempool/octeontx2/otx2_mempool_ops.c:643:11:
    note: ‘aura_handle’ was declared here
  643 |  uint64_t aura_handle;
      |           ^~~~~~~~~~~

This looks like false positive, assigning an initial value to
'aura_handle' to fix the build error.

Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2020-05-11 19:21:18 +02:00
Thomas Monjalon
e3866e7355 replace hot attributes
The new macro __rte_hot, for compiler hinting,
is now used where appropriate for consistency.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
2020-04-16 18:30:58 +02:00
Thomas Monjalon
ef5baf3486 replace packed attributes
There is a common macro __rte_packed for packing structs,
which is now used where appropriate for consistency.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
2020-04-16 18:16:46 +02:00
Pavan Nikhilesh
acec04c4b2 build: disable experimental API check internally
Remove setting ALLOW_EXPERIMENTAL_API individually for each Makefile and
meson.build. Instead, enable ALLOW_EXPERIMENTAL_API flag across app, lib
and drivers.
This changes reduces the clutter across the project while still
maintaining the functionality of ALLOW_EXPERIMENTAL_API i.e. warning
external applications about experimental API usage.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Signed-off-by: David Marchand <david.marchand@redhat.com>
2020-04-14 16:22:34 +02:00
Tao Zhu
bc3282125b mempool/octeontx2: fix build
Change the definition of C99 style to C90 style.
compile log as below:

otx2_mempool_ops.c: In function ‘otx2_npa_populate’:
drivers/mempool/octeontx2/otx2_mempool_ops.c:790:2: error:
	‘for’ loop initial declarations are only allowed in C99 mode
  for (int i = 0; i < OTX2_L1D_NB_SETS; i++)
  ^
drivers/mempool/octeontx2/otx2_mempool_ops.c:790:2:
	note: use option -std=c99 or -std=gnu99 to compile your code

Fixes: 9ed8e95c ("mempool/octeontx2: optimize for L1D cache architecture")

Signed-off-by: Tao Zhu <taox.zhu@intel.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
2020-02-17 19:29:10 +01:00
Pavan Nikhilesh
9ed8e95cc7 mempool/octeontx2: optimize for L1D cache architecture
OCTEON TX2 has 8 sets, 41 ways L1D cache, VA<9:7> bits dictate
the set selection.
Add additional padding to ensure that the element size always
occupies odd number of cachelines to ensure even distribution
of elements among L1D cache sets.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Signed-off-by: Jerin Jacob <jerinj@marvell.com>
2020-02-16 21:54:15 +01:00
Krzysztof Kanas
4f2c3c7b1d mempool/octeontx: fix error handling in initialization
When octeontx_get_fpavf fails fpa pointer is used to get
pool_stack_base, which is then freed.

Coverity issue: 351263
Fixes: 9bc692f83b ("mempool/octeontx: add application domain validation")
Cc: stable@dpdk.org

Signed-off-by: Krzysztof Kanas <kkanas@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2020-01-17 19:46:26 +01:00
Sachin Saxena
f513f62059 drivers: update copyright for NXP files
Signed-off-by: Sachin Saxena <sachin.saxena@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
2019-11-28 16:03:54 +01:00
Pavan Nikhilesh
9bc692f83b mempool/octeontx: add application domain validation
Add application domain validation for OCTEON TX FPA vfs.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
2019-11-26 07:49:30 +01:00
Pavan Nikhilesh
b4134b2d31 common/octeontx: update mbox to version 1.1.3
Sync mail box data structures to version 1.1.3.
Add mail box version verification and defer initializing octeontx
devices if mail box version mismatches.
Update OCTEON TX limitaion with max mempool size used.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
2019-11-26 07:49:30 +01:00