Commit Graph

641 Commits

Author SHA1 Message Date
Vidya Sagar Velumuri
bd02fe78c6 common/cnxk: add NIX inline IPsec config API
Add API to configure NIX block for inline IPSec.

Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2021-04-09 08:32:24 +02:00
Sunil Kumar Kori
1c518ee11e common/cnxk: add NIX specific NPC operations
Add NIX specific NPC operations such as NPC mac address get/set,
mcast entry add/delete, promiscuous mode enable/disable etc.

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2021-04-09 08:32:24 +02:00
Sunil Kumar Kori
313cc41830 common/cnxk: support NIX MAC operations
Add support to different MAC related operations such as
MAC address set/get, link set/get, link status callback,
etc.

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2021-04-09 08:32:24 +02:00
Jerin Jacob
ae06070901 common/cnxk: add NIX Tx queue management API
This patch adds support to init/modify/fini NIX
SQ(send queue) for both CN9K and CN10K platforms.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2021-04-09 08:32:24 +02:00
Jerin Jacob
19a2b54982 common/cnxk: add NIX Rx queue management API
Add nix Rx queue management API to init/modify/fini
RQ context and also setup CQ(completion queue) context.
Current support is both for CN9K and CN10K devices.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2021-04-09 08:32:24 +02:00
Jerin Jacob
f6d567b03d common/cnxk: support NIX IRQ
Add support to register NIX error and completion
queue IRQ's using base device class IRQ helper API's.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Signed-off-by: Harman Kalra <hkalra@marvell.com>
2021-04-09 08:32:24 +02:00
Jerin Jacob
8dcdf319dd common/cnxk: support NIX
Add base nix support as ROC(Rest of Chip) API which will
be used by generic ETHDEV PMD(net/cnxk).

This patch adds support to device init, fini, resource
alloc and free API which sets up a ETHDEV PCI device of either
CN9K or CN10K Marvell SoC.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
2021-04-09 08:32:24 +02:00
Ashwin Sekhar T K
81af267893 common/cnxk: support NPA batch alloc/free
Add APIs to do allocations/frees in batch from
NPA pool.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2021-04-09 08:32:24 +02:00
Ashwin Sekhar T K
1d9f8a4849 common/cnxk: support NPA performance counter
Add APIs to read NPA performance counters.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2021-04-09 08:32:24 +02:00
Ashwin Sekhar T K
2409f53a27 common/cnxk: support NPA bulk alloc/free
Add APIs to alloc/free in bulk from NPA pool.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2021-04-09 08:32:24 +02:00
Ashwin Sekhar T K
f765f56112 common/cnxk: add NPA pool HW operations
Add APIs for creating, destroying, modifying
NPA pools.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2021-04-09 08:32:24 +02:00
Ashwin Sekhar T K
dfb02998e0 common/cnxk: support NPA debug
Add NPA debug APIs.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2021-04-09 08:32:24 +02:00
Ashwin Sekhar T K
e67f633e48 common/cnxk: support NPA IRQ
Add support for NPA IRQs.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2021-04-09 08:32:24 +02:00
Ashwin Sekhar T K
124ff1a4cb common/cnxk: support NPA device
Add base NPA device support. NPA i.e Network Pool Allocator is
HW block that provides HW mempool functionality on Marvell CN9K
and CN10K SoC's. NPA by providing HW mempool support, also
facilitates Rx and Tx packet alloc and packet free by HW without
SW intervention.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2021-04-09 08:32:24 +02:00
Jerin Jacob
585bb3e538 common/cnxk: add VF support to base device class
Add VF specific handling such as BAR4 setup, forwarding
VF mbox messages to AF and vice-versa, VF FLR handling
etc.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2021-04-09 08:32:24 +02:00
Jerin Jacob
665ff1ccc2 common/cnxk: add base device class
Introduce 'dev' class to hold cnxk PCIe device specific
information and operations.

All PCIe drivers(ethdev, mempool, cryptodev and eventdev) of cnxk
inherits this base object to avail the common functionalities such
as mailbox creation, interrupt registration, LMT setup, VF message
mbox forwarding, etc.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2021-04-09 08:32:24 +02:00
Jerin Jacob
03cc9bd929 common/cnxk: add mailbox base infrastructure
This patch adds mailbox infra API's to communicate with Kernel AF
driver. These API's will be used by all the other cnxk drivers
for mbox init/fini, send/recv functionality.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2021-04-09 08:32:24 +02:00
Jerin Jacob
503b82de2c common/cnxk: add mbox request and response definitions
The admin function driver sits in Linux kernel as mailbox
server. The DPDK AF mailbox client, send the message to mailbox
server to complete the administrative task such as get mac
address.

This patch adds mailbox request and response definition of
existing mailbox defined between AF driver and DPDK driver.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
2021-04-09 08:32:24 +02:00
Jerin Jacob
01bc01e1bb common/cnxk: add interrupt helper API
Add interrupt helper API's in common code to register and
unregister for specific interrupt vectors. These API's
will be used by all cnxk drivers.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2021-04-09 08:32:24 +02:00
Ashwin Sekhar T K
c92d8a70ae common/cnxk: add roc plt init callback support
Add support for registering callbacks for roc plt init.

Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2021-04-09 08:32:24 +02:00
Jerin Jacob
014a9e222b common/cnxk: add model init and IO handling API
Add routines for SoC model identification and HW IO handling
routines specific to CN9K and CN10K Marvell SoC's.
These are based on arm64 ISA and behaviour specific to
Marvell SoC's.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>
Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
2021-04-09 08:32:24 +02:00
Jerin Jacob
fa8f86a14e common/cnxk: add build infrastructre and HW definition
Add meson build infrastructure along with HW definition
header file.

This patch also adds cross-compile configs for arm
for CN9K series and CN10K series of Marvell SoC's.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
2021-04-09 08:32:24 +02:00
Suanming Mou
f205429101 common/mlx5: add user memory registration bits
This commit adds the UMR capability bits.

Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
2021-04-08 22:42:48 +02:00
Thomas Monjalon
b164198729 drivers: align log names
The log levels are configured by using the name of the logs.
Some drivers are aligned to follow a common log name standard:
	pmd.class.driver[.sub]
Some "common" drivers skip the "class" part:
	pmd.driver.sub

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Rosen Xu <rosen.xu@intel.com>
Acked-by: Xiao Wang <xiao.w.wang@intel.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Acked-by: Min Hu (Connor) <humin29@huawei.com>
2021-04-08 18:32:31 +02:00
Thomas Monjalon
3be42081ba drivers: fix log level after loading
When compiled as a shared object, and loaded at runtime as a plugin,
the drivers should get the log level set earlier at EAL init
by the user through --log-level option.

The function for applying the log level setting is
rte_log_register_type_and_pick_level().
It is called by most drivers via RTE_LOG_REGISTER().

The drivers common/mlx5, bcmfs and e1000 were missing,
so the user-specified log level was not applied when
those drivers were loaded as plugins.
The macro RTE_LOG_REGISTER() is used for those drivers.

The unnecessary protection for double registration
is removed from e1000.

Fixes: 9c99878aa1 ("log: introduce logtype register macro")
Fixes: c8e79da7c6 ("crypto/bcmfs: introduce BCMFS driver")
Cc: stable@dpdk.org

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Reviewed-by: David Marchand <david.marchand@redhat.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
2021-04-08 18:32:31 +02:00
David Marchand
56ea803e87 build: remove Windows export symbol list
Rather than have two files that keeps getting out of sync, let's
annotate the version.map to generate the Windows export file.

Some mlx5 symbols (haswell_broadwell_cpu, mlx5_glue, mlx5_os_*) were
only exported for Windows.
All of them are available and used by Linux too, so this patch adds
them in version.map.

Note: Existing version.map annotation achieved with:
$ for dir in lib/librte_eal drivers/common/mlx5; do
    ./buildtools/map-list-symbol.sh $dir/*.map |
    while read file version sym; do
      ! git grep -qw $sym $dir/*.def || continue;
      sed -i -e "s/$sym;/$sym; # WINDOWS_NO_EXPORT/" $dir/*.map;
    done;
  done

Signed-off-by: David Marchand <david.marchand@redhat.com>
Tested-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
2021-04-08 17:57:33 +02:00
Thomas Monjalon
4d509afa7b pci: rename catch-all ID
The name of the constant PCI_ANY_ID was missing RTE_ prefix.
It is renamed, and the old name becomes a deprecated alias.

While renaming, the duplicate definitions in rte_bus_pci.h
are removed to keep only those in rte_pci.h.
Note: rte_pci.h is included in rte_bus_pci.h

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Reviewed-by: Parav Pandit <parav@nvidia.com>
Reviewed-by: David Marchand <david.marchand@redhat.com>
2021-04-06 14:52:49 +02:00
Xueming Li
59df97f1a8 common/mlx5: support sub-function representor parsing
This patch supports representor name parsing for SF.
In sysfs, representor name stored under "phys_port_name" sysfs key,
similar to VF representor, switch port name of SF representor is
"pf<x>sf<y>".

For netlink message, net SF type is supported.

Examples:

pf0sf1
pf0sf[0-3]

Signed-off-by: Xueming Li <xuemingl@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2021-03-31 09:16:23 +02:00
Satheesh Paul
5cf9911717 net/octeontx2: support raw flow pattern
Add support for rte_flow_item_raw to parse custom L2 and L3 protocols.

Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2021-03-20 15:16:55 +01:00
Andrew Rybchenko
db4a78b53f common/sfc_efx: remove GENEVE from supported tunnels
The first GA of the SN1022 does not support Geneve.

Fixes: d874d2a149 ("common/sfc_efx/base: support UDP tunnel operations for EF100")
Cc: stable@dpdk.org

Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
2021-03-22 18:05:39 +01:00
Ivan Malov
0f6b017bd8 common/sfc_efx/base: support adding decap action to a set
The action has no arguments.

Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
2021-03-22 17:19:16 +01:00
Ivan Malov
3907defa5b common/sfc_efx/base: support adding encap action to a set
For convenience, there are two separate APIs provided, one for
adding the action and one for setting the encap. header ID.
This design allows the client driver to first build the action
set specification (which validates the order of the actions)
and, if everything is correct, proceed with allocation of the
resource utilised by the action set (encap. header). This
facilitates clarity of the client code and its efficiency.

Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
2021-03-22 17:19:16 +01:00
Ivan Malov
308331681c common/sfc_efx/base: support encap header provisioning
Let the client allocate / free encap. headers.

Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
2021-03-22 17:19:16 +01:00
Natanael Copa
e9fd4b87f0 bus/dpaa: fix build with musl
The header files argp.h and error.h do not exist in musl libc.

Fix build with musl libc by using err(3) instead of
the GNU-specific error(3).

We could have used the identical errx("...: %s", strerror(ret))` but
strerror(3) is not thread-safe and the strerror_r variant has two
incompatible versions, one GNU specific and one XSI-compliant.
Avoid the mess by letting "err" use the thread-local errno.

This also fixes error message for kzmalloc failures which previously
would always have given "Unknown error -1", since that is what
strerror(-1) returns. Let "err" use the proper error message from errno
which is set by kzalloc.

Fixes: 9d32ef0f5d ("bus/dpaa: support creating dynamic HW portal")
Fixes: f09ede6c8f ("bus/dpaa: add BMAN driver core")
Fixes: 5b22cf7446 ("bus/dpaa: introducing FMan configurations")
Fixes: 39f373cf01 ("bus/dpaa: add compatibility and helper macros")
Cc: stable@dpdk.org

Signed-off-by: Natanael Copa <ncopa@alpinelinux.org>
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Acked-by: David Marchand <david.marchand@redhat.com>
2021-03-23 08:41:05 +01:00
Natanael Copa
69cb391787 common/dpaax/caamflib: simplify log macros
Simplify pr_debug, pr_err and pr_warn macros by adding an intermediate
pr_msg macro. This way we only need to test for SUPPRESS_PRINTS once.

Signed-off-by: Natanael Copa <ncopa@alpinelinux.org>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Acked-by: David Marchand <david.marchand@redhat.com>
2021-03-23 08:41:05 +01:00
Natanael Copa
8bf3ff3c37 common/dpaax/caamflib: fix build with musl
The swab16/swab32/swab64 are Linux specific and not GNU libc specific.
Keep the check for __GLIBC__ just in case other GNU systems depends on
this (Hurd or GNU/kFreeBSD).

This fixes a build error with musl libc.

Fixes: 04711d41a8 ("crypto/dpaa2_sec: add run-time assembler for descriptor")
Cc: stable@dpdk.org

Signed-off-by: Natanael Copa <ncopa@alpinelinux.org>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Acked-by: David Marchand <david.marchand@redhat.com>
2021-03-23 08:41:05 +01:00
Thomas Monjalon
e0ae50c687 build: remove redundant _GNU_SOURCE definitions
The feature macro _GNU_SOURCE is defined globally,
but there was some remaining useless settings.

The internal definition in config/meson.build is kept,
all other internal definitions of _GNU_SOURCE are removed,
except in examples, which can be built as external applications.
Note: external applications do not inherit of _GNU_SOURCE.

Fixes: 5d7b673d5f ("mk: build with _GNU_SOURCE defined by default")
Fixes: 28188cee2a ("build: enable BSD features visibility for FreeBSD")
Fixes: e6cdc54cc0 ("net/mlx5: add socket server for external tools")
Cc: stable@dpdk.org

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Acked-by: David Marchand <david.marchand@redhat.com>
2021-03-23 08:41:05 +01:00
Viacheslav Ovsiienko
569ffbc981 common/mlx5: add timestamp format support to DevX
This patch handles the NIC-supported timestamp formats via DevX.
Two different timestamp formats can be provided potentially.
The free-running format provides opaque values captured from
the internal clock counter fed by some independent oscillator.
The free-running frequency is not pre-defined and should be
queried from the NIC. The real-time timestamps are expressed
in nanoseconds, captured from the dedicated UTC counter, that
can be adjusted on the fly and synchronized with some external
reference clock.

Depending on the version and configuration the hardware might
support either FR (free-running) or RT (real-time) timestamps,
per queue basis.

The commit provides the querying information about the supported
timestamp formats and provides the means to configure ones
at queue creation time.

Fixes: e2b4925ef7 ("net/mlx5: support Direct Rules E-Switch")
Cc: stable@dpdk.org

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
2021-03-16 10:05:32 +01:00
Thomas Monjalon
1b9e9826ad common/mlx5: remove extra line feed in log messages
The macro DRV_LOG already includes a terminating line feed character
defined in PMD_DRV_LOG_.
The extra line feeds added in some messages are removed.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-03-15 14:30:57 +01:00
Thomas Monjalon
87acdcc78d net/mlx5: enable debug logs dynamically
Most debug logs are using DRV_LOG(DEBUG,)
but some were using DEBUG().
The macro DEBUG is doing nothing if not compiled with
RTE_LIBRTE_MLX5_DEBUG.

As it is not used in the data path, the macro DEBUG
can be replaced with DRV_LOG.
Then all debug logs can be enabled at runtime with:
	--log-level pmd.net.mlx5:debug

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Matan Azrad <matan@nvidia.com>
2021-03-15 14:30:55 +01:00
Vijay Kumar Srivastava
7178fbdce1 common/sfc_efx: move function to get family
Move function to get efx family from net driver into common driver.

Signed-off-by: Vijay Kumar Srivastava <vsrivast@xilinx.com>
Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
2021-03-16 12:39:42 +01:00
Vijay Kumar Srivastava
1adaea57ca common/sfc_efx: support getting device class
Device class argument would be used to select compatible driver.
Driver probe would be skipped for incompatible device class.

Signed-off-by: Vijay Kumar Srivastava <vsrivast@xilinx.com>
Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
2021-03-16 12:39:41 +01:00
Vijay Kumar Srivastava
b8a896ab97 common/sfc_efx/base: support verifying virtio features
Add an API to verify virtio features supported by device.

Signed-off-by: Vijay Kumar Srivastava <vsrivast@xilinx.com>
Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
2021-03-16 12:39:41 +01:00
Vijay Kumar Srivastava
46d2b38ba9 common/sfc_efx/base: support getting virtio features
Add an API to get virtio features supported by device.

Signed-off-by: Vijay Kumar Srivastava <vsrivast@xilinx.com>
Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
2021-03-16 12:39:41 +01:00
Vijay Kumar Srivastava
ce05513b08 common/sfc_efx/base: add virtio build dependency
Add EFSYS_HAS_UINT64 build dependency on EFSYS_OPT_VIRTIO.
virtio features are represented as bitmask in 64-bit unsigned
integer.

Signed-off-by: Vijay Kumar Srivastava <vsrivast@xilinx.com>
Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
2021-03-16 12:39:41 +01:00
Vijay Srivastava
ec03ce6909 common/sfc_efx/base: support getting virtq doorbell offset
Add an API to query the virtqueue doorbell offset in the BAR for a VI.
For vDPA, the virtio net driver notifies the device directly by writing
doorbell. This API would be invoked from vDPA client driver.

Signed-off-by: Vijay Srivastava <vijays@solarflare.com>
Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
2021-03-16 12:39:41 +01:00
Vijay Srivastava
4dda72dbde common/sfc_efx/base: add base virtio support for vDPA
In the vDPA mode, only data path is offloaded in the hardware and
control path still goes through the hypervisor and it configures
virtqueues via vDPA driver so new virtqueue APIs are required.

Implement virtio init/fini and virtqueue create/destroy APIs.

Signed-off-by: Vijay Srivastava <vijays@solarflare.com>
Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
2021-03-16 12:39:41 +01:00
Andrew Rybchenko
672386c1e9 common/sfc_efx: update copyright year
Bump copyright year to 2021.

Signed-off-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
2021-03-12 15:57:16 +01:00
Matan Azrad
750e48c7d8 common/mlx5: add DevX commands for queue counters
A queue counter set is an HW object that can be assigned to any RQ\QP
and it counts HW events on the assigned QPs\RQs.

Add DevX API to allocate and query queue counter set object.

The only used counter event is the "out of buffer" where the queue
drops packets when no SW buffer is available to receive it.

Cc: stable@dpdk.org

Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2021-03-03 17:27:19 +01:00
Matan Azrad
542689e92e common/mlx5: add DevX command to query WQ
Add a DevX command to query Rx queues attributes created by VERBS.

Currently support only counter_set_id attribute.

This counter ID is managed by the kernel driver and being assigned to
any queue created by the kernel.

Cc: stable@dpdk.org

Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
2021-03-03 17:27:18 +01:00