When Rx queue is created by VERBS API ibv_create_wq there is a dedicated
rdma-core API to query an information about this WQ(Work Queue).
VERBS WQ querying is needed for PMD cases which combine VERBS objects
with DevX objects.
Next feature to use this glue function is the HW queue counters.
Cc: stable@dpdk.org
Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Previous patch included a glue function call, with wrong size
calculation for an output buffer.
This patch fixes the issue, using the correct size calculation.
Fixes: bb7ef9a962 ("common/mlx5: add register access DevX routine")
Cc: stable@dpdk.org
Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
As the internal MAC table is divided into Unicast and Multicast address
sections, we should check the type of synced MAC address before storing
it to the internal table. Currently the check is not done, and the
synced MAC of 33:33:00:00:00:01 gets stored in the unicast section
(mostly index 1) causing all subsequent mlx5_set_mc_addr_list()
to fail with error -EADDRINUSE, as the mac_list contains the MAC
33:33:00:00:00:01. This denies adding of any new multicast address to
the internal list and also fails to add the MAC address to the device
in case of SR-IOV VF.
Fixes: f22442cb5d ("net/mlx5: reduce Netlink commands dependencies")
Fixes: ccdcba53a3 ("net/mlx5: use Netlink to add/remove MAC addresses")
Cc: stable@dpdk.org
Signed-off-by: Souvik Dey <sodey@rbbn.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
miniCQE formats for Flow Tag and L3/L4 Header compression are only
supported by Mellanox FW starting version 16.29.392. There is no
point to allow user to enable these formats if FW cannot provide them.
Check FW capabilities and deny user requests if the selected miniCQE
format is not supported by an underlying NIC.
Fixes: 54c2d46b16 ("net/mlx5: support flow tag and packet header miniCQEs")
Cc: stable@dpdk.org
Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Existing names of the flags denoting flow meter capability are unclear
and may be misleading.
This patch updates the names to align with the updated documentation.
Comments were edited, describing the names clearly.
Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Device id to be probed by octeontx_ep raw device pmd is changed from
B203 to B204. B203 is for octeontx_ep net device pmd to probe.
Signed-off-by: Nalla Pradeep <pnalla@marvell.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
Define hardware ID for GTP TEID modification. This value
can be used later in the RTE modify field API.
Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Update function mlx5_devx_cmd_query_hca_attr() to add the
reg_c_preserve bit query.
The stored metadata in register C may be lost in NIC Tx and
FDB egress while doing one of the following operations:
- packet encapsulation.
- packet mirroring (multiple processing paths).
- packet sampling (using Flow Sampler).
If the reg_c_preserve bit is set to 1, then the above
limitation is obsolete, the all metadata registers Cx
preserve their values even through the operations mentioned
above.
Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
In order to support enable/disable VLAN filtering the VF has to
negotiate the capability via VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2. If
VIRTCHNL_VLAN_TOGGLE is allowed for the VLAN filtering capabilities,
then there needs to be a method to allow this. Make the necessary
changes to support this.
Also, since the virtchnl_vlan_offload message has the desired format,
change the structure name to virtchnl_vlan_setting so it can be used for
VIRTCHNL_OP_ENABLE_VLAN_FILTERING_V2 and
VIRTCHNL_OP_DISABLE_VLAN_FILTERING_V2.
Signed-off-by: Brett Creeley <brett.creeley@intel.com>
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
Add a new compress PMD for Mellanox devices.
The MLX5 compress driver library provides support for Mellanox
BlueField 2 families of 25/50/100/200 Gb/s adapters.
GGAs (Generic Global Accelerators) are offload engines that can be used
to do memory to memory tasks on data.
These engines are part of the ARM complex of the BlueField 2 chip, and
as such they do not use NIC related resources (e.g. RX/TX bandwidth).
They do share the same PCI and memory bandwidth.
So, using the BlueField 2 device, the compress class operations can be
run in parallel to the net, vdpa, and regex class operations.
This driver is depending on rdma-core like the other mlx5 PMDs, also it
is going to use mlx5 DevX to create HW objects directly by the FW.
Add the probing functions, PCI bus connectivity, HW capabilities checks
and some basic objects preparations.
Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Meson can use cmake as a fallback for detecting packages, and this can
lead to picking up 64-libs for 32-bit builds. To work around this, force
the use of pkg-config only for detecting libcrypto, zlib, jansson and
other package dependencies.
Cc: stable@dpdk.org
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Tested-by: Ruifeng Wang <ruifeng.wang@arm.com>
Tested-by: Liron Himi <lironh@marvell.com>
Tested-by: Lee Daly <lee.daly@intel.com>
Tested-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Tested-by: Martin Spinler <spinler@cesnet.cz>
As announced in the deprecation note, remove all compatibility build
defines from previous make/meson versions and use only the standardized
ones - RTE_LIB_<name> for libraries, and RTE_<CLASS>_<NAME> for drivers.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
An application may submit all-zeros masks for a given field
to be used in two given specifications and, in the meantime,
use different unmasked values. Later on, when compared, the
two specifications will prove unequal, and, if the rules in
question are outer, the client driver will have to allocate
a separate rule for the second specification. Provided that
all other match criteria are the same, the HW will deem the
two outer rules being duplicates, which is in fact the case.
Apply masks to values in efx_mae_match_spec_field_set() API
to fix the issue and avoid duplicate outer rule allocations.
Fixes: 370ed675a9 ("common/sfc_efx/base: support setting PPORT in match spec")
Cc: stable@dpdk.org
Reported-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
TLV object is a special firmware maintained entity used
to support match on GENEVE header extension option.
The TLV object is created with DevX API and accepts
the option class, type and lehgth fields.
The class type and length fields are set using MLX5_SET
and the Devx object is created using mlx5 glue function.
Signed-off-by: Shiri Kuzin <shirik@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
This is preparation step to support match on GENEVE TLV option.
In this Patch we add the HCA attributes that will allow
supporting GENEVE TLV option matching.
Signed-off-by: Shiri Kuzin <shirik@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
A field ID passed to the API may point to a gap in the array
of field descriptors. Turn down such invocations as improper.
Fixes: 370ed675a9 ("common/sfc_efx/base: support setting PPORT in match spec")
Cc: stable@dpdk.org
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
The helper exits once it encounters a field which hasn't its
capability status reported by the FW. Handle the corner case
when the two mask-value pairs match for the field, which, in
the absence of capability information, is sufficient to deem
the class unaffected by the field. Explain this in a comment.
Fixes: bb71f7e0a3 ("common/sfc_efx/base: add match specs class comparison API")
Cc: stable@dpdk.org
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
A particular FW version is aware of some set of match fields.
Depending on FW configuration and match specification type, a
known field may not necessarily be allowed to have a non-zero
mask. FW communicates such restrictions via field capabilities
MCDI. Newer FW may be aware of more fields. For such fields,
older FW simply does not report any capabilities.
A situation may occur when libefx is aware of a match field
which the FW is unaware of (eg., older FW), that is, FW does
not report capability status for this field. In this case,
libefx must consider such field as unsupported and demand
all-zeros mask for it when validating match specifications.
Currently, the helper in question simply exits and reports
that the specification is valid when it encounters a field
with no capability status available. This is clearly wrong.
Introduce the missing check to fix the problem.
Fixes: 34285fd089 ("common/sfc_efx/base: add match spec validate API")
Cc: stable@dpdk.org
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
MPORT values derived by helper functions are little-endian.
At the same time, MCDIs which consume these values perform
one more host-order to little-endian conversion internally.
Fix the helper functions to return host-order MPORT values.
Fixes: 370ed675a9 ("common/sfc_efx/base: support setting PPORT in match spec")
Fixes: bb024542ff ("common/sfc_efx/base: add API for adding action drop")
Fixes: 097058033f ("common/sfc_efx/base: add API to get mport of PF/VF")
Cc: stable@dpdk.org
Reported-by: Andy Moreton <amoreton@xilinx.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
This is a preparation step to support GTP extension header.
In this patch we add the matcher fields that will be
used to match on the GTP extension header.
Signed-off-by: Shiri Kuzin <shirik@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
This patch adds support for AES_CMAC integrity in non-security mode.
This patch modifies the camm flib to handles the AES CMAC
without conflicting the proto ALG operations. i.e. by creating
another ALG operation routine.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
The descriptor sharing needed to be changed for ZUC+ZUC as we
were getting invalid CHA combination error due to sharing
being done on DECOs simultaneously.
Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
CN98xx SoC comes up with two CPT blocks wrt
CN96xx, CN93xx, to achieve higher performance.
Adding support to allocate all LFs of VF with even BDF from CPT0
and all LFs of VF with odd BDF from CPT1.
If LFs are not available in one block then they will be allocated
from alternate block.
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
Enable mlx5 common driver on Windows with clang compilation.
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
While compiling with clang 11 the callers of the
__mlx5_bit_off macro warns on the cast of pointers to
unsigned long which is a smaller int type in Windows.
warning: cast to smaller integer type 'unsigned long'
from 'u8 (*)[16]' [-Wpointer-to-int-cast]
To resolve it the type is changed to uintptr_t to be
compatible for both Linux and Windows.
Fixes: 865a0c1567 ("net/mlx5: add Direct Verbs prepare function")
Cc: stable@dpdk.org
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
The mlx5_devx_dbr_page structure was used to allocate and release the
umem of the doorbells.
Since doorbell and buffer have used same umem, this structure is
useless.
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
The RQ object in DevX is used currently only in net driver, but it is
shared for future.
Add a structure that contains all the resources, and provide creation
and release functions for it.
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
The SQ object in DevX is created in several places and in several
different drivers.
In all places almost all the details are the same, and in particular the
allocations of the required resources.
Add a structure that contains all the resources, and provide creation
and release functions for it.
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
The PRM calculates page size in 4K, so need to reduce the log_wq_pg_sz
attribute.
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
The CQ object in DevX is created in several places and in several
different drivers.
In all places almost all the details are the same, and in particular the
allocations of the required resources.
Add a structure that contains all the resources, and provide creation
and release functions for it.
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
According to the current data-path implementation in the PMD the CQE
size must follow the cache-line size.
So, the configuration of the CQE size should be depended in
RTE_CACHE_LINE_SIZE.
Wrongly, part of the CQE creations didn't follow it exactly what caused
an incompatibility between HW and SW in the data-path when working in
128B cache-line size systems.
Adjust the rule for any CQE creation.
Remove the cqe_size attribute from the DevX CQ creation command and set
it inside the command translation according to the cache-line size.
Fixes: 79a7e409a2 ("common/mlx5: prepare support of packet pacing")
Fixes: 5cd0a83f41 ("common/mlx5: support more fields in DevX CQ create")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Adding support to parse 24B custom L2 header. Added devargs support to
configure the PKIND, and removed the restriction to support custom
headers on non SDP interface.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Add new opcode VIRTCHNL_OP_DCF_VLAN_OFFLOAD to set VLAN offload
by DCF, the virtchnl message includes:
1. A valid target VF
2. Type of VLAN to be supported: outer or inner
3. Ethertype of the VLAN (either 0x8100 or 0x88A8 or 0x9100)
4. VLAN insert settings
a). No insert offload, VLAN ID in the packet (default)
b). Offload via transmit descriptor
c). Insert as a port VLAN (via VSI)
5. VLAN strip settings
a). Strip (and discard)
b). Strip and place in descriptor
c). No Strip
6. VLAN ID for the target VF
Signed-off-by: Qiming Yang <qiming.yang@intel.com>
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Currently VIRTCHNL only allows for VLAN filtering and offloads to happen
on a single 802.1Q VLAN. Add support to filter and offload on inner,
outer, and/or inner + outer VLANs.
This is done by introducing the new capability
VIRTCHNL_VF_OFFLOAD_VLAN_V2. The flow to negotiate this new capability
is shown below.
1. VF - sets the VIRTCHNL_VF_OFFLOAD_VLAN_V2 bit in the
virtchnl_vf_resource.vf_caps_flags during the
VIRTCHNL_OP_GET_VF_RESOURCES request message. The VF should also set
the VIRTCHNL_VF_OFFLOAD_VLAN bit in case the PF driver doesn't
support the new capability.
2. PF - sets the VLAN capability bit it supports in the
VIRTCHNL_OP_GET_VF_RESOURCES response message. This will either be
VIRTCHNL_VF_OFFLOAD_VLAN_V2, VIRTCHNL_VF_OFFLOAD_VLAN, or none.
3. VF - If the VIRTCHNL_VF_OFFLOAD_VLAN_V2 capability was ACK'd by the
PF, then the VF needs to request the VLAN capabilities of the
PF/Device by issuing a VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2_CAPS request.
If the VIRTCHNL_VF_OFFLOAD_VLAN capability was ACK'd then the VF
knows only single 802.1Q VLAN filtering/offloads are supported. If no
VLAN capability is ACK'd then the PF/Device doesn't support hardware
VLAN filtering/offloads for this VF.
4. PF - Populates the virtchnl_vlan_caps structure based on what it
allows/supports for that VF and sends that response via
VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2_CAPS.
After VIRTCHNL_OP_GET_OFFLOAD_VLAN_V2_CAPS is successfully negotiated
the VF driver needs to interpret the capabilities supported by the
underlying PF/Device. The VF will be allowed to filter/offload the
inner 802.1Q, outer (various ethertype), inner 802.1Q + outer
(various ethertypes), or none based on which fields are set.
The VF will also need to interpret where the VLAN tag should be inserted
and/or stripped based on the negotiated capabilities.
Also, update the virtchnl_op_str() function to support the added opcodes.
Signed-off-by: Brett Creeley <brett.creeley@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Building with gcc 10.2 with SVE extension enabled got error:
{standard input}: Assembler messages:
{standard input}:4002: Error: selected processor does not support `mov z3.b,#0'
{standard input}:4003: Error: selected processor does not support `whilelo p1.b,xzr,x7'
{standard input}:4005: Error: selected processor does not support `ld1b z0.b,p1/z,[x8]'
{standard input}:4006: Error: selected processor does not support `whilelo p4.s,wzr,w7'
This is because inline assembly code explicitly resets cpu model to
not have SVE support. Thus SVE instructions generated by compiler
auto vectorization got rejected by assembler.
Added SVE to the cpu model specified by inline assembly for SVE support.
Not replacing the inline assembly with C atomics because the driver relies
on specific LSE instruction to interface to co-processor [1].
Fixes: 8a4f835971 ("common/octeontx2: add IO handling APIs")
Cc: stable@dpdk.org
[1] https://mails.dpdk.org/archives/dev/2021-January/196092.html
Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
This patch introduces new parameters for VirtQ CQ moderation, used for
performance tuning.
Signed-off-by: Xueming Li <xuemingl@nvidia.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Wrap glue calls dr_create_flow_action_sampler() and
dr_create_flow_action_dest_array() as OS-specific functions.
This is a follow up on
commit b293fbf967 ("net/mlx5: add OS specific flow actions operations")
On Windows, the sampling actions wrappers currently return ENOTSUP.
Using configuration definitions HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE and
HAVE_MLX5_DR_CREATE_ACTION_DEST_ARRAY the missing sampling DV structs
are added as stubs to windows/mlx5_glue.h file.
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
This commit implements mlx5_flow_os_create_flow() API. It is equivalent
to Linux rdma-core implementation. The API receives the matcher mask,
matcher value and an array of actions. They are copied into a PRM-like
struct devx_fs_rule_add_in. Then glue API devx_fs_rule_add() is called.
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
This commit implements mlx5_flow_os_create_flow_action_dest_devx_tir()
API as the Linux rdma-core equivalent. Missing rdma-core parameters are
added to file mlx5_win_defs.h. The action TIR id and type
(MLX5_FLOW_CONTEXT_DEST_TYPE_TIR) are saved in the action struct. The
action struct will be added to array of actions and will be used later
by the flow creation API.
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
This commit implements the mlx5_flow_os_create_flow_matcher() API. It is
the Linux rdma-core equivalent implementation. Missing rdma-core
parameters (e.g. struct mlx5dv_flow_match_parameters) are added to file
mlx5_win_defs.h. The API allocates space to hold the PRM bits in PRM
fte_match_param format and copy the DV translated PRM bits into the
matcher struct. This matcher struct will be used later by the flow
creation API.
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
This patch adds the initial flow framework under Windows OS. It supports
a subset of filters (ETH, IPV4, UDP) and a QUEUE action. It is based on
DevX mechanism to send commands to the NIC through the kernel. It does
not support steering rules (i.e. writing directly to the NIC memory).
The Windows framework uses the existing DV framework where file
mlx5_flow_dv.c remains intact.
Steps involved in flow creation:
1. Create a domain (RX, TX, FDB). Since domains are created by steering
rules and not with DevX, Windows does not require a domain object (this
means switch dev mode which requires an FDB domain is not supported).
2. Create a table object. Windows only supports table 0. The call to
mlx5_flow_os_create_flow_tbl() silently returns successfully.
3. Create a matcher object. A matcher struct is created by calling
mlx5_flow_os_create_flow_matcher(). The matcher validation and
translation are part of the DV implementation. The matcher bits that
were created by DV in standard PRM format are copied into the matcher
struct.
4. Create an action object. The call to
mlx5_flow_os_create_flow_action_dest_devx_tir() creates an action struct
with the TIR type and id. This struct will be a parameter later in a
call to flow creation. All other action calls (e.g. packet reformat,
header modification, jump to flow table, etc) return with a non
supported error.
5. Create the flow. The call to mlx5_flow_os_create_flow() receives the
matcher struct, action struct, and copy them into Windows specific
fs_rule struct, then it calls glue API devx_fs_rule_add().
Details on additional APIs:
* mlx5_flow_os_get_type() is called during flow type selection. In
Windows it constantly returns MLX5_FLOW_TYPE_DV.
* mlx5_flow_os_item_supported() is called before starting DV items
validation or translation. It filters out the OS non supported items in
advance.
* mlx5_flow_os_action_supported() is called before starting DV actions
validation or translation. It filters out the OS non supported actions
in advance.
* mlx5_flow_adjust_priority() is an OS stub for flow priority
adjustment. Windows only supports flow priority 0.
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
This commit implements mlx5_dev_spawn() API which allocates an eth
device (struct rte_eth_dev) for each PCI device. When working with
representors virtual functions (as in Linux), one PCI device may spawn
several eth devices: the master device for the main physical function
(PF) and several representors for the virtual functions (VFs). However,
currently Windows does not work in switch dev mode, therefore, no VFs
are created and no representors are spawned. In this case one eth device
is created per one PCI main port. In addition to device creation - the
device configuration must be correctly set. The device arguments
(devargs - set by the user) are parsed but they may be overridden by
Windows limitations or hardware configurations. Some associated network
parameters are stored in eth device (e.g. ifindex, MAC address, MTU) and
some callback (e.g. burst functions) are set.
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
This commit implements mlx5_is_removed() API. A new glue call
'init_shutdown_event' is added to support the new API.
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
This commit adds a new glue function query_rt_values to support the new
API mlx5_read_clock().
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
This commit is the Windows equivalent of the Linux implementation.
Windows returns an error ENOTSUP for the APIs to create/destroy event
channel or to subscribe an event.
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
The following getters are added: mlx5_os_get_devx_uar_mmap_offset,
mlx5_os_get_devx_uar_base_addr, mlx5_os_get_devx_uar_reg_addr,
mlx5_os_get_devx_uar_page_id. This commit is the Windows equivalent of
the Linux implementation in [1].
[1]
commit 1f66ac5bbe ("net/mlx5: remove more Direct Verbs dependencies")
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Add #include <rte_compat.h> to file mlx5_devx_cmds.h. It is required for
Windows to identify the __rte_internal definition.
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Add missing DV and IBV definition to file mlx5_win_defs.h. The
definitions originated from rdma-core library which is not part of
Windows. They are referenced in shared files that must compile under
Windows such as mlx5_flow_dv.c and mlx5_rxtx.c.
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
This commit is the Windows implementation of mlx5_os_get_dev_attr() API.
It follows the commit in [1]. A new file named mlx5_os.c is added under
windows directory as its Linux counterpart file: linux/mlx5_os.c.
[1].
commit e85f623e13 ("net/mlx5: remove attributes dependency on Verbs")
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
This commits implements Windows API for MR registration and
deregistration. It is based on DevX. Is support the relaxed ordering
flow in Windows by checking the capabilities and machine type.
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Implement Windows API mlx5_os_umem_reg() and mlx5_os_umem_dereg(). They
are equivalent to the Linux implementation.
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Implement Windows API mlx5_os_alloc_pd() and mlx5_os_dealloc_pd().
They are equivalent to the Linux implementation in [1].
[1] ("net/mlx5: wrap glue alloc/dealloc PD with OS calls")
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Add reserved size to PRM 'struct mlx5_ifc_fte_match_param_bits' for non
Linux OS. Windows drivers require this extension since their expected
size should match the actual struct size. Linux drivers do not require
this extension and already use calculations based on the shorter size.
Use a static assert to verify that the PRM fte_match_param struct size
remains correct.
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
File mlx5_autoconf.h is generated under Windows to maintain
compatibility with the Linux build system. This file is included in
Linux/Windows shared source files therefore it is required. Currently
the file is created empty.
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Add function mlx5_glue_constructor() as an initialization routine for
run-time dependency on external lib. Currently the routine has an empty
body. It is used for compatibility with Linux.
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
File drivers/common/mlx5/windows/meson.build is added to enable mlx5
source files compilation under common windows directory.
A Devx SDK tool must be installed to export two external H files:
mlx5devx.h and mlx5_ifc_devx.h. The installation is based on environment
variable DEVX_INC_PATH. In addition a DLL lib file is installed based on
environment variable DEVX_LIB_PATH. The meson file is using the
environment variables for compilation and linkage.
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Windows glue functions are added to file mlx5/windows/mlx5_glue.c.
The following APIs are supported:
get_device_list, free_device_list, open_device, close_device,
query_device, query_hca_iseg, devx_obj_create, devx_obj_destroy,
devx_obj_query, devx_obj_modify, devx_general_cmd, devx_umem_reg,
devx_umem_dereg, devx_alloc_uar, devx_free_uar, devx_fs_rule_add,
devx_fs_rule_del, devx_query_eqn
New added files:
mlx5_win_defs.h - this file imports missing definitions from Linux
rdma-core library and Linux OS.
mlx5_win_ext.h - this file contains structs that enable a unified
Linux/Windows API. Each struct has an equivalent (but different) Linux
struct. By calling with 'void *' pointers - the Linux/Windows API is
identical.
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Add a new DevX API mlx5_devx_cmd_alloc_pd() that creates a new protection
domain (PD).
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Extend DevX API mlx5_devx_cmd_query_hca_attr() to report on max number
of available objects including: CQ, QP, PD, SRQ.
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
File drivers/common/mlx5/rte_common_mlx5_exports.def contains mlx5
Windows exported symbols under common/mlx5 directory (DLL file
name librte_common_mlx5*.dll). It is the equivalent of Linux map
file version.map but the list of symbols may be
different between the two operating systems.
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Wrap the API to create/destroy event channel and to subscribe an event
with OS calls. In Linux those calls are implemented by glue functions
while in Windows they are not supported.
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
This commit is the Windows equivalent of the Linux implementation. The
APIs included in this commit: mlx5_os_malloc(), mlx5_os_free(). For
memory allocations (with or without alignment) we always call
_aligned_malloc(). Even if zero alignment was requested in the first
place - we always select a minimal alignment value. In this way when the
memory is free - it is always safe to call _aligned_free().
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
mlx5_malloc() API has an alignment parameter for system memory
allocations. malloc() is called for non-aligned allocations and
posix_memalign() is called for aligned allocations. When calling
mlx5_free() there is no distinction whether the memory was originally
allocated with or without alignment. Freeing a memory may be handled
differently by operating systems. Therefore this commit wraps these APIs
with OS specific calls: mlx5_os_malloc(), mlx5_os_free().
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Add a Verbs file presence indication. Under Linux it is required that
file infiniband/verbs.h is installed for building DPDK. Other
operating systems (e.g. Windows) ignore Verbs completely. This commit
adds definition HAVE_INFINIBAND_VERBS_H (file mlx5_autoconf.h) to
indicate whether DPDK compiles with Verbs or not.
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Wrap glue calls for UMEM registration and deregistration with generic OS
calls since each OS (Linux or Windows) has a different glue API
parameters.
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Wrap glue calls alloc_pd() and dealloc_pd() with generic OS calls. In
Linux - protection domain allocations are implemented by Verbs glue API
while in Windows it is by DevX API.
Signed-off-by: Ophir Munk <ophirmu@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Add eCPRI header and its field selectors, including MSG_TYPE, PCID
and RTCID. Since the offset of PCID is same as RTCID, we just add one
MACRO for these two fields. For MSG Type 0, ecpriRtcid/ecpriPcid field
within the eCPRI header will be extracted to Field Vector for FDIR and
RSS.
SPEC for eCPRI:
http://www.cpri.info/downloads/eCPRI_v_2.0_2019_05_10c.pdf
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
With pkg-config support available within musdk library
(from musdk-release-SDK-10.3.5.0-PR2 version),
meson option 'lib_musdk_dir' can be removed.
PKG_CONFIG_PATH environment variable should be set appropriately
to use the musdk library.
docs are updated with new musdk version and meson instructions.
Signed-off-by: Liron Himi <lironh@marvell.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
VFs can't control MAE, so it's important to override the general
MAE capability bit by taking MAE privilege into account. Reorder
the code slightly to have the privileges queried before datapath
capabilities are discovered and add required MAE privilege check.
Fixes: eb4e80085f ("common/sfc_efx/base: indicate support for MAE")
Cc: stable@dpdk.org
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
VFs and unprivileged PFs should not be able to control MAE.
Add MAE privilege to MCDI headers in order to reflect that.
Fixes: 84d3fb7d7e ("common/sfc_efx/base: add MAE definitions to MCDI")
Cc: stable@dpdk.org
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
If MAE slice is configured without conntrack support, outer
rules must match on IP SRC/DST. This isn't reported clearly
by the FW because IPv4 and IPv6 have separate SRC/DST pairs.
The FW reports status ALWAYS for all these four fields, and
having an all-zeros mask for either field prevents the spec
from being certified by the existing spec validation method.
Extend the spec validation to take the "alternative" fields
into account so that legitimate specs don't get turned down.
Fixes: ed15d7f8e0 ("common/sfc_efx/base: validate and compare outer match specs")
Cc: stable@dpdk.org
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Fix signed/unsigned mismatch issues found by Windows build.
Fixes: 34285fd089 ("common/sfc_efx/base: add match spec validate API")
Fixes: bb71f7e0a3 ("common/sfc_efx/base: add match specs class comparison API")
Fixes: e9d5c5fb68 ("common/sfc_efx/base: avoid reading past buffer")
Cc: stable@dpdk.org
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Windows build of the current libefx rejects these specifiers.
They're unneeded anyway; the compiler should decide inlining.
Fixes: 34285fd089 ("common/sfc_efx/base: add match spec validate API")
Cc: stable@dpdk.org
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
Existing code uses the previous API offered by rdma-core in order
to create ASO Flow Hit action.
A general API is now formally released, to create ASO action of any
type. This patch moves the MLX5 PMD code to use the formal API.
Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Starting ConnectX-6 Dx, the VF device ID is generic
and not per chip.
https://pci-ids.ucw.cz/v2.2/pci.ids
101e ConnectX Family mlx5Gen Virtual Function
This means that all will have the same VF device ID.
Fixes: 5fc66630be ("net/mlx5: add ConnectX6-DX device ID")
Cc: stable@dpdk.org
Signed-off-by: Raslan Darawsheh <rasland@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Syncing the data types of msix offset mbox response structure
fields wrt rvu_pfvf structure as in msix offset mbox handler,
respective block LFs response field is initialised with rvu_pfvf
and mismatch in the data types of respective fields may lead
to issues.
This mismatch in data types resulted in a bug where no sso msix
offsets are returned. For 256 SSO hwgrps, 256 msix offsets
are required, but since num of sso lf field (rsp->sso) in
response structure is u8 and is initialised with same field
in pfvf structure viz u16, value 256 corresponds to 0 hence
no sso_msixoff.
Similar mbox changes are required in kernel side also which are
available in marvell SDK version SDK-11.0.
Fixes: 2b71657c86 ("common/octeontx2: add mbox request and response definition")
Cc: stable@dpdk.org
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Reasons for building not supported generally start with lowercase
because printed as the second part of a line.
Other changes:
- "linux" should be "Linux" with a capital letter.
- ARCH_X86_64 may be simply x86_64.
- aarch64 is preferred over arm64.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: David Marchand <david.marchand@redhat.com>
Replaced structure 'rid' which has single field with its
field itself.
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
CPT inst word7 is an immutable data for a session.
This data can be populated in a session.
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
The mlx5_devx_cmd_create_flex_parser function defines a local array
(with constant size) named in, and then allocates a pointer to
mlx5_devx_obj structure by the mlx5_malloc function.
If the allocation fails, the function releases the array in and returns
NULL. However, the array has been defined locally on the stack and the
mlx5_free function is not required to release it.
Remove the call to the mlx5_free function.
Fixes: 66914d19d1 ("common/mlx5: convert control path memory to unified malloc")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Improve the clarity of the code.
Fixes: 833cfcd590 ("common/sfc_efx/base: add API for querying board info")
Fixes: 312191e86e ("common/sfc_efx/base: refactor version / boot info get helper")
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Recent patch introduced a new SQ for ASO flow hit management.
This SQ uses two WQEBB's for each WQE.
The SQ producer index is 16 bits wide.
The enqueue loop posts new WQEs to the ASO SQ, using WQE index for
the SQ management.
This 16 bits index multiplied by 2 was wrongly used also for SQ
doorbell ringing.
The multiplication caused the SW index overlapping to be out of sync
with the hardware index, causing it to get stuck.
This patch separates the WQE index management from the doorbell index
management.
So, for each WQE index incrementation by 1, the doorbell index is
incremented by 2.
Fixes: f935ed4b64 ("net/mlx5: support flow hit action for aging")
Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Existing field ID validity check does not validate the field
descriptor availability. Make it more rigorous to avoid
reading past the buffer containing field descriptors.
Coverity issue: 363742
Fixes: 370ed675a9 ("common/sfc_efx/base: support setting PPORT in match spec")
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>
mlx5 PMD created the MR (Memory Region) resource on the
mlx5_dma_map call to make the memory available for DMA
operations. On the mlx5_dma_unmap call the MR resource
was not freed but inserted to MR Free list for further
garbage collection.
Actual MR resource destroying happened on device stop
call. That caused the runtime out of memory in case of
application performed multiple DMA map/unmap calls.
The fix immediately frees the MR resource on mlx5_dma_unmap
call not engaging the list. The export for mlx5_mr_free
function from common PMD part is added as well.
Fixes: 989e999d93 ("net/mlx5: support PCI device DMA map and unmap")
Cc: stable@dpdk.org
Signed-off-by: Jiawei Wang <jiaweiw@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
This patch introduces the routine to allocate the UAR (User
Access Region) with various memory mapping types. The origin
patch being fixed provided the UAR allocation workaround
for the mlx5 net PMD only. As it was found the other mlx5
based drivers - vdpa and regex are affected by the issue
as well and must be fixed.
Fixes: a0bfe9d56f ("net/mlx5: fix UAR memory mapping type")
Cc: stable@dpdk.org
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
The drivers for OCTEON TX2 are not supported in 32-bit mode.
Suggested-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Jerin Jacob <jerinj@marvell.com>
The current DevX implementation of the relaxed ordering feature is
enabling relaxed ordering usage only if both relaxed ordering read AND
write are supported. In that case both relaxed ordering read and write
are activated.
This commit will optimize the usage of relaxed ordering by enabling it
when the read OR write features are supported. Each relaxed ordering
type will be activated according to its own capability bit.
This will align the DevX flow with the verbs implementation of
ibv_reg_mr when using the flag IBV_ACCESS_RELAXED_ORDERING
Fixes: 53ac93f71a ("net/mlx5: create relaxed ordering memory regions")
Cc: stable@dpdk.org
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
A new ASO (Advanced Steering Operation) feature was added in the last
mlx5 adapters to support flow hit detection.
Using this new steering action, the driver can detect flow traffic hit
and to reset this indication any time.
The ASO age action cannot support flows in table 0.
Add support for flow aging action in rte_flow using this new feature.
The counter aging mode will be taken only when the ASO feature is not
supported for the user flow groups.
Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Signed-off-by: Matan Azrad <matan@nvidia.com>
This patch adds different PRM definitions, related to ASO flow hit
feature, in MLX5 PMD code.
Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Add glue function to create the flow hit action using DV API,
if rdma-core support exists.
Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
