33440 Commits

Author SHA1 Message Date
Qi Zhang
cb02072170 net/ice/base: enable calling ETH56G functions
Enable calling of ETH56G functions in the base code when the
appropriate PHY has been detected

Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
fb800fde66 net/ice/base: work around missing PTP capabilities
Provide a WA for missing PTP caps on Simics, this code shall be
removed after cap reporting is fixed

Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
e05720c063 net/ice/base: implement 56G PHY setup functions
Implement setup functions for the 56G PHY Simics model

Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
680793c782 net/ice/base: implement 56G PHY access functions
Implement 56G PHY register and memory read/write functions
to facilitate PTP support

Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
88b32fd7cc net/ice/base: add 56G PHY register definitions
Add 56G PHY register address definitions to facilitate 56G PHY
support.

Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
f4ce264ffe net/ice/base: add 56G PHY destination address
Add PHY 56G destination address. PHY56G is a single device
incorporating all SerDes lanes

Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
85508ab0c7 net/ice/base: move code block
Move some code block to the beginning of ice_ptp_hw.c to align
with kernel driver.

Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
0fb8370005 net/ice/base: add suffix to E822-specific functions
Add the suffix to E822 HW-dependent function names

Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
5a71038ffa net/ice/base: complete health status codes
add definitions for async health status codes.

Signed-off-by: Leszek Zygo <leszek.zygo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
bc696378a9 net/ice/base: fix DSCP PFC TLV creation
When creating the TLV to send to the FW for configuring DSCP
mode PFC, the PFCENABLE field was being masked with a 4 bit
mask (0xF), but this is an 8 bit bitmask for enabled classes
for PFC.  This means that traffic classes 4-7 could not be
enabled for PFC.

Remove the mask completely, as it is not necessary, as we are
assigning 8bits to an 8 bit field.

Fixes: 8ea78b169603 ("net/ice/base: support L3 DSCP QoS")
Cc: stable@dpdk.org

Signed-off-by: Dave Ertman <david.m.ertman@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
9066f200cb net/ice/base: support VXLAN and GRE for RSS
Add RSS of inner headers for VXLAN tunnel packet.

Add packet types for packets with outer IPv4/IPv6 header
support GRE and VXLAN tunnel packet.

Following rules can use new packet types:
    - eth / ipv4(6) / udp / vxlan / ipv4(6)
    - eth / ipv4(6) / udp / vxlan / ipv4(6) / tcp
    - eth / ipv4(6) / udp / vxlan / ipv4(6) / udp
    - eth / ipv4(6) / gre / ipv4(6)
    - eth / ipv4(6) / gre / ipv4(6) / tcp
    - eth / ipv4(6) / gre / ipv4(6) / udp

Signed-off-by: Jie Wang <jie1x.wang@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
8f81056e5a net/ice/base: fix 100M speed capability
Couple of 10GBase-T devices don't support advertising 100M
speed. For these devices, ice_is_100m_speed_supported should
return false. Meanwhile add device that supports 100M speed.

Fixes: 486d29fda54c ("net/ice/base: add dedicate MAC type for E810")
Cc: stable@dpdk.org

Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
0054012bd8 net/ice/base: add auto drop blocking packets
Extended ice_aq_set_mac_cfg()function to add support for
auto drop blocking packets.

Signed-off-by: Mateusz Rusinski <mateusz.rusinski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
4e1d404e03 net/ice/base: fix division during E822 PTP init
When initializing the device hardware for PTP, the E822 devices
requirea number of values to be calculated and programmed to
hardware.These values are calculated using unsigned 64-bit
division.

The DIV_64BIT macro currently translates into a specific Linux
functionthat triggers a *signed* division. This produces incorrect
results when operating on a dividend larger than an s64. The
division calculation effectively overflows and results in totally
unexpected behavior.

In this case, the UIX value for 10Gb/40Gb link speeds are calculated
incorrectly. This ultimately cascades into a failure of the Tx
timestamps. Specifically, the reported Tx timestamps become wildly
inaccurate and not representing nominal time.

The root cause of this bug is the assumption that DIV_64BIT can
correctly handle both signed and unsigned division. In fact the
entire reason we need this is because the Linux kernel compilation
target does not provide native 64 bit division ops, and requires
explicit use of kernel functions which explicitly do either signed
or unsigned division.

To correctly solve this, introduce new functions, DIV_U64 and
DIV_S64 which are specifically intended for signed or unsigned
division. To help catch issues, use static inline functions so
that we get strict type checking.

Fixes: 97f4f78bbd9f ("net/ice/base: add functions for device clock control")
Cc: stable@dpdk.org

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
683b6ab56e net/ice/base: make function names more generic
Previously "e810t" was part of few function names.
In the future it will require to add similar functions
for different NIC types.
Make "NIC type" a suffix of the function name.

Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
f450334f47 net/ice/base: combine functions for VSI promiscuous
Remove ice_get_vsi_vlan_promisc,
cause of similar implementation as ice_get_vsi_promisc,
which will now handle the use case of ice_get_vsi_vlan_promisc.

Signed-off-by: Wiktor Pilarczyk <wiktor.pilarczyk@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
2146d23a18 net/ice/base: get NVM CSS header length from CSS header
The CSS Header length is defined as ICE_CSS_HEADER_LENGTH. To
support changes in CSS Header length, calculate the CSS Header
length from the NVM CSS Header length field plus the Authentication
Header length.

Signed-off-by: Paul Greenwalt <paul.greenwalt@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Qi Zhang
10eddf13bd net/ice/base: add netlist helper functions
Add new functions to check in netlist if HW has:
- Recovered Clock device,
- Clock Generation Unit,
- Clock Multiplexer,
- GPS generic device.

Signed-off-by: Michal Michalik <michal.michalik@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
2022-09-18 16:12:32 +02:00
Zhichao Zeng
6de9af2491 net/ice: support traffic to original DCF port
Add support for sending traffic to the original DCF port
with 'port_representor' action by using DCF port id as 'port_id'.

For example:
testpmd> flow create 0 ingress pattern any
         / end actions port_representor port_id 0 / end

Signed-off-by: Zhichao Zeng <zhichaox.zeng@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-18 16:12:27 +02:00
Jie Wang
19147456ac net/iavf: support priority of flow rule
Add flow rule attribute "priority" support for AVF.

Lower values denote higher priority, the highest priority for
a flow rule is 0.

All subscription rule will have a lower priority than the rules
that be created by host.

Signed-off-by: Jie Wang <jie1x.wang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-07 20:33:26 +02:00
Jie Wang
7b902af499 net/iavf: support flow subscription rule
Support flow subscribption create/destroy/validation flow
rule for AVF.

For examples:
testpmd> flow create 0 ingress pattern eth / ipv4 / udp src is 11
          / end actions represented_port port_id 1 / end
testpmd> flow validate 1 ingress pattern eth / ipv4 / tcp src is 22
          / end actions represented_port port_id 1 / end
testpmd> flow destroy 1 rule 0

VF subscribes to a rule, which means the packets will be sent to VF
instead of PF, and only VF will receive the packets.

It is allowed multiple VF subscribe to same rule, the packets will
be replicated and received by each VF.

PF will destroy all subscriptions during VF reset.

Signed-off-by: Jie Wang <jie1x.wang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-07 20:33:26 +02:00
Jie Wang
6d42380e59 net/iavf: add flow subscrption supported pattern
Add flow subscription pattern support for AVF.

The supported patterns are listed below:
eth/vlan/ipv4
eth/ipv4(6)
eth/ipv4(6)/udp
eth/ipv4(6)/tcp

Signed-off-by: Jie Wang <jie1x.wang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-07 20:33:26 +02:00
Jie Wang
fe10f0407e net/iavf: add flow subscription skeleton
Add the skeletal code of flow subscription to AVF driver.

Signed-off-by: Jie Wang <jie1x.wang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-07 20:33:26 +02:00
Jie Wang
096c21906a common/iavf: support flow subscription
VF is able to subscribe a flow from PF by VIRTCHNL_FLOW_SUBSCRIBE.

PF is expected to offload a rule to hardware which will redirect
the packet that matching the required pattern to this VF.

Only a flow with dst mac address as PF's mac address can be subscribed.

VIRTCHNL_VF_OFFLOAD_FSUB_PF is used for Flow subscription capability
negotiation and only a trusted VF can be granted with this capability.

A flow can be unsubscribed by VIRTCHNL_FLOW_UNSUBSCRIBE.

Signed-off-by: Jie Wang <jie1x.wang@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-07 20:33:26 +02:00
Steven Zou
c60fad5626 common/iavf: avoid copy in async mode
If cmd_details are defined or async flag is set,
don't copy the desc/buff back to temp.

Fixes: e5b2a9e957e7 ("net/avf/base: add base code for avf PMD")
Cc: stable@dpdk.org

Signed-off-by: Steven Zou <steven.zou@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-07 20:33:26 +02:00
Mah Yock Gen
4841015ffb net/igc: remove unnecessary PHY ID checks
I225 devices have only one PHY vendor. There is unnecessary to check
_I_PHY_ID during the link establishment and auto-negotiation process,
the checking also caused devices like i225-IT failed. This patch is to
remove the mentioned unnecessary checking.

Cc: stable@dpdk.org

Signed-off-by: Mah Yock Gen <yock.gen.mah@intel.com>
Signed-off-by: Taripin Samuel <samuel.taripin@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-07 20:33:26 +02:00
Kevin Liu
df539aaf35 net/ice: refactor flex descriptor protocol field extraction
The ice has the feature to extract protocol fields into flex descriptor
by programming per queue. However, the dynamic field for proto_ext are
allocated by PMD, it is the responsibility of application to reserved
the field, before start DPDK.

Application with parse the offset and proto_ext name to PMD with devargs.
Remove related private API in 'rte_pmd_ice.h' and 'rte_pmd_ice.h' file.

Signed-off-by: Kevin Liu <kevinx.liu@intel.com>
Tested-by: Jin Ling <jin.ling@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-06 14:54:56 +02:00
Radu Nicolau
eb944b5906 net/iavf: update IPsec ESN values when updating session
When updating an ingress session update the internal values before
making the virtual channel request.

Fixes: 6bc987ecb860 ("net/iavf: support IPsec inline crypto")
Cc: stable@dpdk.org

Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-06 14:54:56 +02:00
Aleksandr Miloshenko
4e868408bf net/iavf: fix Tx done descriptors cleanup
iavf_xmit_pkts() sets tx_tail to the next of last transmitted
Tx descriptor. So the cleanup of Tx done descriptors must be started
from tx_tail, not from the next of tx_tail.
Otherwise rte_eth_tx_done_cleanup() doesn't free the first Tx done mbuf
when tx queue is full.

Fixes: 86e44244f95c ("net/iavf: cleanup Tx buffers")
Cc: stable@dpdk.org

Signed-off-by: Aleksandr Miloshenko <a.miloshenko@f5.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-06 14:54:56 +02:00
Zhichao Zeng
9e984bc53b net/ice: add option to disable ACL engine in DCF
Support disabling DCF ACL engine via devarg "acl=off" in cmdline, aiming to
shorten the DCF startup time.

Signed-off-by: Zhichao Zeng <zhichaox.zeng@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-06 14:54:56 +02:00
Steve Yang
e5c7498fae net/iavf: fix pattern check for flow director parser
FDIR rules with masks are not supported in current code. Thus add
pattern check for IPv4/UDP/TCP/SCTP addr/port to terminate the FDIR
programming stage.

Fixes: d5eb3e600d9e ("net/iavf: support flow director basic rule")
Cc: stable@dpdk.org

Signed-off-by: Steve Yang <stevex.yang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-06 14:54:56 +02:00
Junfeng Guo
cf0884e4b0 net/igc: support device I225-IT
Add device id for Ethernet Controller (2) I225-IT.

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-06 14:54:56 +02:00
Yiding Zhou
0d58caa7d6 net/iavf: fix VLAN insertion
When the driver tells the VF to insert VLAN tag using the L2TAG2 field,
vector Tx path does not use Tx context descriptor and would cause VLAN tag
inserted into the wrong location.

This commit is to fix issue by using normal Tx path to handle L2TAG2 case.

Fixes: 3aa957338503 ("net/iavf: fix VLAN insert")
Cc: stable@dpdk.org

Signed-off-by: Yiding Zhou <yidingx.zhou@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-06 14:54:56 +02:00
Zhichao Zeng
776c119736 net/ice: remove deprecated VF flow action
According to the ABI and API Deprecation, remove deprecated VF action
as hard-to-use / ambiguous.

Action REPRESENTED_PORT should be used instead.

Signed-off-by: Zhichao Zeng <zhichaox.zeng@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-06 14:54:56 +02:00
Ke Zhang
817577c03a net/iavf: fix L3 checksum Tx offload flag
When ol_flag is only RTE_MBUF_F_TX_IPV4, the Tx L3
checksum offload is still configured to IIPT in the
command field of Tx data descriptor.

This patch is to fix the issue to make the Tx L3
checksum offload flags and Tx data descriptor
consistent.

Fixes: 1e728b01120c ("net/iavf: rework Tx path")
Cc: stable@dpdk.org

Signed-off-by: Ke Zhang <ke1x.zhang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-06 14:54:56 +02:00
Zhichao Zeng
c0444f6273 net/ice: support represented port flow action
Add support for action REPRESENTED_PORT in DCF. Supposed to send matching
traffic to the entity (VF) represented by the given ethdev, at embedded
switch level.

Signed-off-by: Zhichao Zeng <zhichaox.zeng@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-09-06 14:54:40 +02:00
Dexia Li
4be031d7af net/iavf: support flow matching on MAC address
Position src and dst mac bit in iavf fdir eth inset, thus
eth pattern can support src and dst mac match.

Signed-off-by: Dexia Li <dexia.li@jaguarmicro.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-08-08 11:11:30 +02:00
Ting Xu
53e7c7fcf3 net/ice/base: fix inner symmetric RSS hash in raw flow
Inner IPv4 and IPv6 symmetric RSS hash is not valid for raw pattern.
This patch fixes the issue by adding the corresponding protocol ID
for inner IPv4/6.

Fixes: 0837da2e27ae ("net/ice/base: support add HW profile for RSS raw flow")
Cc: stable@dpdk.org

Signed-off-by: Ting Xu <ting.xu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-08-08 10:51:02 +02:00
Zhichao Zeng
04887b812a net/ice: fix RSS hash update
This patch fixes the issue that the RSS does not update correctly
when the user sets it to none.

Fixes: 4717a12cfaf1 ("net/ice: initialize and update RSS based on user config")
Cc: stable@dpdk.org

Signed-off-by: Zhichao Zeng <zhichaox.zeng@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-08-08 10:45:53 +02:00
Ke Zhang
ba10df53e4 net/i40e: fix VF representor release
A segmentation fault occurs when testpmd exit.

This is due to fetching the device name from PF, PF
is freed firstly and then VF representor is called
later.

This commit fixes the bug by fetching the device
name from VF representor instead of PF.

Fixes: e391a7b7f815 ("net/i40e: fix multi-process shared data")
Cc: stable@dpdk.org

Signed-off-by: Ke Zhang <ke1x.zhang@intel.com>
Acked-by: Yuying Zhang <yuying.zhang@intel.com>
2022-08-08 10:37:41 +02:00
Ali Alnubani
9891ded2ea net: fix build with -Wpedantic
Adds the __extension__ attribute to resolve the following warning
with gcc 4.8.5 on CentOS 7:
lib/net/rte_macsec.h:38:2: error: type of bit-field 'short_length' is
  a GCC extension [-Werror=pedantic]

Fixes: 0aaf097585a6 ("ethdev: add MACsec flow item")

Signed-off-by: Ali Alnubani <alialnu@nvidia.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
2022-09-29 09:20:12 +02:00
Akhil Goyal
bbbe6c596b security: support MACsec
Added support for MACsec in rte_security for offloading
MACsec Protocol operation to inline NIC device or a crypto device.

To support MACsec we cannot just make one security session and
send with the packet to process it. MACsec specifications suggest,
it has 3 different entities - SECY Entity, SC (secure channel) and
SA (security association). And same SA can be used by multiple SCs and
similarly many SECY can have same SCs. Hence, in order to support this
many to one relationships between all entities, 2 new APIs are created -
rte_security_macsec_sc_create and rte_security_macsec_sa_create.
Flow of execution of the APIs would be as
- rte_security_macsec_sa_create
- rte_security_macsec_sc_create
- rte_security_session_create (for secy)
And in case of inline protocol processing rte_flow can be created with
rte_security action. A new flow item will be added for MACsec header.
New APIs are also created for getting SC and SA stats.

Signed-off-by: Akhil Goyal <gakhil@marvell.com>
2022-09-28 21:31:14 +02:00
Akhil Goyal
0aaf097585 ethdev: add MACsec flow item
A new flow item is defined for MACsec flows which can be
offloaded to an inline device. If the flow matches with
MACsec header, device will process as per the security
session created using rte_security APIs.
If an error comes while MACsec processing in HW, PMD will
notify with the events defined in this patch.

Signed-off-by: Akhil Goyal <gakhil@marvell.com>
Acked-by: Ori Kam <orika@nvidia.com>
2022-09-28 21:31:02 +02:00
Akhil Goyal
32ae9939d9 net: add MACsec header
Added MACsec protocol header to be used for supporting
MACsec protocol offload in hardware or directly in the application.

Signed-off-by: Akhil Goyal <gakhil@marvell.com>
Acked-by: Olivier Matz <olivier.matz@6wind.com>
Acked-by: Ori Kam <orika@nvidia.com>
2022-09-28 21:17:21 +02:00
Volodymyr Fialko
4f3c773825 eventdev: fix name of Rx conf type in documentation
Rename configuration structure type to correspond definition.

Fixes: dcc806c2638 ("eventdev: add eth Rx adapter API")
Cc: stable@dpdk.org

Signed-off-by: Volodymyr Fialko <vfialko@marvell.com>
Acked-by: Jay Jayatheerthan <jay.jayatheerthan@intel.com>
2022-09-28 13:02:55 +02:00
Naga Harish K S V
3c3328aef3 eventdev/eth_tx: add queue start/stop API
Add support to start or stop a particular queue
that is associated with the adapter.

Start function enables the Tx adapter to start enqueueing
packets to the Tx queue.

Stop function stops the Tx adapter from enqueueing any
packets to the Tx queue. The stop API also frees any packets
that may have been buffered for this queue. All in-flight packets
destined to the queue are freed by the adapter runtime until the
queue is started again.

Signed-off-by: Naga Harish K S V <s.v.naga.harish.k@intel.com>
Acked-by: Jay Jayatheerthan <jay.jayatheerthan@intel.com>
2022-09-28 05:47:38 +02:00
Pavan Nikhilesh
2367e7e0cf event/cnxk: update event vector Tx routine
Update event vector transmit routine to honor elem_offset.
Use ``rte_event_vector::elem_offset`` to report partial
vector transmission to the application when there is not
enough space in the SQ.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
2022-09-27 15:41:59 +02:00
Pavan Nikhilesh
3a304711b6 examples: update event vector free routine
Update event vector free routine to account for element
offset while freeing elements.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
2022-09-27 15:41:39 +02:00
Pavan Nikhilesh
0fbb55efa5 eventdev: add element offset to event vector
Add `rte_event_vector:elem_offset:12` bit field event vector
structure the bits are taken from `rte_event_vector::rsvd:15`.
The element offset defines the offset into the vector array
at which valid elements start.

The valid elements count will be equal to
`rte_event_vector::nb_elem`.

Update Rx/Tx adapter SW implementation to use elem_offset.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
2022-09-27 15:41:03 +02:00
Pavan Nikhilesh
a6d13f59e6 event/cnxk: disable timer resolution estimation
Disable timer resolution estimation, read TIM LF clock registers
to get the current running clock counter as estimating causes
time drift.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
2022-09-27 12:56:38 +02:00