Commit Graph

3605 Commits

Author SHA1 Message Date
Michal Krawczyk
e1e73e3229 net/ena: add Tx drops statistic
ENA device can report in the AENQ handler amount of Tx packets that were
dropped and not sent.

This statistic is showing global value for the device and because
rte_eth_stats is missing field that could indicate this value (it
isn't the Tx error), it is being presented as a extended statistic.

As the current design of extended statistics prevents tx_drops from
being an atomic variable and both tx_drops and rx_drops are only updated
from the AENQ handler, both were set as non-atomic for the alignment.

Signed-off-by: Michal Krawczyk <mk@semihalf.com>
Reviewed-by: Igor Chauskin <igorch@amazon.com>
Reviewed-by: Guy Tzalik <gtzalik@amazon.com>
2020-04-21 13:57:07 +02:00
Michal Krawczyk
8a7a73f26c net/ena: support large LLQ headers
Default LLQ (Low-latency queue) maximum header size is 96 bytes and can
be too small for some types of packets - like IPv6 packets with multiple
extension. This can be fixed, by using large LLQ headers.

If the device supports larger LLQ headers, the user can activate them by
using device argument 'large_llq_hdr' with value '1'.

If the device isn't supporting this feature, the default value (96B)
will be used.

Signed-off-by: Michal Krawczyk <mk@semihalf.com>
Reviewed-by: Igor Chauskin <igorch@amazon.com>
Reviewed-by: Guy Tzalik <gtzalik@amazon.com>
2020-04-21 13:57:07 +02:00
Zhaoyan Chen
fd5cbded9e doc: update ice guide driver/firmware/package version
Update driver/firmware/package version for DPDK20.02

Signed-off-by: Zhaoyan Chen <zhaoyan.chen@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2020-04-21 13:57:06 +02:00
Lunyuan Cui
ea0c22fd82 net/i40e: enable MAC address as flow director input set
Enable source MAC address and destination MAC address as FDIR's
input set for ipv4-other, ipv4-udp and ipv4-tcp. When OVS-DPDK is
working as a pure L2 switch, enable MAC address as FDIR input set
with Mark+RSS action would help the performance speed up. And FVL
FDIR supports to change input set with MAC address.

Signed-off-by: Lunyuan Cui <lunyuanx.cui@intel.com>
Acked-by: Beilei Xing <beilei.xing@intel.com>
2020-04-21 13:57:06 +02:00
Junyu Jiang
8f5b4af736 examples/vmdq: fix RSS configuration
In order that all queues of pools can receive packets,
add enable-rss argument to change RSS configuration.

Fixes: 6bb97df521 ("examples/vmdq: new app")
Cc: stable@dpdk.org

Signed-off-by: Junyu Jiang <junyux.jiang@intel.com>
Acked-by: Xiaoyun Li <xiaoyun.li@intel.com>
Tested-by: Yingya Han <yingyax.han@intel.com>
2020-04-21 13:57:06 +02:00
Junyu Jiang
9a82259d5d doc: add user guide for VMDq example
Currently, there is no documentation for VMDq example,
this path added the user guide for VMDq.

Signed-off-by: Junyu Jiang <junyux.jiang@intel.com>
Reviewed-by: Jingjing Wu <jingjing.wu@intel.com>
2020-04-21 13:57:06 +02:00
Xueming Li
9b1249d9ff app/testpmd: support dumping socket memory
Introduce new command to dump memory statistics of each socket,
summary, also show changes since last call.

Usage:
    dump_socket_mem

Signed-off-by: Xueming Li <xuemingl@mellanox.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
2020-04-21 13:57:06 +02:00
Wei Zhao
829c310681 net/ice: enable switch flow on DCF
DCF on CVL is a control plane VF which take the responsibility to
configure all the PF/global resources, this patch add support DCF
on to program forward rule to direct packets to VFs.

Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2020-04-21 13:57:06 +02:00
Satheesh Paul
0342232aa4 net/octeontx2: support custom L2 header
This patch adds SDP packet parsing support with custom L2 header,
adds support to include a field from custom header for flow tag
generation.

Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2020-04-21 13:57:06 +02:00
Krzysztof Kanas
3912fbde15 net/octeontx2: add TM capability
Add Traffic Management capability callbacks to provide
global, level and node capabilities. This patch also
adds documentation on Traffic Management Support.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Krzysztof Kanas <kkanas@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2020-04-21 13:57:06 +02:00
Krzysztof Kanas
a3147ae9af net/octeontx2: add Tx queue rate limit
Add Tx queue ratelimiting support. This support is mutually
exclusive with TM support i.e when TM is configured, tx queue
ratelimiting config is no more valid.

Signed-off-by: Krzysztof Kanas <kkanas@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2020-04-21 13:57:06 +02:00
Harman Kalra
100f699242 net/octeontx: support Rx/Tx checksum offload
This patch implements rx/tx checksum offload. In case of
wrong checksum received (inner/outer l3/l4) it reports the
corresponding layer which has bad checksum and also corrects
it if hw checksum is enabled on tx side.

Signed-off-by: Harman Kalra <hkalra@marvell.com>
2020-04-21 13:57:06 +02:00
Vamsi Attunuru
241a650061 net/octeontx: support flow control
Patch adds ethdev flow control set/get callback ops,
pmd enables modifying flow control attributes like
rx_pause, tx_pause, high & low water mark.

Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Acked-by: Harman Kalra <hkalra@marvell.com>
2020-04-21 13:57:06 +02:00
Harman Kalra
8b42b07eef net/octeontx: support set link up/down
Adding support for setting link up/down eth operation.
It is used to enable disable lmac.  Also implemented a
poll function for getting the link status at regular
intervals.

Signed-off-by: Harman Kalra <hkalra@marvell.com>
2020-04-21 13:57:06 +02:00
Vamsi Attunuru
56139e85ab net/octeontx: support VLAN filter offload
Patch adds support for vlan filter offload support.
MBOX messages for vlan filter on/off and vlan filter
entry add/rm are added to configure PCAM entries to
filter out the vlan traffic on a given port.

Patch also defines rx_offload_flag for vlan filtering.

Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Acked-by: Harman Kalra <hkalra@marvell.com>
2020-04-21 13:57:06 +02:00
Harman Kalra
3151e6a687 net/octeontx: support MTU
Adding support for mtu eth operation which configures mtu based
on max pkt len.

Signed-off-by: Harman Kalra <hkalra@marvell.com>
2020-04-21 13:57:06 +02:00
Harman Kalra
85221a0c7c net/octeontx: support multi segment
Adding multi segment support to the octeontx PMD. Also
adding the logic to share rx/tx ofloads with the eventdev
code.

Signed-off-by: Harman Kalra <hkalra@marvell.com>
2020-04-21 13:57:06 +02:00
Andrew Rybchenko
a0147be547 net/sfc: add Xilinx copyright
Xilinx acquired Solarflare in 2019.

Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Acked-by: James Fox <jamesfox@xilinx.com>
2020-04-21 13:57:06 +02:00
Qi Zhang
d2e5322900 doc: update ixgbe features list
Remove vector path feature list, if a feature only be supported
in non-vector path, use "P" to represent.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2020-04-21 13:57:06 +02:00
Qi Zhang
efbaaefb16 doc: update iavf features list
Remove vector path feature list, if a feature only be supported
in non-vector path, use "P" to represent.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2020-04-21 13:57:06 +02:00
Qi Zhang
271cc8c502 doc: update ice features list
Remove vector path feature list, if a feature only be supported
in non-vector path, use "P" to represent.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2020-04-21 13:57:06 +02:00
Qi Zhang
c4c7ea2465 doc: update i40e features list
Remove vector path feature list, if a feature only be supported
in non-vector path, use "P" to represent.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
2020-04-21 13:57:06 +02:00
Wisam Jaddo
dac98e8780 net/mlx5: fix zero value validation for metadata
MARK and META items are interrelated with datapath -
they might move from/to the applications in mbuf.

zero value for these items has the special meaning -
it means "no metadata are provided", not zero values
are treated by applications and PMD as valid ones.

Moreover in the flow engine domain the value zero is
acceptable to match and set, and we should allow to
specify zero values as rte_flow parameters for the
META and MARK items and actions. In the same time
zero mask has no meaning and should be rejected
on validation stage.

Fixes: fcc8d2f716 ("net/mlx5: extend flow metadata support")
Fixes: e554b672aa ("net/mlx5: support flow tag")
Fixes: 55deee1715 ("net/mlx5: extend flow mark support")
Cc: stable@dpdk.org

Signed-off-by: Wisam Jaddo <wisamm@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
2020-04-21 13:57:05 +02:00
Shiri Kuzin
53ac93f71a net/mlx5: create relaxed ordering memory regions
In the current state, when preforming read/write
transactions we must wait for a completion in order
to run the next transaction, and all transactions are
performed by order.

Relaxed Ordering is a PCI optimization which by enabling it
we allow the system to perform read/writes in a different
order without having to wait for completion and improve
the performance in that matter.

This commit introduces the creation of relaxed ordering
memory regions in mlx5.
As relaxed ordering is an optimization, drivers that
do not support it can simply ignore it and therefore
it is enabled by default.

Signed-off-by: Shiri Kuzin <shirik@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
2020-04-21 13:57:05 +02:00
Dekel Peled
a386116c20 doc: update mlx5 firmware configuration guidelines
This patch updates the MLX5 PMD documentations, adding Flex parser
settings and correcting minimal versions numbers.

Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
2020-04-21 13:57:05 +02:00
Haiyue Wang
7564d55096 net/ice: add DCF hardware initialization
Introduce the DCF (Device Config Function) feature in the ice PMD, it
works as a standalone PMD which doesn't handle the packet Rx/Tx related
things. Its hardware entity is the VF.

Add the basic DCF hardware initialization, this is specified by devarg
'cap=dcf'.

Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2020-04-21 13:57:05 +02:00
Jerin Jacob
9f8e1810f6 doc: add trace library guide
Add programmer's guide for trace library support.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: David Marchand <david.marchand@redhat.com>
2020-04-23 15:40:12 +02:00
Sunil Kumar Kori
8c8066ea6a trace: add trace mode configuration parameter
Trace library exposes --trace-mode eal parameter to configure
event record mode when ring buffers are full.

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: David Marchand <david.marchand@redhat.com>
2020-04-23 15:40:01 +02:00
Sunil Kumar Kori
44ab5377f0 trace: add trace bufsize configuration parameter
Trace library exposes --trace-bufsz EAL parameter to configure
maximum size of ring buffer where events are to be stored.

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: David Marchand <david.marchand@redhat.com>
2020-04-23 15:40:00 +02:00
Sunil Kumar Kori
8af866df8d trace: add trace directory configuration parameter
Trace library exposes --trace-dir EAL parameter to configure
directory where traces will be generated.

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: David Marchand <david.marchand@redhat.com>
2020-04-23 15:39:58 +02:00
Sunil Kumar Kori
3d26a70ae3 trace: add trace configuration parameter
Trace library exposes --trace EAL parameter to enable trace points.

Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: David Marchand <david.marchand@redhat.com>
2020-04-23 15:39:57 +02:00
Jerin Jacob
27db82c709 trace: introduce new subsystem
Define the public API for trace support.
This patch also adds support for the build infrastructure and
update the MAINTAINERS file for the trace subsystem.

The 8 bytes tracepoint object is a global variable, and can be used in
fast path. Created a new __rte_trace_point section to store the
tracepoint objects as,
- It is a mostly read-only data and not to mix with other "write"
  global variables.
- Chances that the same subsystem fast path variables come in the same
  fast path cache line. i.e, it will enable a more predictable
  performance number from build to build.

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Sunil Kumar Kori <skori@marvell.com>
Acked-by: David Marchand <david.marchand@redhat.com>
2020-04-23 15:39:06 +02:00
Ruifeng Wang
1d301a8a25 doc: add RCU integration design details
Add a section to describe a design to integrate QSBR RCU library
with other libraries in DPDK.

Signed-off-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
2020-04-22 20:46:00 +02:00
Pablo de Lara
fed5ee5f18 doc: support IPsec Multi-buffer lib v0.54
Updated AESNI MB and AESNI GCM PMD documentation guides
with information about the latest Intel IPSec Multi-buffer
library supported.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2020-04-19 23:00:23 +02:00
Adam Dybkowski
6e21c1a532 crypto/qat: support plain SHA1..SHA512 hashes
This patch adds support for plain SHA-1, SHA-224, SHA-256,
SHA-384 and SHA-512 hashes to QAT PMD.

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2020-04-19 22:45:11 +02:00
Pablo de Lara
b3aaf24de5 cryptodev: add session-less feature flag
Add feature flag for symmetric sessionless support,
so it can be checked by applications.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Tested-by: Ruifeng Wang <ruifeng.wang@arm.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-19 22:45:11 +02:00
Nicolas Chautru
65f1eecaa0 doc: add feature matrix table for bbdev
Adding missing overview page in documentation with
comparison of feature set by each available PMD implementation.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Acked-by: Niall Power <niall.power@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-19 22:34:26 +02:00
Nicolas Chautru
2d4306438c baseband/fpga_5gnr_fec: add configure function
Add configure function to configure the PF from within
the bbdev-test itself without external application
configuration the device.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Reviewed-by: Niall Power <niall.power@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-19 22:34:26 +02:00
Nicolas Chautru
44dc6faa79 baseband/fpga_5gnr_fec: add LDPC processing functions
Adding LDPC processing operations and related documentation.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Acked-by: Niall Power <niall.power@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-19 22:34:26 +02:00
Nicolas Chautru
0b5927cbcb baseband/fpga_5gnr_fec: add PMD for FPGA 5GNR FEC
Add stubs for the FPGA 5GNR FEC PMD

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Acked-by: Niall Power <niall.power@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-19 22:33:07 +02:00
Adam Dybkowski
c13cecf60f compress/qat: support IM buffer too small operation
This patch implements a special way of buffer handling when internal
QAT IM buffer is too small for Huffman dynamic compression operation.
Instead of falling back to fixed compression, the operation is now
split into multiple smaller dynamic compression requests (possible to
execute on QAT) and their results are then combined and copied into
the output buffer. This is not possible if any checksum calculation
was requested - in such case the code falls back to fixed compression
as before.

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2020-04-19 17:15:14 +02:00
Konstantin Ananyev
a2c6d3f34f crypto/aesni_mb: support CPU crypto
Add support for CPU crypto mode by introducing required handler.

Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2020-04-19 17:15:14 +02:00
Praveen Shetty
6738c0a956 examples/ipsec-secgw: support flow director
Support load distribution in security gateway application using
NIC load distribution feature (Flow Director).
Flow Director is used to redirect the specified inbound ipsec flow
to a specified queue. This is achieved by extending the SA rule syntax
to support specification by adding new action_type of <flow-direction>
to a specified <port_id> <queue_id>.

Signed-off-by: Praveen Shetty <praveen.shetty@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-19 17:15:14 +02:00
Mairtin o Loingsigh
9536622b86 crypto/aesni_mb: support DOCSIS AES-256
This patch adds support for DOCSIS AES-256 when using AESNI-MB

Signed-off-by: Mairtin o Loingsigh <mairtin.oloingsigh@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2020-04-19 17:15:14 +02:00
Anoob Joseph
a8af994b41 examples/ipsec-secgw: support 192/256 AES key sizes
Adding support for the following,
1. AES-192-GCM
2. AES-256-GCM
3. AES-192-CBC

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-19 17:15:14 +02:00
Konstantin Ananyev
664ff4b172 ring: introduce peek style API
For rings with producer/consumer in RTE_RING_SYNC_ST, RTE_RING_SYNC_MT_HTS
mode, provide an ability to split enqueue/dequeue operation
into two phases:
      - enqueue/dequeue start
      - enqueue/dequeue finish
That allows user to inspect objects in the ring without removing
them from it (aka MT safe peek).

Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
2020-04-21 12:52:55 +02:00
Konstantin Ananyev
1cc363b8ce ring: introduce HTS ring mode
Introduce head/tail sync mode for MT ring synchronization.
In that mode enqueue/dequeue operation is fully serialized:
only one thread at a time is allowed to perform given op.
Suppose to reduce stall times in case when ring is used on
overcommitted cpus (multiple active threads on the same cpu).

Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
2020-04-21 12:52:55 +02:00
Konstantin Ananyev
e6ba4731c0 ring: introduce RTS ring mode
Introduce relaxed tail sync (RTS) mode for MT ring synchronization.
Aim to reduce stall times in case when ring is used on
overcommited cpus (multiple active threads on the same cpu).
The main difference from original MP/MC algorithm is that
tail value is increased not by every thread that finished enqueue/dequeue,
but only by the last one.
That allows threads to avoid spinning on ring tail value,
leaving actual tail value change to the last thread in the update queue.

Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
2020-04-21 12:52:55 +02:00
Konstantin Ananyev
ebff988d0c ring: prepare ring to allow new sync schemes
To make these preparations two main things are done:
- Change from *single* to *sync_type* to allow different
  synchronisation schemes to be applied.
  Mark *single* as deprecated in comments.
  Add new functions to allow user to query ring sync types.
  Replace direct access to *single* with appropriate function call.
- Move actual rte_ring and related structures definitions into a
  separate file: <rte_ring_core.h>. It allows to refer contents
  of <rte_ring_elem.h> from <rte_ring.h> without introducing a
  circular dependency.

Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
2020-04-21 11:34:09 +02:00
Thomas Monjalon
b11ecebc04 doc: remove similar columns from NIC features matrix
The PMDs bnx2x and nfp have a separate column for VF.
Such separation is unneeded because the features are the same.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
2020-04-16 23:55:49 +02:00