VF is able to subscribe a flow from PF by VIRTCHNL_FLOW_SUBSCRIBE.
PF is expected to offload a rule to hardware which will redirect
the packet that matching the required pattern to this VF.
Only a flow with dst mac address as PF's mac address can be subscribed.
VIRTCHNL_VF_OFFLOAD_FSUB_PF is used for Flow subscription capability
negotiation and only a trusted VF can be granted with this capability.
A flow can be unsubscribed by VIRTCHNL_FLOW_UNSUBSCRIBE.
Signed-off-by: Jie Wang <jie1x.wang@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
If cmd_details are defined or async flag is set,
don't copy the desc/buff back to temp.
Fixes: e5b2a9e957e7 ("net/avf/base: add base code for avf PMD")
Cc: stable@dpdk.org
Signed-off-by: Steven Zou <steven.zou@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
Disable timer resolution estimation, read TIM LF clock registers
to get the current running clock counter as estimating causes
time drift.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Removed support to limit XAQ from devargs. If XAQ is limited, new add
works could run out of XAQ entries and disable the queue.
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Add support for offloading RTE_CRYPTO_CIPHER_AES_DOCSISBPI and
RTE_CRYPTO_CIPHER_DES_DOCSISBPI algorithms to symmetric crypto session.
Signed-off-by: Volodymyr Fialko <vfialko@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Errors in crypto adapter datapath can be handled gracefully. So the
error print can be moved under debug.
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
'struct roc_se_buf_ptr ctx_buf' has fields for a pointer and len.
The field for len was unused.
It is removed and the required pointer is added in the parent struct.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
This commit fixes answer sent to physical device in
vf2pf communication.
Fixes: b17d16fb47b4 ("common/qat: add PF to VF communication")
Cc: stable@dpdk.org
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
Arm port of ipsec_mb library [1] has different header file name than
the Intel ipsec_mb library. Proper header name is picked according to
the architecture to get the code compile when ipsec_mb is installed on
Arm platform.
And the Arm port currently supports ZUC and SNOW3g. Call to other
algorithms will be blocked.
[1] https://gitlab.arm.com/arm-reference-solutions/ipsec-mb/-/tree/main
Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Acked-by: Ashwin Sekhar T K <asekhar@marvell.com>
This patch add in libcrypto version check before enable libipsec-mb for
QAT. The intel-ipsec-mb lib for partial hash and AES calculation should
only be enabled when both OpensSSL 3.0 and IPSec_MB 1.2.0 are installed
on the system.
Fixes: 3227bc7138f5 ("crypto/qat: use intel-ipsec-mb for partial hash and AES")
Cc: stable@dpdk.org
Signed-off-by: Kai Ji <kai.ji@intel.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
When dumping hardware flow data, print any counter
configured on the flow as well.
Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Reviewed-by: Kiran Kumar K <kirankumark@marvell.com>
Add helper API to complete device info for debug purposes.
This is used by ethdev dump API to dump ethdev's internal info.
Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
Update CQ threshold limit associated with sq.
This is used when we need completions for packets that are
successfully transmitted.
Signed-off-by: Kommula Shiva Shankar <kshankar@marvell.com>
Added mailbox for masking and setting nix_rq_ctx
parameters and enabling rq masking in ipsec_cfg1
so second pass is applied to all RQ's
Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
Updated shaper profile with user configurable RED algorithm.
This helps in configuring a TM node in red drop mode vs
stall mode.
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
This patch set enables aging on CNF105 variant of CN10K platform.
Enables aging statistics while dumping/reset SQ statistics.
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Use the Full context SA structures and command in IPsec fast path.
For inline outbound, populate CPT instruction as per full context.
Added new macros and functions with respect to full context.
Populate WQE ptr in CPT instruction with proper offset from mbuf.
Also add option to override outbound inline SA IV for debug
Update mbuf length based on IP version in Rx post process purposes
via environment variable.
User can set env variable as:
export ETH_SEC_IV_OVR="0x0, 0x0,..."
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add support to create zero aura for inline inbound meta packets when
platform supports it.
AURA zero will hold as many buffers as all the available
pkt pool with a data to accommodate 384B in best case to store
meta packets coming from Inline IPsec.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Update attributes to pools used by NIX so that we
can later identify which mempools are packet pools
and which are used for Inline IPsec enabled ethdev.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add support to set/get per-aura buf type with refs and
get sum of all aura limits matching given buf type mask
and val.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Reserve AURA id 0 on cn10k and provide mechanism to specifically
allocate it and free it via roc_npa_* API's.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Similar to other RQ's, delay inline device RQ until dev is started
to avoid traffic reception when device is stopped.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Limit meta AURA workaround to CN10K A0.
Also other NIX and Inline related Erratas applicable for CN10K A1.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Updates CPT inbound inline IPsec configuration mailbox
to provide opcode and CPT credit from VF.
This patch also adds mailbox for reading inbound IPsec
configuration.
Signed-off-by: Srujana Challa <schalla@marvell.com>
Updating the logic for getting part and pass value for cn10k family,
as device tree compatible logic does not work in VMs.
Scanning all the PCI device and detect first RVU device, subsystem
device file gives part no and revision file provide pass information.
Fixes: 014a9e222bac ("common/cnxk: add model init and IO handling API")
Cc: stable@dpdk.org
Signed-off-by: Harman Kalra <hkalra@marvell.com>
Add FC check in vector event Tx path, the check needs to be
performed after head wait right before LMTST is issued.
Since, SQB pool FC updates are delayed w.r.t the actual
utilization of pool add sufficient slack to avoid overflow.
Added a new device argument to override the default SQB slack
configured, can be used as follows:
-a 0002:02:00.0,sqb_slack=32
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Add support to enable PTP per ethernet device when that
specific ethernet device is connected to event device via
Rx adapter.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Correct the partnumber value for CN103xx.
Fixes: dd462f68f04a ("common/cnxk: support CN103XX platform")
Cc: stable@dpdk.org
Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
Changed log level from info to debug for a log message
printed during MCAM allocation.
Fixes: 1f66919817ee ("common/cnxk: improve MCAM entries management")
Cc: stable@dpdk.org
Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Reviewed-by: Kiran Kumar K <kirankumark@marvell.com>
Make rte_driver opaque for non internal users.
This will make extending this object possible without breaking the ABI.
Introduce a new driver header and move rte_driver definition.
Update drivers and library to use the internal header.
Some applications may have been dereferencing rte_driver objects, mark
this object's accessors as stable.
Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Jay Jayatheerthan <jay.jayatheerthan@intel.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Acked-by: Abhinandan Gujjar <abhinandan.gujjar@intel.com>
Make rte_bus opaque for non internal users.
This will make extending this object possible without breaking the ABI.
Introduce a new driver header and move rte_bus definition and helpers.
Update drivers and library to use the internal header.
Some applications may have been dereferencing rte_bus objects, mark
this object's accessors as stable.
Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
The pci bus interface is for drivers only.
Mark as internal and move the header in the driver headers list.
While at it, cleanup the code:
- fix indentation,
- remove unneeded reference to bus specific singleton object,
- remove unneeded list head structure type,
- reorder the definitions and macro manipulating the bus singleton object,
- remove inclusion of rte_bus.h and fix the code that relied on implicit
inclusion,
Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Acked-by: Rosen Xu <rosen.xu@intel.com>
The auxiliary bus interface is for drivers only.
Mark as internal and move the header in the driver headers list.
While at it, cleanup the code:
- fix indentation,
- remove unneeded reference to bus specific singleton object,
- remove unneeded list head structure type,
- reorder the definitions and macro manipulating the bus singleton object,
- remove inclusion of rte_bus.h and fix the code that relied on implicit
inclusion,
Signed-off-by: David Marchand <david.marchand@redhat.com>
Those macros have no real value and are easily replaced with a simple
if() block.
Existing users have been converted using a new cocci script.
Deprecate them.
Signed-off-by: David Marchand <david.marchand@redhat.com>
Do not include <ctype.h>, <errno.h>, and <stdlib.h> from <rte_common.h>,
because they are not used by this file.
Include the needed headers directly from the files that need them.
Signed-off-by: Dmitry Kozlyuk <dmitry.kozliuk@gmail.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Start a new release cycle with empty release notes.
The ABI version becomes 23.0.
The map files are updated to the new ABI major number (23).
The ABI exceptions are dropped and CI ABI checks are disabled because
compatibility is not preserved.
Special handling of removed drivers is also dropped in check-abi.sh and
a note has been added in libabigail.abignore as a reminder.
Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
The number of memory regions (MR) that MLX5 PMD can use
was limited by 512 per IB device, the size of the global MR cache
that was fixed at compile time.
The cache allows to search MR LKey by address efficiently,
therefore it is the last place searched on data path
(skipped is the global MR database which would be slow).
If the application logic caused the PMD to create more than 512 MRs,
which can be the case with external memory,
those MRs would never be found on data path
and later cause a HW failure.
The cache size was fixed because at the time of overflow
the EAL memory hotplug lock may be held,
prohibiting to allocate a larger cache
(it must reside in DPDK memory for multi-process support).
This patch adds logic to release the necessary locks,
extend the cache, and repeat the attempt to insert new entries.
`mlx5_mr_btree` structure had `overflow` field
that was set when a cache (not only the global one)
could not accept new entries.
However, it was only checked for the global cache,
because caches of upper layers were dynamically expandable.
With the global cache size limitation removed, this field is not needed.
Cache size was previously limited by 16-bit indices.
Use the space in the structure previously field by `overflow` field
to extend indices to 32 bits.
With this patch, it is the HW and RAM that limit the number of MRs.
Fixes: 974f1e7ef146 ("net/mlx5: add new memory region support")
Cc: stable@dpdk.org
Signed-off-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
