caam_jr need support from kernel caam driver for
job ring initialisation. So to access register space
for job ring and allow re configure and map to userspace
UIO interface is used. This also allows to handle the
caam interrupts from the user space.
This patch adds UIO specific operations
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
This patch add routines for configuring the hw
to support various features.
These routines will be used by the PMD ops.
The patch also defines structure and macros used
to access hw capabilities.
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
caam_jr hardware can be tuned for multiple settings
like ring depth, coalescing, notification types, cache
size etc.
These parameter can be used for performance tuning
for various platforms.
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
The caam_jr poll mode crypto driver is supported for
NXP SEC 4.x+ (CAAM) hardware accelerator.
This driver is by default supported on LE platforms,
if it is used on BE platforms like LS104X,
config option CONFIG_RTE_LIBRTE_PMD_CAAM_JR_BE can be
enabled.
This patch add skeleton for caam jobring driver
with probe and uintialisation functions
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
This patch updates the current AESNI-MB PMD with added AES-GCM
algorithm support. The patch includes the necessary changes
to the code including the capability update, control and data
patch changes for the AES-GCM algorithm support.
Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com>
Acked-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
This patch add AES-CMAC support. CMAC is a keyed hash function
that is based on a symmetric key block cipher. It is One-Key
CBC MAC improvement over XCBC-MAC. RFC 4493. NIST SP 800-38B.
Signed-off-by: Tomasz Cel <tomaszx.cel@intel.com>
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
Queues attached to event crypto device can be
parallel, atomic and ordered.
This patch add support for atomic queues processing
for dpaa2_sec queues.
Signed-off-by: Ashish Jain <ashish.jain@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
dpaa2_sec hw queues can be attached to a hw dpaa2 event
device and the application can configure the event
crypto adapter to access the dpaa2_sec packets using
hardware events.
This patch defines APIs which can be used by the dpaa2
event device to attach/detach dpaa2_sec queues.
Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
Signed-off-by: Ashish Jain <ashish.jain@nxp.com>
Adding initialization of global resources. This will be saved as
metadata in cptvf and would be used by common code. Exit path for
failure case is also added along with the new routines.
Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
Adding hardware init routine for OCTEON TX crypto device. A place holder
is added for misc polling routine. That will be added in the further
patches.
Signed-off-by: Ankur Dwivedi <ankur.dwivedi@caviumnetworks.com>
Signed-off-by: Anoob Joseph <anoob.joseph@caviumnetworks.com>
Signed-off-by: Murthy NSSR <nidadavolu.murthy@caviumnetworks.com>
Signed-off-by: Nithin Dabilpuram <nithin.dabilpuram@caviumnetworks.com>
Signed-off-by: Ragothaman Jayaraman <rjayaraman@caviumnetworks.com>
Signed-off-by: Srisivasubramanian S <ssrinivasan@caviumnetworks.com>
Signed-off-by: Tejasree Kondoj <kondoj.tejasree@caviumnetworks.com>
Use common initialization to reduce boilerplate code.
Signed-off-by: Dmitri Epshtein <dima@marvell.com>
Signed-off-by: Tomasz Duszynski <tdu@semihalf.com>
Reviewed-by: Natalie Samsonov <nsamsono@marvell.com>
The patch adds support for chained source mbufs given
to crypto operations. The crypto engine accepts source buffer
containing a number of segments. The destination buffer
stays the same - always one segment.
On decryption, EIP engine will look for digest at 'auth_icv_offset'
offset in SRC buffer.It must be placed in the last segment and the
offset must be set to reach digest in the last segment.
If application doesn't placed digest in source mbuf, driver try to
copy it to a last segment.
Signed-off-by: Zyta Szpak <zr@semihalf.com>
Signed-off-by: Natalie Samsonov <nsamsono@marvell.com>
Reviewed-by: Dmitri Epshtein <dima@marvell.com>
3DES in ECB mode is supported by the PMD thus specific
entry should exist in the crypto PMD capabilities list.
Signed-off-by: Tomasz Duszynski <tdu@semihalf.com>
Reviewed-by: Natalie Samsonov <nsamsono@marvell.com>
Add support for both cipher and auth NULL algorithms.
Signed-off-by: Tomasz Duszynski <tdu@semihalf.com>
Reviewed-by: Natalie Samsonov <nsamsono@marvell.com>
Add support for the HMAC SHA224 authentication algorithm.
Signed-off-by: Tomasz Duszynski <tdu@semihalf.com>
Reviewed-by: Natalie Samsonov <nsamsono@marvell.com>
Add missing rte_kvargs library dependency. Without that
shared library build fails due to unresolved rte_kvargs_* symbols.
Fixes: 25b05a1c80 ("crypto/mvsam: parse max number of sessions")
Cc: stable@dpdk.org
Signed-off-by: Tomasz Duszynski <tdu@semihalf.com>
Add following features to the device's features list
and update documentation accordingly:
* OOP SGL in LB out
* OOP LB in LB out
Signed-off-by: Tomasz Duszynski <tdu@semihalf.com>
This patch add the support for new Management Complex
Firmware version to 10.1x.x. One of the main changes in
the APIs ordered queue.
The fslmc bus lib ABI will need to be bumped to reflect
the MC FW API and structure changes.
This will also result in bumping of ABI verion of all dependent
libs as they internally use the MC FW APIs and structures.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
With this patch, fslmc bus and ethernet devices on this bus
would start using the physical-virtual library interfaces.
This patch impacts mempool/dpaa2, event/dpaa2, net/dpaa2,
raw/dpaa2_cmdif and raw/dpaa2_qdma as they are dependent
on the bus/fslmc and thus impact linkage of libraries.
Signed-off-by: Shreyansh Jain <shreyansh.jain@nxp.com>
With this patch, dpaa bus and ethernet devices on this bus
would start using the physical-virtual library interfaces.
This patch impacts mempool/dpaa, event/dpaa and net/dpaa as
they are dependent on the bus/dpaa and thus impact linkage of
libraries.
Signed-off-by: Shreyansh Jain <shreyansh.jain@nxp.com>
Code for session create is restructured to make scalable to
support different algorithms.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
OOP support for look aside protocol support is added.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
With this patch sequence number will be rolled over and
SEC block will ignore the sequence number overflow error.
Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
With this patch sequence number will be rolled over and
SEC block will ignore the sequence number overflow error.
Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
In dpaa_sec, there are unlimited queues, but in order
to match the DPDK handling of queue pairs, rx side queues
are still unlimited, but the application will see only limited
qp (tx queues) from dpaa_sec hw.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
