This patch adds to MLX5 PMD the support of matching on IPv4 TTL and
IPv6 hoplimit.
Support is valid when using DV flow engine (Verbs flow engine doesn't
support matching on this field).
Signed-off-by: Eli Britstein <elibr@mellanox.com>
Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
The nic_mask struct in function mlx5_flow_validate_item_ipv6()
includes hop_limits field.
This is redundant since matching on this item is not supported using
Verbs flow engine (dv_flow_en=0).
(Separate patch will be sent to handle this issue for DV flow engine.)
Setting a rule including match on this field will fail:
testpmd> flow create 0 ingress pattern eth / ipv6 hop is 1 / end actions
drop / end
port_flow_complain(): Caught PMD error type 1 (cause unspecified):
hardware refuses to create flow: Operation not supported
This patch removes the redundant field from nic_mask, to ensure that
such flow rules will be rejected by PMD validation:
testpmd> flow create 0 ingress pattern eth / ipv6 hop is 1 / end actions
drop / end
port_flow_complain(): Caught PMD error type 13 (specific pattern item):
cause: 0x7fffffffa2c8, mask enables non supported bits: Operation not
supported
The related lines in function flow_verbs_translate_item_ipv6() are
removed as well, since they are redundant.
Fixes: 23c1d42c71 ("net/mlx5: split flow validation to dedicated function")
Fixes: 84c406e745 ("net/mlx5: add flow translate function")
Cc: stable@dpdk.org
Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
The VLAN 16 bits tci field contains both values of PCP and VID. When
extracting any one of them - it is required not to affect the other one.
Previous to this commit in routine flow_dev_get_vlan_info_from_items()
we calculated the PCP as follows:
(1) vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
(2) vlan->vlan_tci |= <3 bits value of PCP>
In line (1) we should have used the negated mask ('~' operator) such
that only the PCP bits will be nullified before ORing them with the
updated PCP value.
Fixes: 9aee7a8418 ("net/mlx5: support push flow action on VLAN header")
Cc: stable@dpdk.org
Signed-off-by: Ophir Munk <ophirmu@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
The devices of the family ConnectX may have two letters as suffix.
Such suffix is preceded with a space and the second x is lowercase:
- ConnectX-4 Lx
- ConnectX-5 Ex
- ConnectX-6 Dx
Uppercase of the device family name BlueField is also fixed.
The lists of supported devices are fixed.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
The routine sending packets with Multi-Packet Write method assigns
the wqe_last variable with transmit descriptor (WQE - work queue entry)
being built. If send queue is close to full state, the WQE has no data
yet (trying to put the first packet) and there is no enough space
in descriptor for the next packet the WQE is discarded and the stored
wqe_last value becomes invalid - points to the discarded WQE.
The mlx5_tx_burst_request_completion() routine might set the completion
request flags in the WQE pointed by wqe_last, it is safe, but the next
mlx5_tx_burst call uses the WQE as the first free one and request
completion flags might be overwritten and completion request will be
lost causing the transmit datapath malfunction.
Fixes: 8b581c690a ("net/mlx5: move Tx complete request routine")
Cc: stable@dpdk.org
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
In order to move the mbuf metadata from the WQE to the FDB steering
domain, the PMD add for each NIC TX flow a new action to copy the
metadata register REG_A to REG_C_0.
This copy action is considered as modify header action from HW
perspective.
The HW doesn't support to do modify header action after ant
encapsulation action.
The split metadata function wrongly added the copy action in the end of
the original actions list, hence, NIC egress flow with encapsulation
action failed when the PMD worked with dv_xmeta_en mode.
Move the copy action to be before and back to back with the
encapsulation action for the aforementioned case.
Fixes: 71e254bc02 ("net/mlx5: split Rx flows to provide metadata copy")
Cc: stable@dpdk.org
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
When running mlx5_dev_start in mlx5_ethdev the function calls
mlx5_dev_configure_rss_reta in order to configure the rxq's.
Before mlx5_dev_configure_rss_reta there isn't a check whether
there are rxq's and if rxq's are 0 the function fails.
For example, this command:
/build/app/test-pmd/testpmd -n 4 -w 0000:08:00.0,rx_vec_en=0
-- --burst=64 --mbcache=512 -i --nb-cores=27 --txd=2048 --rxd=2048
--vxlan-gpe-port=6081 --mp-alloc=xbuf --rxq 0 --forward-mode=txonly
would fail.
In order to fix this issue, we should call mlx5_dev_configure_rss_reta
only if we have rxq's.
Fixes: 63bd16292c ("net/mlx5: support RSS on hairpin")
Cc: stable@dpdk.org
Reported-by: Sylvain Rodon <srn@nexatech.fr>
Signed-off-by: Shiri Kuzin <shirik@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
HW supports match on one Ethertype, the Ethertype following the last
VLAN tag of the packet (see PRM).
Previous patch added specific handling for packets with VLAN tag,
after setting match on Ethertype.
This patch moves the handling of packets with VLAN tag, to be done
before and instead of setting match on Ethertype.
Previous patch also added, as part of specific handling for packets
with VLAN tag, the setting of cvlan_tag mask bit in translation of
L3 items.
In case of L3 tunnel there is no inner L2 header, so setting this
mask bit is wrong and causes match failures.
This patch adds check to make sure L2 header exists before setting
cvlan_tag mask bit for L3 items.
Fixes: 00f75a4057 ("net/mlx5: fix VLAN match for DV mode")
Cc: stable@dpdk.org
Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Tested-by: Raslan Darawsheh <rasland@mellanox.com>
Meter suffix subflow only has the port id and tag match item, if VLAN
push and set VLAN id actions exist in the suffix subflow, the user
defined VLAN items is required for the actions to set a correct VLAN
id.
Currently, the VLAN item stays in the meter prefix subflow. Without
the VLAN item, VLAN id or pcp will not be inherited.
Actions require the VLAN item as below:
RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN
RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID
Add a private VLAN item to copy the user defined VLAN item to the meter
suffix subflow, so the suffix subflow will have the chance to get the
correct original VLAN id and pcp value from the VLAN item.
Fixes: 9ea9b049a9 ("net/mlx5: split meter flow")
Cc: stable@dpdk.org
Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
As meter flows are split into three subflows each, the prefix subflow
with meter action color the packet, the meter subflow filters out the
colored packets, the suffix subflow applies all the remaining actions
to the passed packets.
Currently, all the user defined items are matched in the prefix flow.
Flow id tag match item is the only item added to the meter suffix
subflow. Some of the remaining actions to be applied in the suffix
subflow require more information in the match item, or the suffix
subflow will not be created successfully.
Actions require the L3/L4 type in the match items as below:
RTE_FLOW_ACTION_TYPE_SET_TP_SRC
RTE_FLOW_ACTION_TYPE_SET_TP_DST
RTE_FLOW_ACTION_TYPE_DEC_TTL
RTE_FLOW_ACTION_TYPE_SET_TTL
RTE_FLOW_ACTION_TYPE_RSS
RTE_FLOW_ACTION_TYPE_QUEUE
Inherit the match item flags from meter prefix subflow to make actions
in suffix subflow get sufficient information.
Fixes: 9ea9b049a9 ("net/mlx5: split meter flow")
Cc: stable@dpdk.org
Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Metadata suffix subflow inherits the RSS needed hash_fields from the
prefix subflow as the suffix subflow only has the tag match item unable
to generate the full original hash_fields for RSS action.
Unfortunately, hash_fields will only be generated if flow has RSS
action. So it means the prefix flow won't generate the hash_fields as
the RSS action has been split to the suffix flow.
Copy the layer flags from prefix subflow to suffix subflow to help the
suffix subflow to generate the correct hash_fields itself.
Fixes: 71e254bc02 ("net/mlx5: split Rx flows to provide metadata copy")
Cc: stable@dpdk.org
Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Currently, for header modify actions after tunnel decapsulation, the
header modify actions will still select the old outermost layer type.
It will cause header modify actions get the wrong layer type.
Add the tunnel decap flag to indicate the layer type to get for header
modify actions.
Fixes: 4bb14c83df ("net/mlx5: support modify header using Direct Verbs")
Cc: stable@dpdk.org
Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Currently, the flow validate function only validate the outermost layer
with the header modify actions. If there is decapsulation action before
the header modify action, the validation should choose the inner layer
for validation.
Add decapsulation check when validate with the header modify actions.
Choose the inner layer once there is decapsulation action.
Fixes: 4bb14c83df ("net/mlx5: support modify header using Direct Verbs")
Cc: stable@dpdk.org
Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Currently, the set VLAN ID header modify action has already got the
action pointer with offset from the header modify action array, but
the configuration saves the detail to the memory of action with the
offset again. It causes double offset to set the VLAN ID action to
the wrong place in the header modify array.
Remove the offset when get the action pointer to fix that issue.
Fixes: 5f163d520c ("net/mlx5: support modify VLAN ID on existing VLAN header")
Cc: stable@dpdk.org
Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
The RSS expansion feature was introduced to split RSS flows according to
the adjustment between the RSS types and the flow items.
The expansion function gets an item tree for the above adjustment from
the caller which reflects the HW needs.
The standard vxlan header next protocol is always Ethernet while there
are some Mellanox customers who use their own method to allow L3
headers after the vxlan tunnel header.
The expansion tree of mlx5 PMD didn't expect to get L3 headers after the
vxlan header what caused a failure in flow creation when inner RSS is
requested on L3 after vxlan flow.
Add IPV4 and IPV6 as optional headers after vxlan in the RSS expansion
tree to allow L3 tunnel support for vxlan.
Fixes: f4f06e3615 ("net/mlx5: add flow VXLAN item")
Cc: stable@dpdk.org
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
The hairpin TX/RX queue depth and packet size is fixed in the past.
When the firmware has some fix or improvement, the PMD will not
make full use of it. And also, 32 packets for a single queue will not
guarantee a good performance for hairpin flows. It will make the
stride size larger and for small packets, it is a waste of memory.
The recommended stride size is 64B now.
The parameter of hairpin queue setup needs to be adjusted.
1. A proper buffer size should support the standard jumbo frame with
9KB, and also more than 1 jumbo frame packet for performance.
2. Number of packets of a single queue should be the maximum
supported value (total buffer size / stride size).
There is no need to support the max capacity of total buffer size
because the memory consumption should also be taken into
consideration.
Fixes: e79c9be915 ("net/mlx5: support Rx hairpin queues")
Cc: stable@dpdk.org
Signed-off-by: Bing Zhao <bingz@mellanox.com>
Acked-by: Ori Kam <orika@mellanox.com>
The new Mellanox devices support GENEVE tunnel stateless offloads by
native HW parsers, FW doesn't need to configure flex parser to support
it.
The FW capability for GENEVE flex parser is not set for the above
devices, hence the GENEVE flow validation failed for them.
Remove the flex parser validation for GENEVE, stay only with the direct
FW capability for GENEVE support.
Fixes: e59a5dbcfd ("net/mlx5: add flow match on GENEVE item")
Cc: stable@dpdk.org
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
The RTE_FLOW_ITEM_TYPE_GRE_KEY means that GRE key should
be present on the flow and in addition can explicitly match on the GRE
key field itself.
When no value is set in this item any GRE key should match the flow.
The match on GRE key wrongly was not added if the item fields are NULL
while at least the GRE key should be present in the flow.
Add the GRE key present match when RTE_FLOW_ITEM_TYPE_GRE_KEY is in
the flow item list.
Fixes: a7a0365565 ("net/mlx5: match GRE key and present bits")
Cc: stable@dpdk.org
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Ori Kam <orika@mellanox.com>
ICMPv6 header contains the checksum field, that includes the IP
addresses from IP header.
The ConnectX-5 hardware does not support ICMPv6 checksum calculation
and in case of IP header modification the checksum will contain
the wrong value.
The patch rejects the header modification actions related to IP
addresses if ICMPv6 protocol is detected in pattern.
This issue was also partly fixed in commit below which rejects
flows with the pattern "ipv6 proto is 58".
Fixes: 0e2ceb639d ("net/mlx5: fix ICMPv6 header rewrite actions")
Cc: stable@dpdk.org
Signed-off-by: Shiri Kuzin <shirik@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
The hardware can recognize and mark the layer 4 protocol type for TCP,
UDP and IPSec non-fragmented packets. For all the fragmented packets,
L4 type will be considered as None. This can be used when creating a
flow with L4 matching, then hops number will be reduced and a better
performance could be gained.
But for ICMP packets, it cannot be recognized correctly because it is
not a L4 protocol in the stack, even if the packet format is similar.
All the fragmented and non-fragmented ICMP will have the None L4 type.
Fragmented packets with incomplete headers could not hit the flow,
even for the first fragment. Because then it will make it complex to
defragment for both HW and SW. For other types, the implicit rules
could be used directly and all the fragments will miss the flow.
For ICMP packets, this should be done explicitly because all packets
have None type. The first fragment will still hit the flow if there is
no explicit rule.
All ICMP fragments will still hit the rules like ETH, ETH + IP, and
ETH + IP + "ICMP protocol" only since they are wildcard rules, and
there is no next layer protocol specified field in such rules.
Fixes: d53aa89aea ("net/mlx5: support matching on ICMP/ICMP6")
Cc: stable@dpdk.org
Signed-off-by: Bing Zhao <bingz@mellanox.com>
Acked-by: Ori Kam <orika@mellanox.com>
This adds new device id to the list of Mellanox devices
that runs mlx5 PMD.
- BlueField-2 integrated ConnectX-6 Dx network controller
This device is not ready yet, it is in development stage.
Signed-off-by: Raslan Darawsheh <rasland@mellanox.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Acked-by: Matan Azrad <matan@mellanox.com>
The PMD manages internally the priority of the flows in addition to the
user configured priority.
So, 2 flows with the same user priority may get different priority.
The method:
As much as the flow is more specific it gets higher priority
(higher means first to be matched).
In addition, When the user creates a RSS flow the PMD splits the flows
according to the flow RSS layers as the HW requests for RSS TIR.
The internal priority for each flow is decided by the flow last layer.
L2, L3 and L4 (L2 low and L4 high).
The tunnel layer was wrongly decided to be L4 all the time, even when
the flow is configured with inner-RSS.
Hence, the first RSS split which takes the tunnel layer priority all the
time will be matched before the more specific splits.
Change the priority of tunnel layer to be L2 when inner-RSS is
configured.
Fixes: d4a405186b ("net/mlx5: support tunnel RSS level")
Cc: stable@dpdk.org
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Ori Kam <orika@mellanox.com>
The meter flows are split into three subflows each, the prefix subflow
with meter action color the packet, the meter subflow filters out the
colored packets, the suffix subflow applies all the remaining actions
to the passed packets. The tag header modify action is added to the
prefix subflow to make the suffix subflow to match the packets from the
prefix subflow.
Currently, the tag header modify action is added at the beginning in the
prefix subflow even before decap action. The header modify action does
not make sense to the later decap action, so the flow create will be
validated as incorrect flow rule and failed.
Move the tag header modify action just before meter action in the prefix
subflow to make the flow with decap action to do the decap first, then
do the tag and meter to fix that issue.
Fixes: 9ea9b049a9 ("net/mlx5: split meter flow")
Cc: stable@dpdk.org
Reported-by: Tonghao Zhang <xiangxia.m.yue@gmail.com>
Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Currently MLX5 PMD can't match on untagged packets specifically.
Tagged traffic still hits the flows intended for untagged packets.
If the flow has ETH, it will catch all matching packets, tagged
and untagged.
The solution is to use cvlan_tag bit.
If mask=1 and value=0 it matches on untagged traffic.
If mask=1 and value=1 it matches on tagged traffic.
This is the kernel implementation.
This patch updated MLX5 PMD to set cvlan_tag mask and value according
to flow rule contents.
This update is relevant when using DV flow engine (dv_flow_en=1).
See example at https://doc.dpdk.org/guides/nics/mlx5.html#limitations.
Fixes: fc2c498ccb ("net/mlx5: add Direct Verbs translate items")
Cc: stable@dpdk.org
Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
The blocker should take FDB into consideration, since FDB all directions
have transfer ingress in it.
Fixes: 55060e62e4 ("net/mlx5: block push VLAN action on Rx")
Cc: stable@dpdk.org
Signed-off-by: Wisam Jaddo <wisamm@mellanox.com>
Acked-by: Raslan Darawsheh <rasland@mellanox.com>
Replace checking against 65535 limit,
with a simpler form using RTE_MIN and UINT16_MAX macros.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Matan Azrad <matan@mellanox.com>
To provide the better PCIe bandwidth utilization the ConnectX-4LX
NIC supports the multi-packet write (MPW) sessions allowing to
pack multiple packets into one descriptor (WQE). This is legacy
feature and it has some limitations on the packets and data
description segments. To provide the best performance all inline
packets must be put into shared data segment and the total length
of MPW session must be limited. The limit is controlled with
txq_inline_mpw devarg.
Fixes: 82e75f8323 ("net/mlx5: fix legacy multi-packet Tx descriptors")
Cc: stable@dpdk.org
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
The encapsulation and decapsulation actions are divided into 2 types:
L2 and L3.
In order to configure L3 xcapsulation actions the user should use both
RAW_DECAP and RAW_ENCAP and setting the appropriated data sizes in
their action configuration structures.
The PMD flow validation wrongly didn't detect the RAW_DECAP
and RAW_ENCAP combination to distinguish between L3_DECAP and L3_ENCAP.
Thus, some xcapsulation related validation failed.
For example, when configuring modify header action before L3_DECAP.
Simplify the xcapsulation defines and fix the L3 xcapsulation detection
using the action configuration data sizes.
By the way, add the hairpin validation in this area.
Fixes: d85c7b5ea5 ("net/mlx5: split hairpin flows")
Fixes: 8ba9eee4ce ("net/mlx5: add raw data encap/decap to Direct Verbs")
Cc: stable@dpdk.org
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Ori Kam <orika@mellanox.com>
The header file rte_config.h is always included by make or meson.
If required in an exported API header file, it must be included
in the public header file for external applications.
In the internal files, explicit include of rte_config.h is useless,
and can be removed.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Matan Azrad <matan@mellanox.com>
Acked-by: David Marchand <david.marchand@redhat.com>
Acked-by: Neil Horman <nhorman@tuxdriver.com>
Previous patch changed the format of struct
mlx5_flow_dv_modify_hdr_resource, to use a flexible array for
modification actions.
In __flow_dv_translate() a union was defined with item of this struct,
and an array of maximal possible size.
Array elements are filled in several functions.
In function flow_dv_convert_action_set_reg(), array element is filled
partially, while the other fields of this array element are left
uninitialized.
This may cause failure of flow_dv_modify_hdr_resource_register()
when calling driver function with the 'dirty' array.
This patch updates flow_dv_convert_action_set_reg(), setting the
selected array element fields while clearing the other fields.
Other functions that fill the same array elements are also updated
for clarity and proofing future use.
Fixes: 024e95759c ("net/mlx5: fix modify actions support limitation")
Cc: stable@dpdk.org
Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
The mpx5 PMD maintains the list of devices for those the memory
operation callback routines must be invoked to keep the device MRs (MR
is the entity backing the hardware DMA transactions) consistent with the
mapped memory.
Each device context in the list is protected with dedicated lock on per
device basis, which might be taken inside the callback routine.
When device is closing the PMD frees all MRs by calling
mlx5_mr_release(), that might call rte_free() under the taken device
lock. If this rte_free call triggers the entire memory segment freeing
it, in its turn, invokes the callback routine and attempt to take the
lock inside this one causes the deadlock.
The patch proposes the remove the device from the callback list first
and then call mlx5_mr_release() and free the remaining device MRs
explicitly.
Fixes: 0e3d0525b2 ("net/mlx5: fix memory event callback list")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Get a burst mode information for Rx/Tx queues in mlx5.
Provide callback functions to show this information in
a "show rxq info" and "show txq info" output.
Signed-off-by: Alexander Kozyrev <akozyrev@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Currently, when using VXLAN-GPE or VXLAN item in the flow
both are being treated the same with flags 0x8 in VXLAN
header. Which mean the matching of the item VXLAN-GPE
will match any VXLAN packet.
This fixes the translation of VXLAN GPE item into PMD flow
item. Which will by default set the flags to VXLAN-GPE
to be 0xc.
Fixes: 3d69434113 ("net/mlx5: add Direct Verbs validation function")
Cc: stable@dpdk.org
Signed-off-by: Raslan Darawsheh <rasland@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Use the MLX5_ASSERT macros instead of the standard assert clause.
Depends on the RTE_LIBRTE_MLX5_DEBUG configuration option to define it.
If RTE_LIBRTE_MLX5_DEBUG is enabled MLX5_ASSERT is equal to RTE_VERIFY
to bypass the global CONFIG_RTE_ENABLE_ASSERT option.
If RTE_LIBRTE_MLX5_DEBUG is disabled, the global CONFIG_RTE_ENABLE_ASSERT
can still make this assert active by calling RTE_VERIFY inside RTE_ASSERT.
Signed-off-by: Alexander Kozyrev <akozyrev@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Use the RTE_LIBRTE_MLX5_DEBUG configuration flag to get rid of dependency
on the NDEBUG definition. This is a preparation step to switch
from standard assert clauses to DPDK RTE_ASSERT ones in MLX5 driver.
Signed-off-by: Alexander Kozyrev <akozyrev@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
This patch adds support for dynamic flag that hints transmit
datapath do not copy data to the descriptors. This flag is
useful when data are located in the memory of another (not NIC)
physical device and copying to the host memory is undesirable.
This hint flag is per mbuf for multi-segment packets.
This hint flag might be partially ignored if:
- hardware requires minimal data header to be inline into
descriptor, it depends on the hardware type and its configuration.
In this case PMD copies the minimal required number of bytes to
the descriptor, ignoring the no inline hint flag, the rest of data
is not copied.
- VLAN tag insertion offload is requested and hardware does not
support this options. In this case the VLAN tag is inserted by
software means and at least 18B are copied to descriptor.
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
The inline feature is designed to save PCI bandwidth by copying some
of the data to the wqe. This feature if enabled works for all packets.
In some cases when using external memory, the PCI bandwidth is not
relevant since the memory can be accessed by other means.
This commit introduce the ability to control the inline with mbuf
granularity.
In order to use this feature the application should register the field
name, and restart the port.
Signed-off-by: Ori Kam <orika@mellanox.com>
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
There are RDMA-CORE versions which are not supported multi-table for
some Mellanox mlx5 devices.
Hence, the optimization added in commit [1] which forwards all the FDB
traffic to table 1 cannot be configured.
Make the above optimization optional:
Do not fail when either table 1 cannot be created or the jump rule
(all =>jump to table 1) is not configured successfully.
In this case, all the flows will be configured to table 0.
[1] commit b67b4ecbde ("net/mlx5: skip table zero to improve
insertion rate")
Cc: stable@dpdk.org
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Move Netlink mechanism and its dependencies from net/mlx5 to
common/mlx5 in order to be ready to use by other mlx5 drivers.
The dependencies are BITFIELD defines, the ppc64 compilation workaround
for bool type and the function mlx5_translate_port_name.
Update build mechanism accordingly.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
As an arrangment for Netlink command moving to the common library,
reduce the net/mlx5 dependencies.
Replace ethdev class command parameters.
Improve Netlink sequence number mechanism to be controlled by the
mlx5 Netlink mechanism.
Move mlx5_nl_check_switch_info to mlx5_nl.c since it is the only one
which uses it.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
The Netlink commands interfaces is included in the mlx5.h file with a
lot of other PMD interfaces.
As an arrangement to make the Netlink commands shared with different
PMDs, this patch moves the Netlink interface to a new file called
mlx5_nl.h.
Move non Netlink pure vlan commands from mlx5_nl.c to the
mlx5_vlan.c.
Rename Netlink commands and structures to use prefix mlx5_nl.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
There might be a case that one Mellanox device can be probed by
multiple mlx5 drivers.
One case is that any mlx5 vDPA device can be probed by both net/mlx5
and vdpa/mlx5.
Add a new mlx5 common API to get the requested driver by devargs:
class=[net/vdpa].
Skip net/mlx5 PMD probing while the device is selected to be probed by
the vDPA driver.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Add option to create an indirect mkey by the current
mlx5_devx_cmd_mkey_create command.
Indirect mkey points to set of direct mkeys.
By this way, the HW\SW can reference fragmented memory by one object.
Align the net/mlx5 driver usage in the above command.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
The CQE has owner bit to indicate if it is in SW control or HW.
Share a CQE check for all the mlx5 drivers.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Move the vendor information, vendor ID and device IDs from net/mlx5 PMD
to the common mlx5 file.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Move PCI detection by IB device from mlx5 PMD to the common code.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
A new Mellanox vdpa PMD will be added to support vdpa operations by
Mellanox adapters.
This vdpa PMD design includes mlx5_glue and mlx5_devx operations and
large parts of them are shared with the net/mlx5 PMD.
Create a new common library in drivers/common for mlx5 PMDs.
Move mlx5_glue, mlx5_devx_cmds and their dependencies to the new mlx5
common library in drivers/common.
The files mlx5_devx_cmds.c, mlx5_devx_cmds.h, mlx5_glue.c,
mlx5_glue.h and mlx5_prm.h are moved as is from drivers/net/mlx5 to
drivers/common/mlx5.
Share the log mechanism macros.
Separate also the log mechanism to allow different log level control to
the common library.
Build files and version files are adjusted accordingly.
Include lines are adjusted accordingly.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
The DevX commands interface is included in the mlx5.h file with a lot
of other PMD interfaces.
As an arrangement to make the DevX commands shared with different PMDs,
this patch moves the DevX interface to a new file called mlx5_devx_cmds.h.
Also remove shared device structure dependency on DevX commands.
Replace the DevX commands log mechanism from the mlx5 driver log
mechanism to the EAL log mechanism.
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Flow with meter will split to three subflows, the prefix subflow with
meter action do the color, the meter subflow filter the packets, the
suffix subflow do all the left actions for packets pass the filter.
Both the color and the subflow match between prefix and suffix use the
register to store the tag.
For some of the NICs with meter color register share capability, it
only uses 8 LSB of the register for color, the left 24 MSB can be used
for flow id match between meter prefix subflow and suffix subflow.
Currently, one entire register is allocated for flow matching which
causes the NICs with limited registers don't have enough register for
other matching.
Add the meter color share capability checking to fix lacking of
registers issue.
Fixes: 9ea9b049a9 ("net/mlx5: split meter flow")
Cc: stable@dpdk.org
Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
