The devtools that check Python code are Black and Isort to format the
code and Pylama to do static analysis.
Signed-off-by: Owen Hilyard <ohilyard@iol.unh.edu>
Signed-off-by: Juraj Linkeš <juraj.linkes@pantheon.tech>
Harish is the new maintainer of Rx/Tx adapters due to role change of Jay.
Signed-off-by: Jay Jayatheerthan <jay.jayatheerthan@intel.com>
Acked-by: Naga Harish K S V <s.v.naga.harish.k@intel.com>
Support device init and add the following dev ops:
- dev_configure
- dev_close
- dev_infos_get
Signed-off-by: Beilei Xing <beilei.xing@intel.com>
Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Introduce a new crypto PMD for hardware accelerators based on UADK [1].
UADK is a framework for user applications to access hardware accelerators.
UADK relies on IOMMU SVA (Shared Virtual Address) feature, which share
the same page table between IOMMU and MMU.
Thereby user application can directly use virtual address for device dma,
which enhances the performance as well as easy usability.
This patch adds the basic framework.
[1] https://github.com/Linaro/uadk
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Introduced stubs for device driver for the ACC200
integrated VRAN accelerator on SPR-EEC
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Used a common directory for the ACC PMDs
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
These are my last couple of days at Microsoft.
Remove the old email from MAINTAINERS.
Will no longer have free access to Azure to work on Netvsc.
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
This library has no maintainer and, for now, nobody expressed interest
in taking over.
Mark this experimental library as deprecated and announce plan for
removal in v23.11.
Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Ferruh Yigit <ferruh.yigit@amd.com>
Acked-by: Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
Bernard is no longer with Intel and is no longer involved in the DPDK
community, so remove him from the MAINTAINERS file.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: John McNamara <john.mcnamara@intel.com>
Driver is disabled by default because its dependencies are not
upstreamed yet, code is available for development and investigation.
When all dependencies are upstreamed, driver can be enabled back.
Fixes: 517ed6e2d5 ("net/mana: add basic driver with build environment")
Signed-off-by: Ferruh Yigit <ferruh.yigit@amd.com>
Acked-by: Long Li <longli@microsoft.com>
Acked-by: Thomas Monjalon <thomas@monjalon.net>
Support device init and add following devops skeleton:
- dev_configure
- dev_start
- dev_stop
- dev_close
Note that build system (including doc) is also added in this patch.
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Developer tools associated with ABI are maintained with as part of
developer tooling, EAL ABI headers are maintained with EAL,
ABI build scripts are maintained with the build system
and ABI policy and version documents along with rest of the documentation.
Major change is that individual components maintainers become
responsible for ensuring correctness of their map file(s).
Signed-off-by: Ray Kinsella <mdr@ashroe.eu>
MANA is a PCI device. It uses IB verbs to access hardware through the
kernel RDMA layer. This patch introduces build environment and basic
device probe functions.
Signed-off-by: Long Li <longli@microsoft.com>
Add all necessary elements for DPDK to compile and run EAL on
LoongArch64 Soc.
This includes:
- EAL library implementation for LoongArch ISA.
- meson build structure for 'loongarch' architecture.
RTE_ARCH_LOONGARCH define is added for architecture identification.
- xmm_t structure operation stubs as there is no vector support in
the current version for LoongArch.
Compilation was tested on Debian and CentOS using loongarch64
cross-compile toolchain from x86 build hosts. Functions were tested
on Loongnix and Kylin which are two Linux distributions supported
LoongArch host based on Linux 4.19 maintained by Loongson
Corporation.
We also tested DPDK on LoongArch with some external applications,
including: Pktgen-DPDK, OVS, VPP.
The platform is currently marked as linux-only because there is no
other OS than Linux support LoongArch host currently.
The i40e PMD driver is disabled on LoongArch because of the absence
of vector support in the current version.
Similar to RISC-V, the compilation of following modules has been
disabled by this commit and will be re-enabled in later commits as
fixes are introduced:
net/ixgbe, net/memif, net/tap, example/l3fwd.
Signed-off-by: Min Zhou <zhoumin@loongson.cn>
As part of the agreed process for deprecating KNI in DPDK, the example
app is scheduled for removal as part of the 22.11 release.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Stephen Hemminger <stephen@networkplumber.org>
NVIDIA acquired Mellanox Technologies in 2020.
The DPDK documentation and code might still include instances
of or references to Mellanox trademarks (like BlueField and ConnectX)
that are now NVIDIA trademarks.
The PCI IDs and copyrights are unchanged.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Gal Cohen <galco@nvidia.com>
The ioat driver has been superseded by the ioat and idxd dmadev drivers,
and has been deprecated for some time, so remove it.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Going over list of active DPDK developers and MAINTAINERS
and noticed that Jan's email was not active.
His response was:
"
The viktorin@rehivetech.com is no longer under my control.
As there is already another maintainer (Ruifeng Wang),
I would prefer and suggest to remove my address
from the maintainers entirely.
"
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
This patch renames octeon end point driver from octeontx_ep to
octeon_ep to enable single unified driver to support current
OcteonTx and future Octeon PCI endpoint NICs to reflect common
driver for all Octeon based PCI endpoint NICs.
Signed-off-by: Sathesh Edara <sedara@marvell.com>
Acked-by: Veerasenareddy Burru <vburru@marvell.com>
Add performance test for the rte_raw_cksum() function, which delegates
the actual work to __rte_raw_cksum(), which in turn is used by other
functions in need of Internet checksum calculation.
Signed-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
Acked-by: Olivier Matz <olivier.matz@6wind.com>
Remove Nalla Pradeep as co-maintainer of octeontx_ep driver.
Add Sathesh Edara as co-maintainer of octeontx_ep driver.
Signed-off-by: Veerasenareddy Burru <vburru@marvell.com>
This will make the packet grouping function common, so
that other examples can utilize as per need.
For each architecture sse/neon/altivec, port group
headers will be created under examples/common/<arch>.
Signed-off-by: Rahul Bhansali <rbhansali@marvell.com>
Tested-by: Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>
Acked-by: Konstantin Ananyev <konstantin.v.ananyev@yandex.ru>
Lijun Ou and Min Hu currently do not work for the hns3 PMD.
I will do the work, so update the hns3 maintainers.
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
Acked-by: Yisen Zhuang <yisen.zhuang@huawei.com>
Added support for ACC101 as a derivative of ACC100.
Integrated in unified driver and reusing existing code when possible.
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
MCS lock, PF lock and Ticket lock have no arch specific implementation,
there is no need for the extra redirection in headers.
Signed-off-by: David Marchand <david.marchand@redhat.com>
Acked-by: Stephen Hemminger <stephen@networkplumber.org>
Acked-by: Stanislaw Kardach <kda@semihalf.com>
l3fwd-acl contains duplicate functions to l3fwd.
For this reason we merge l3fwd-acl code into l3fwd
with '--lookup acl' cmdline option to run ACL.
Signed-off-by: Sean Morrissey <sean.morrissey@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Add all necessary elements for DPDK to compile and run EAL on SiFive
Freedom U740 SoC which is based on SiFive U74-MC (ISA: rv64imafdc)
core complex.
This includes:
- EAL library implementation for rv64imafdc ISA.
- meson build structure for 'riscv' architecture. RTE_ARCH_RISCV define
is added for architecture identification.
- xmm_t structure operation stubs as there is no vector support in the
U74 core.
Compilation was tested on Ubuntu and Arch Linux using riscv64 toolchain.
Clang compilation currently not supported due to issues with missing
relocation relaxation.
Two rte_rdtsc() schemes are provided: stable low-resolution using rdtime
(default) and unstable high-resolution using rdcycle. User can override
the scheme by defining RTE_RISCV_RDTSC_USE_HPM=1 during compile time of
both DPDK and the application. The reasoning for this is as follows.
The RISC-V ISA mandates that clock read by rdtime has to be of constant
period and synchronized between all hardware threads within 1 tick
(chapter 10.1 in version 20191213 of RISC-V spec).
However this clock may not be of high-enough frequency for dataplane
uses. I.e. on HiFive Unmatched (FU740) it is 1MHz.
There is a high-resolution alternative in form of rdcycle which is
clocked at the core clock frequency. The drawbacks are that it may be
disabled during sleep (WFI), its frequency might change due to DVFS and
it is core-local and therefore cannot be used as a wall-clock. It can
however be used for micro-benchmarking user applications, similarly to
Aarch64's PMCCNTR PMU counter.
The platform is currently marked as linux-only because rte_cycles
implementation uses the timebase-frequency device-tree node read through
the proc file system. Such approach was chosen because Linux kernel
depends on the presence of this device-tree node.
The i40e PMD driver is disabled on RISC-V as the rv64gc ISA has no vector
operations.
The compilation of following modules has been disabled by this commit
and will be re-enabled in later commits as fixes are introduced:
net/ixgbe, net/memif, net/tap, example/l3fwd.
Sponsored-by: Frank Zhao <frank.zhao@starfivetech.com>
Sponsored-by: Sam Grove <sam.grove@sifive.com>
Signed-off-by: Michal Mazurek <maz@semihalf.com>
Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
Update and add maintainers for NXP devices and RAW device API.
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
A sequence lock (seqlock) is a synchronization primitive which allows
for data-race free, low-overhead, high-frequency reads, suitable for
data structures shared across many cores and which are updated
relatively infrequently.
A seqlock permits multiple parallel readers. A spinlock is used to
serialize writers. In cases where there is only a single writer, or
writer-writer synchronization is done by some external means, the
"raw" sequence counter type (and accompanying rte_seqcount_*()
functions) may be used instead.
To avoid resource reclamation and other issues, the data protected by
a seqlock is best off being self-contained (i.e., no pointers [except
to constant data]).
One way to think about seqlocks is that they provide means to perform
atomic operations on data objects larger than what the native atomic
machine instructions allow for.
DPDK seqlocks (and the underlying sequence counters) are not
preemption safe on the writer side. A thread preemption affects
performance, not correctness.
A seqlock contains a sequence number, which can be thought of as the
generation of the data it protects.
A reader will
1. Load the sequence number (sn).
2. Load, in arbitrary order, the seqlock-protected data.
3. Load the sn again.
4. Check if the first and second sn are equal, and even numbered.
If they are not, discard the loaded data, and restart from 1.
The first three steps need to be ordered using suitable memory fences.
A writer will
1. Take the spinlock, to serialize writer access.
2. Load the sn.
3. Store the original sn + 1 as the new sn.
4. Perform load and stores to the seqlock-protected data.
5. Store the original sn + 2 as the new sn.
6. Release the spinlock.
Proper memory fencing is required to make sure the first sn store, the
data stores, and the second sn store appear to the reader in the
mentioned order.
The sn loads and stores must be atomic, but the data loads and stores
need not be.
The original seqlock design and implementation was done by Stephen
Hemminger. This is an independent implementation, using C11 atomics.
For more information on seqlocks, see
https://en.wikipedia.org/wiki/Seqlock
Acked-by: Morten Brørup <mb@smartsharesystems.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Reviewed-by: Ola Liljedahl <ola.liljedahl@arm.com>
Reviewed-by: Chengwen Feng <fengchengwen@huawei.com>
Signed-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
A new test suite is added in test app to test inline IPsec protocol
offload. In this patch, predefined vectors from Lookaside IPsec test
are used to verify the IPsec functionality without the need of
external traffic generators. The sent packet is loopbacked onto the same
interface which is received and matched with the expected output.
The test suite can be updated further with other functional test cases.
In this patch encap only cases are added.
The testsuite can be run using:
RTE> inline_ipsec_autotest
Signed-off-by: Akhil Goyal <gakhil@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
The DPAA2 DMA driver is an implementation of the dmadev APIs,
that provide means to initiate a DMA transaction from CPU.
Earlier this was part of RAW driver, but with DMA drivers
added as separate flavor of drivers, this driver is being
moved to DMA drivers.
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
With DMA devices supported as a separate flavor of devices,
the DPAA2 QDMA driver is moved in the DMA devices.
This change removes the DPAA2 QDMA driver from raw devices.
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Establish unit test for testing thread api. Initial unit tests
for rte_thread_{get,set}_affinity_by_id().
Signed-off-by: Narcisa Vasile <navasile@linux.microsoft.com>
Signed-off-by: Tyler Retzlaff <roretzla@linux.microsoft.com>
Junfeng and Simei have been appointed the new maintainers for the igc
PMD. Update the MAINTAINERS file to reflect this.
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Simei Su <simei.su@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Qiming and Wenjun have been appointed the new maintainers for the ixgbe
PMD. Update the MAINTAINERS file to reflect this.
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
Acked-by: Wenjun Wu <wenjun1.wu@intel.com>
Simei and Wenjun have been appointed the new maintainers for the e1000
PMD. Update the MAINTAINERS file to reflect this.
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Acked-by: Simei Su <simei.su@intel.com>
Acked-by: Wenjun Wu <wenjun1.wu@intel.com>
Make Jochen Behrens the maintainer of the net/vmxnet3 device
driver as Yong Wang is not working on vmxnet3 any more.
Signed-off-by: Jochen Behrens <jbehrens@vmware.com>
Acked-by: Yong Wang <yongwang@vmware.com>
These were implicit from DPDK script but adding
separate reference to make it explicit.
Separate sections for API and PMDs
Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Niklas has been appointed the new maintainer for the NFP PMD.
Update the MAINTAINERS file to reflect this.
Signed-off-by: Heinrich Kuhn <heinrich.kuhn@corigine.com>
