A Rx ring stop start sequence may result in the FW returning
a different set of Rx ring and AGG ring IDs. If the ring group
is not updated with the new IDs, the HW sees the host driver using
incorrect BD types for the Rx ring and AGG ring. This can cause
the chip to go into a bad state or encounter RE_flush issue
or leak mbufs in the HW.
Fix this by issuing a bnxt_hwrm_ring_grp_free() and an
bnxt_hwrm_ring_grp_alloc() to refresh the ring group information.
Fixes: 9b63c6fd70 ("net/bnxt: support Rx/Tx queue start/stop")
Cc: stable@dpdk.org
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
When an ETH or VLAN flow item directly preceding ECPRI (i. e. a pattern
for eCPRI over Ethernet) did not specify the eCPRI protocol, matches
were not restricted to eCPRI traffic. For example, "eth / ecpri / end"
pattern behaved as "eth / end". Implicitly add Ethernet type condition,
so that "eth / ecpri / end" behaves as "eth type is 0xAEFE / end".
Fixes: daa38a8924 ("net/mlx5: add flow translation of eCPRI header")
Cc: stable@dpdk.org
Signed-off-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
A core dump is being generated with the following call stack:
0 _mm256_storeu_si256 (__A=..., __P=0x80)
1 rte_mov32 (src=0x2299c9140 "", dst=0x80)
2 rte_memcpy_aligned (n=60, src=0x2299c9140, dst=0x80)
3 rte_memcpy (n=60, src=0x2299c9140, dst=0x80)
4 mprq_buf_to_pkt (strd_cnt=1, strd_idx=0, buf=0x2299c8a00, len=60,
pkt=0x18345f0c0, rxq=0x18345ef40)
5 rxq_copy_mprq_mbuf_v (rxq=0x18345ef40, pkts=0x7f76e0ff6d18, pkts_n=5)
6 rxq_burst_mprq_v (rxq=0x18345ef40, pkts=0x7f76e0ff6d18, pkts_n=46,
err=0x7f76e0ff6a28, no_cq=0x7f76e0ff6a27)
7 mlx5_rx_burst_mprq_vec (dpdk_rxq=0x18345ef40, pkts=0x7f76e0ff6a88,
pkts_n=128)
8 rte_eth_rx_burst (nb_pkts=128, rx_pkts=0x7f76e0ff6a88,
queue_id=<optimized out>, port_id=<optimized out>)
This crash is caused by an attempt to copy previously uncompressed CQEs
into non-allocated mbufs. There is a check to make sure we only use
allocated mbufs in the rxq_burst_mprq_v() function, but it is done only
before the main processing loop. Leftovers of compressed CQEs session are
handled before that loop and may lead to the mbufs overflow as seen.
Move the check for replenished mbufs up to protect uncompressed CQEs
session leftovers from accessing non-allocated mbufs after the
mlx5_rx_mprq_replenish_bulk_mbuf() function is invoked.
Bugzilla ID: 746
Fixes: 0f20acbf5e ("net/mlx5: implement vectorized MPRQ burst")
Cc: stable@dpdk.org
Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
The RSS expansion algorithm is using a graph to find the possible
expansion paths. The VLAN item in the flow pattern requires special
treatment, because it should not be added implicitly by the expansion
algorithm. If the flow pattern ends with ETH item, the pattern will be
expanded with IPv4 and IPv6.
For example:
testpmd> flow create ... eth / end actions rss / end
ETH END
ETH IPV4 END
ETH IPV6 END
If a VLAN item follows the ETH item in the flow pattern, the pattern
will be expanded with IPv4 and IPv6 following the VLAN item.
For example:
testpmd> flow create ... eth / vlan / end actions rss level 1 / end
ETH VLAN END
ETH VLAN IPV4 END
ETH VLAN IPV6 END
The case of inner tunnel VLAN item was not taken care of so the flow
pattern did not expand with IPv6 and IPv4 as expected.
Example with inner VLAN:
testpmd> flow create ... / vxlan / eth / vlan / end actions rss level 2
/ end
The current result of the expansion alg:
ETH IPV6 UDP VXLAN ETH VLAN END
The expected result of the expansion alg:
ETH IPV6 UDP VXLAN ETH VLAN END
ETH IPV6 UDP VXLAN ETH VLAN IPV4 END
ETH IPV6 UDP VXLAN ETH VLAN IPV6 END
The fix is to introduce a new flag to set on a graph expansion node
to apply the 'explicit' behavior, meaning the node is not added to
the expanded pattern, if it is not found in the flow pattern, but the
expansion alg can go deeper to its next nodes.
Fixes: c7870bfe09 ("ethdev: move RSS expansion code to mlx5 driver")
Cc: stable@dpdk.org
Signed-off-by: Lior Margalit <lmargalit@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Remove bit reverse for TCP/UDP port mask, since it causes the flows with
some TCP/UDP ports to disobey the flow director rules.
Fixes: ea230dda16 ("net/txgbe: configure flow director filter")
Cc: stable@dpdk.org
Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
When device is stopped, the port status is not changed and only the Tx
laser is turned off by hardware design.
Fixes: 0c061eadec ("net/txgbe: add link status change")
Cc: stable@dpdk.org
Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
Rename the nfp_net.c file to nfp_common as it now contains functions
common to VF and PF functionality. Rename the header file too to be
consistent. Also remove the "net" naming from the _ctrl and _logs files
for consistency across the PMD.
Signed-off-by: Heinrich Kuhn <heinrich.kuhn@netronome.com>
Signed-off-by: Simon Horman <simon.horman@corigine.com>
Similar to the last commit, this changeset moves all the PF specific
functions to a new file called nfp_ethdev.c.
Signed-off-by: Heinrich Kuhn <heinrich.kuhn@netronome.com>
Signed-off-by: Simon Horman <simon.horman@corigine.com>
Move any ethdev functionality specific to VF devices into a new file
called nfp_ethdev_vf.c.
Signed-off-by: Heinrich Kuhn <heinrich.kuhn@netronome.com>
Signed-off-by: Simon Horman <simon.horman@corigine.com>
The majority of "ethdev" type functions are used for both PF devices and
VF devices. Prototype these functions in the nfp_net_pmd header file in
preparation of splitting PF and VF specific functions.
Signed-off-by: Heinrich Kuhn <heinrich.kuhn@netronome.com>
Signed-off-by: Simon Horman <simon.horman@corigine.com>
This commit moves the CPP bridge logic to a separate file. A new
corresponding header file is also created.
Signed-off-by: Heinrich Kuhn <heinrich.kuhn@netronome.com>
Signed-off-by: Simon Horman <simon.horman@corigine.com>
Create a new rxtx file and move the Rx/Tx functions to this file. This
commit will also move the needed shared functions to the nfp_net_pmd.h
file as needed.
Signed-off-by: Heinrich Kuhn <heinrich.kuhn@netronome.com>
Signed-off-by: Simon Horman <simon.horman@corigine.com>
This change splits out the rx/tx specific structs and defines from the
main nfp_net_pmd header file and into their own header file.
Signed-off-by: Heinrich Kuhn <heinrich.kuhn@netronome.com>
Signed-off-by: Simon Horman <simon.horman@corigine.com>
This patch adds set link up/down feature. RxTx datapath and link status
will be disabled when dev_set_link_down() is called, and can be enabled by
dev_start() or dev_set_link_up().
Signed-off-by: Huisong Li <lihuisong@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
Currently, hns3 PMD has supported start/stop RxTx datapath request message
between the primary and secondary processes. However, there are some cases
only to start/stop Tx datapath. This patch adds start/stop Tx datapath
request for MP.
Signed-off-by: Huisong Li <lihuisong@huawei.com>
Signed-off-by: Min Hu (Connor) <humin29@huawei.com>
Logging should be converted to dynamic log.
Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
Reviewed-by: Heinrich Kuhn <heinrich.kuhn@netronome.com>
The memory size of bandwidth config parameters is not set correctly in
memory copy process, which leads to the wrong values. This patch fixed
the size to the correct value.
Fixes: 3a6bfc37ea ("net/ice: support QoS config VF bandwidth in DCF")
Cc: stable@dpdk.org
Signed-off-by: Ting Xu <ting.xu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
For ACL, there are three entry priorities: LOW, NORMAL, HIGH.
Low priority starts from the highest index, 25% of total entries;
Normal priority starts from the highest index, 50% of total entries;
High priority starts from the lowest index, 25% of total entries.
Each TCAM block has 512 entries of 40 bits. Currently, there is a
scenario in which multiple TCAM blocks are cascaded. It means the
total entries are 512. The default priority is NORMAL, so the max
entry is 256, not 512. This patch changes the max entry number for
NORMAL priority.
Fixes: 40d466fa9f ("net/ice: support ACL filter in DCF")
Cc: stable@dpdk.org
Signed-off-by: Simei Su <simei.su@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
For GTPoGRE protocol in AVF FDIR/RSS, the number of associated PTGs
of one Profile may exceed the defined ICE_MAX_PTG_PER_PROFILE and
ICE_MAX_TCAM_PER_PROFILE. In those cases, some PTGs may be missed,
and therefore, the related and received packets will not have hash
values. Thus, this patch updated the ICE_MAX_PTG_PER_PROFILE and
ICE_MAX_TCAM_PER_PROFILE to a larger number 64.
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Correct spelling of word data instead of date.
Fixes: 453d087cca ("net/ice/base: add common functions")
Cc: stable@dpdk.org
Signed-off-by: Kevin Scott <kevin.c.scott@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Rename ucast_shared to umac_shared, as "umac" is a more widely
used shorthand for "unicast MAC".
Also add a helper function to set this flag. This helper is
expected to be called by core drivers.
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
The IPv4/TCP/UDP/SCTP header checksum fields are defined in this
patch and can be used as RSS input sets.
Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Add logic to parse capabilities relating to the firmware update reset
requirements. This includes both capability 0x76, which informs the
driver if the firmware can sometimes skip PCIe resets, and 0x77, which
informs the driver if the firmware might potentially restrict EMP
resets.
For capability 0x76, if the number is 1, the firmware will report the
required reset level for a given update as part of its response to the
last command sent to program the NVM bank. (Otherwise, if the firmware
does not support this capability then it will always send a 0 in the
field of the response).
For capability 0x77, if the number is 1, the firmware will report when
EMP reset is available as part of the response to the command for
switching flash banks. (Otherwise, if the firmware does not support this
capability, it will always send a 0 in the field of the response
message).
These capabilities are required to implement immediate firmware
activation. If the capabilities are set, software can read the response
data and determine what reset level is required to activate the firmware
image. If only an EMP reset is required, and if the EMP reset is not
restricted by firmware, then the driver can issue an EMP reset to
immediately activate the new firmware.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
TC nodes CIR configuration is not supported. In order to configure PIR,
the corresponding adminq command should not include the flag for CIR.
Since the TC node info has this flag by default, it is supposed to delete
this flag for TC nodes before sending the adminq command.
Signed-off-by: Ting Xu <ting.xu@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Move replay_pre_init function to interface.
Add further MAC rules, despite unicast address is already on list.
Signed-off-by: Marcin Domagala <marcinx.domagala@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Add ice_aqc_sw_gpio struct to ice_aq_desc
This change allows us to do SW_GPIO AQ cmd transactions
over ice_aq_send_cmd() interface.
Signed-off-by: Siddaraju DH <siddaraju.dh@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Add function ice_is_e810t() to be able to distinguish if hardware is
E810T based or not.
Signed-off-by: Michal Michalik <michal.michalik@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
After starting the timestamping block, hardware begins calculating
precise offsets through a process of vernier calibration. This process
measures the effective phase offset of the various internal clocks used
in the PHY.
Once hardware completes these measurements, the P_REG_TX_OV_STATUS and
P_REG_RX_OV_STATUS registers are updated to indicate that the hardware
offset measurements are done.
This process does not happen immediately, but requires that at least one
packet be sent or received in order for the offset in that direction to
be calculated.
This poses a problem in some setups, because software expects the first
packet sent to be timestamped. This most often occurs if the clock time
is set by an application during startup. This set time command triggers
a PHY restart. Because of this, the timestamping block is reset, and
timestamps are not enabled until vernier calibration is complete. Since
this process won't complete until at least one packet is sent through
the PHY, timestamps of the very first packet sent will not be obtained.
This can result in the application failing due to missing timestamps.
To avoid this, allow starting the PHY in bypass mode. This mode enables
timestamps immediately, and skips adding the precise offset measurement.
This reduces the accuracy of the timestamp slightly, but ensures that we
get a reasonable value for the first packet.
The driver can continue monitoring the P_REG_TX_OV_STATUS and
P_REG_RX_OV_STATUS registers and exit bypass mode once the total
calibration is completed. In this way, once calibration is complete, the
timestamps will have the precise offset, but we do not break
applications which expect to be able to timestamp immediately.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Rework the comment around checking PFC mode to make it clear why we are
checking the mode after sending the command.
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Move the implementation of Vernier calibration from Linux core ice_ptp.c
into the shared ice_ptp_hw.c file.
This implementation was recently refactored in Linux, so the move should
be verbatim with the latest Linux code that we had implemented.
This includes a new constant table with pre-determined values based on
link speed, new functions to aide in reading the multi-register values
from the PHY, functions to program the PAR/PCS conversion ratios, and
the UIX conversion ratios, functions to program the total Tx and Rx
offset after vernier calibration in the hardware completes, and finally
a function to start and stop the PHY timestamping block.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
The E822 device clock might come from a variety of different sources,
called TIME_REFs. The firmware reports the current TIME_REF as part of
its function capabilities, which the driver caches when it loads.
Add an accessor function to look up the current TIME_REF from the
capabilities. This reduces line length significantly and also avoids
a tight coupling to the capabilities structure.
In some cases, TIME_REF might change at run time. This can occur in the
event that the CGU registers are updated. When this happens, its
possible that the capabilities structure can be out of date until the
capabilities are re-read.
Add a setter function to update the TIME_REF when this occurs. The
driver can call this function after updating the CGU to ensure that the
TIME_REF in the capabilities structure is up to date, without needing to
re-read the entire capabilities from firmware.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Before the device PTP hardware clock can be initialized, some steps must
be taken by the driver. This includes writing some registers and
initializing the PHY.
Some of these steps are distinct depending on the device type (E810 or
E822). Additionally, a future change will introduce more steps for E822
devices to program the Clock Generation Unit.
Introduce ice_ptp_init_phc as well as device-specific sub-functions for
e810 and e822 devices.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Adding macros for shift and masking of the lower timestamp work in the
Rx flex descriptor. The LSB of the timestamp-low word indicates the
validity of the timestamp while the rest 7 bits contain the timestamp.
Signed-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Ethertype was traded as VLAN tpid in dummy packets with VLAN.
This led to a problem when user wanted to add filter for VLAN and
ethertype.
Change ice_vlan_hdr to reflect correct order of VLAN fields in
packets (VLAN tpid, VLAN id). Correct all dummy packets with VLAN.
Move VLAN fields before ethertype and change offsets. Leave values
from dummy packets unchanged as they fit to new VLAN layout.
Order of offsets in ice_prot_ext_tbl_entry for VLAN protocol should
reflect order of fields in ice_vlan_hdr. However, hardware doesn't
support matching on all tpid. This should be done by matching on
packet flags. There is no FV word with protocol for VLAN and offset
2. Because of that, adding vlan tpid with not zero mask will lead
to error in creating recipe.
Signed-off-by: Michal Swiatkowski <michal.swiatkowski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
In order to support switch rule for ethertype filter
with ipv6 ethertype id, it has to check ethertype and
then find a proper dummy packet. There was a silent
assumption that packet is ipv4, unless src or dst ipv6
address is specified in a flow.
Signed-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
The ice hardware supports exposing a hardware clock for high precision
timestamping. This is primarily intended for accelerating the Precision
Time Protocol.
Add several low level functions intended to be used as the basis for
enabling the device clock, and ensuring that the port timers are
synchronized properly.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
Build on aarch64 with clang-10 has warning:
i40e_rxtx.c:3228:1:
warning: unused function 'get_avx_supported' [-Wunused-function]
The function is used in x86 specific path. Moved it into ifdef
to fix build on non-x86.
Fixes: c30751afc3 ("net/i40e: fix data path selection in secondary process")
Cc: stable@dpdk.org
Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
This patch fixes the reversed priority of DCF switch rule. Priority 0
and 1 are supported, and priority 0 should be the highest priority.
Fixes: 2321e34c23 ("net/ice: support flow priority for DCF switch filter")
Cc: stable@dpdk.org
Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
For N1 platform, packet mbuf load and descs load are hot spots to limit
the performance for "desc_to_ptype_v" and "desc_to_olflags_v" functions
in i40e rx NEON path. This is because packet mbuf and descs are evicted
from l1d-cache to l2d-cache.
To reduce l1d-cache-misses and improve the performance, change the code
order and move "desc_to_ptype_v" and "desc_to_olflags_v" functions
forward to the location, where packet mbuf and descs are just loaded.
Test Result:
dpdk:21.08-rc1
gcc-9
For n1sdp, the patch improves the performance by 1.8%.
For thunderx2, no performance changes.
Signed-off-by: Feifei Wang <feifei.wang2@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
