Index overflow when resetting big queues was partially fixed in
bcf457f8c0d64a5c (ixgbe: fix index overflow when resetting big Tx queues)
and better fixed in
e8ae856140bce4e4 (igb/ixgbe: fix index overflow when resetting big queues)
But this version (1.5.2r0) has residues of the initial fix from 1.5.1r0.
Signed-off-by: Intel
ICC requires an initializer be given for the static variables,
so adding one in cases where one wasn't previously given.
This problem was introduced in commit e8ae856140bce4e
(fix index overflow when resetting big queues).
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Thomas Monjalon <thomas.monjalon@6wind.com>
Rings are resetted with a loop because memset cannot be used without
issuing a warning about volatile casting.
The index of the loop was a 16-bit variable which is sufficient for
ring entries number but not for the byte size of the whole ring.
The overflow happens when rings are configured for 4096 entries
(descriptor size is 16 bytes). The result is an endless loop.
It is fixed by indexing ring entries and resetting all bytes of the entry
with a simple assignment.
The descriptor initializer is zeroed thanks to its static declaration.
There already was a fix for ixgbe Tx only
(commit bcf457f8c0d64a5cb094fd55836b324bddb930b6).
It is reverted to use the same fix everywhere (Rx/Tx for igb/ixgbe).
Signed-off-by: Thomas Monjalon <thomas.monjalon@6wind.com>
Acked-by: Ivan Boule <ivan.boule@6wind.com>
The index of the loop was a 16-bit variable which is sufficient for
ring entries number but not for the byte size of the whole ring.
The overflow happens when queue rings are configured for 4096 entries
(descriptor size is 16 bytes). The result is an endless loop.
Signed-off-by: Intel
In case of multi-process application, the secondary process can initialize
the driver without configuring queues. In this case the Rx/Tx functions
were not initialized because it was only done in queue setup.
Fix by reproducing the same behaviour as in eth_ixgbe_dev_init().
Signed-off-by: Intel
Need to change PCI code to support multiple I/O regions on a single device.
Some devices like VMXNET3 have multiple PCI memory regions, and some
have none.
Signed-off-by: Stephen Hemminger <shemminger@vyatta.com>
Signed-off-by: Intel
Fix warnings of type "Value stored to 'xxx' is never read".
Signed-off-by: Zijie Pan <zijie.pan@6wind.com>
Acked-by: Ivan Boule <ivan.boule@6wind.com>
Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
