The qp is never NULL when it reaches the qp_setup_cleanup error handling
code. This is due to checks earlier in the function that return an error
if qp is NULL.
Coverity issue: 375013
Fixes: 581c39b1cb7d ("crypto/ipsec_mb: fix queue cleanup null pointer dereference")
Cc: stable@dpdk.org
Signed-off-by: Ciara Power <ciara.power@intel.com>
Using deschedule cmd might incorrectly ignore updates
to WQE, GGRP on CN9K.
Use addwork to pipeline work instead.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
When attempting to link a port and queue immediately after unlinking,
the CQ inflights may not all be processed. Poll the h/w register for
outstanding inflights instead of reading once, in case the inflights
are still being processed. Also return EBUSY if the inflight
processing is not completed in a suitable amount of time.
Fixes: 1857f1922ce2 ("event/dlb2: use new implementation of resource file")
Cc: stable@dpdk.org
Signed-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>
Update the rolling mask used in dequeue operations to
fix the vector optimized dequeue.
Fixes: 000a7b8e7582 ("event/dlb2: optimize dequeue operation")
Cc: stable@dpdk.org
Signed-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>
Removed RTE_SCHED_SUBPORT_TC_OV from rte_config.h.
Best effort traffic class oversubscription is always enabled.
Signed-off-by: Megha Ajmera <megha.ajmera@intel.com>
Acked-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
Even though nonexistent cnxk_gpio is unlikely at this point
it's a good practice to check pointers before using them.
Fixes: 0e6557b448fa ("raw/cnxk_gpio: add self test")
Coverity issue: 376502
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
All used resources need to be properly cleaned up in error path.
Fixes: 0e6557b448fa ("raw/cnxk_gpio: add self test")
Coverity issue: 376504
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
When configuring an Intel DSA instance using the utility script
dpdk_idxd_cfg.py, explicitly set the max supported batch size value to a
high value, to ensure large bursts are supported if so desired. The
default in the linux kernel is now just 32 [1], which may not be
sufficient for all DPDK apps.
[1] https://lore.kernel.org/r/163528473483.3926048.7950067926287180976.stgit@djiang5-desk3.ch.intel.com
Cc: stable@dpdk.org
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Reviewed-by: Kevin Laatz <kevin.laatz@intel.com>
For DMA device 0000:7d:0.0, the original generated dmadev name starts
with the "7d:0.0", which is not expected.
This patch uses rte_pci_device_name API to generates the dmadev name.
Cc: stable@dpdk.org
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
The Kunpeng930 DMA devices have the same PCI device id with Kunpeng920,
but with different PCI revision and register layout. This patch
introduces the basic initialization for Kunpeng930 DMA devices.
Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
The default mempool driver is one based on the rte_ring, and as such it
needs to be present to have just about any app (which doesn't override
the mempool) run. Given this state of affairs it is probably best to add
this default mempool driver to the always-enabled list to ensure we get
a runnable build in all cases. This means that, for example, to run some
NIC tests with testpmd in a minimal build, in most cases, all the user
should need to do is specify "-Denable_drivers=net/<nic_drv>" for the
build.
Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Morten Brørup <mb@smartsharesystems.com>
Add PMD parameter that allows one to select only subset of available
GPIOs.
This might be useful in cases where some GPIOs are already reserved yet
still available for userspace access but particular app should not touch
them.
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
Add support for custom interrupt handlers. Custom interrupt
handlers bypass kernel completely and are meant for fast
and low latency access to GPIO state.
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Add initial support for PMD that allows to control particular pins form
userspace. Moreover PMD allows to attach custom interrupt handlers to
controllable GPIOs.
Main users of this PMD are dataplain applications requiring fast and low
latency access to pin state.
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Improve vWQE and CQ Rx performance by tuning perfetches to 64B
cacheline size.
Also, prefetch the vWQE array offsets at cacheline boundaries.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Setting WAITW bit enables default min dequeue timeout of 1us.
Avoid the min dequeue timeout by setting WAITW only when dequeue_timeout
is configured.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Store and reuse workslot status for TT, GRP and HEAD status
instead of reading from GWC as reading from GWC imposes
additional latency.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Add support for allow or block list for devices bound
to the kernel driver.
When used the allow or block list applies as an additional
condition to the name prefix.
Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
Reviewed-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: Kevin Laatz <kevin.laatz@intel.com>
Before registering the doorbell interrupt handler callback function,
all the valid doorbell bits within the NTB private data struct should
be cleared to avoid the confusion of the handshake timing sequence
diagram when setting up the NTB connection in back-to-back mode.
Fixes: 62012a76811e ("raw/ntb: add handshake process")
Cc: stable@dpdk.org
Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Acked-by: Jingjing Wu <jingjing.wu@intel.com>
Adding useful debug prints in DPAA driver for
easy debugging. A devarg is added to enable various levels
of prints.
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
This patch supports ordered queue for DPAA2 platform.
A devarg is added to enable strict ordering.
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
This patch add more checks on next type for PDCP cases.
Fixes: 45e019608f31 ("crypto/dpaa2_sec: support integrity only PDCP")
Fixes: a1173d55598c ("crypto/dpaa_sec: support PDCP offload")
Cc: stable@dpdk.org
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Few useful debug prints added in dequeue function.
These are controlled via pmd devargs. Details of using the
devarg is updated in dpaa2_sec.rst
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Add IV size and change the digest size to supported
value by the HW engine.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
DPAA1 and DPAA2 platforms use SEC ERA 8 and 10 only.
Hence, code related to old SEC-ERA (1-7) is removed.
This patch removes code in SDAP and PDCP header related to these
ERA to simplify the codebase:
- Simplify logic using RTA_SEC_ERA_<> macro
- Remove era_2_sw_hfn_ovrd dedicated to RTA_SEC_ERA_2
Signed-off-by: Franck Lenormand <franck.lenormand@nxp.com>
Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
Rather than using a session buffer that contains pointers to private
session data elsewhere, have a single session buffer.
This session is created for a driver ID, and the mempool element
contains space for the max session private data needed for any driver.
Signed-off-by: Ciara Power <ciara.power@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Pending queue also need to be adjusted while updating the number of
descriptors.
Fixes: a455fd869cd7 ("common/cnxk: align CPT queue depth to power of 2")
Cc: stable@dpdk.org
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
CPT inflight request is used to track a request that is enqueued to
cryptodev. Having more than one inst use the same cacheline can result
in serialization of CPT result memory writes causing perf degradations.
Align inflight request to ROC cache line to ensure only one result would
be written per cache line..
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
This patch fix the cipher params configuration in AEAD job if
QAT GEN4 unified cipher slice(UCS) enabled.
Fixes: 328d690d2f60 ("crypto/qat: update raw data path")
Cc: stable@dpdk.org
Signed-off-by: Kai Ji <kai.ji@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
