The ethdev port id should be 16 bits now. This patch changes the
variable size of port id in some net drivers from 8 bits to 16
bits.
Fixes: 09b23f8b9df6 ("net/bnxt: fix port stop process and cleanup resources")
Fixes: 769de16872ab ("net/bnxt: fix port default rule create/destroy")
Fixes: 50370662b727 ("net/ice: support device and queue ops")
Fixes: a50d7cbbdad7 ("net/qede: support registers dump")
Cc: stable@dpdk.org
Signed-off-by: Chenbo Xia <chenbo.xia@intel.com>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
This patch adds required bit to handle VF FLR
indication from Management FW (MFW) of the device
With that VFs were able to load in VM (VF attached as PCI
passthrough to the guest VM) followed by FLR successfully
Updated the docs/guides with the feature support
Signed-off-by: Manish Chopra <manishc@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: Rasesh Mody <rmody@marvell.com>
This patch adds necessary infrastructure support (required to handle
messages from VF and sending ramrod on behalf of VF's configuration
request from alarm handler context) to start/load the VF-PMD driver
instance on top of PF-PMD driver instance.
Signed-off-by: Manish Chopra <manishc@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: Rasesh Mody <rmody@marvell.com>
This patch defines various PCI config space access APIs
in order to read and find IOV specific PCI capabilities.
With these definitions implemented, it enables the base
driver to do SR-IOV specific initialization and HW specific
configuration required from PF-PMD driver instance.
Signed-off-by: Manish Chopra <manishc@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: Rasesh Mody <rmody@marvell.com>
The macro defined for milliseconds sleep was not putting the thread
to sleep and was simply calling a delay routine. This fix redefines
the macro to call the correct rte sleep API.
Fixes: ec94dbc57362 ("qede: add base driver")
Cc: stable@dpdk.org
Signed-off-by: Devendra Singh Rawat <dsinghrawat@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: Rasesh Mody <rmody@marvell.com>
Add support for .get_reg eth_dev ops which will be used to collect the
firmware debug data.
PMD on detecting on some HW errors will collect the FW/HW Dump to a
buffer and then it will save it to a file implemented in
qede_save_fw_dump().
Dump file location and name:
Location: <RTE_SDK> or DPDK root
Name: qede_pmd_dump_mm-dd-yy_hh-mm-ss.bin
DPDK applications can initiate a debug data collection by invoking DPDK
library’s rte_eth_dev_get_reg_info() API. This API invokes .get_reg()
interface in the PMD.
PMD implementation of .get_reg() collects the FW/HW Dump, saves it to
data field of rte_dev_reg_info and passes it to the application. It’s
the responsibility of the application to save the FW/HW Dump to a file.
We recommendation using the file name format used by qede_save_fw_dump().
Signed-off-by: Rasesh Mody <rmody@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
The patch adds QEDE PMD ops and APIs to calculate the size and collect
the debug dump for various firmware components. The patch adds new files
qede_debug.[ch] that has all the firmware debug data collection
infrastructure changes.
Signed-off-by: Rasesh Mody <rmody@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
This patch adds base driver APIs required for debug data collection.
It adds support for dumping internal lookup tables(ilt), reading nvram
image, register definitions.
Signed-off-by: Rasesh Mody <rmody@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Remove its own bit operation APIs and use the common one,
this can reduce the code duplication largely.
Signed-off-by: Joyce Kong <joyce.kong@arm.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
There is a common macro __rte_unused, avoiding warnings,
which is now used where appropriate for consistency.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Replace 'typedef int bool' with 'stdbool.h' to avoid possible
multiple definitions of 'bool'.
(Not sure if the previous code is checking for true/false condition.
Recommend careful review on this patch.)
Signed-off-by: Dharmik Thakkar <dharmik.thakkar@arm.com>
Reviewed-by: Phil Yang <phil.yang@arm.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
Update and add runtime array offsets (rt defs), non-volatile memory
configuration options (nvm cfg) and management co-processor (mcp)
shared code in preparation to update the firmware to version 8.40.25.0.
Signed-off-by: Rasesh Mody <rmody@marvell.com>
Add 'RTE_' prefix to defines:
- rename ETHER_ADDR_LEN as RTE_ETHER_ADDR_LEN.
- rename ETHER_TYPE_LEN as RTE_ETHER_TYPE_LEN.
- rename ETHER_CRC_LEN as RTE_ETHER_CRC_LEN.
- rename ETHER_HDR_LEN as RTE_ETHER_HDR_LEN.
- rename ETHER_MIN_LEN as RTE_ETHER_MIN_LEN.
- rename ETHER_MAX_LEN as RTE_ETHER_MAX_LEN.
- rename ETHER_MTU as RTE_ETHER_MTU.
- rename ETHER_MAX_VLAN_FRAME_LEN as RTE_ETHER_MAX_VLAN_FRAME_LEN.
- rename ETHER_MAX_VLAN_ID as RTE_ETHER_MAX_VLAN_ID.
- rename ETHER_MAX_JUMBO_FRAME_LEN as RTE_ETHER_MAX_JUMBO_FRAME_LEN.
- rename ETHER_MIN_MTU as RTE_ETHER_MIN_MTU.
- rename ETHER_LOCAL_ADMIN_ADDR as RTE_ETHER_LOCAL_ADMIN_ADDR.
- rename ETHER_GROUP_ADDR as RTE_ETHER_GROUP_ADDR.
- rename ETHER_TYPE_IPv4 as RTE_ETHER_TYPE_IPv4.
- rename ETHER_TYPE_IPv6 as RTE_ETHER_TYPE_IPv6.
- rename ETHER_TYPE_ARP as RTE_ETHER_TYPE_ARP.
- rename ETHER_TYPE_VLAN as RTE_ETHER_TYPE_VLAN.
- rename ETHER_TYPE_RARP as RTE_ETHER_TYPE_RARP.
- rename ETHER_TYPE_QINQ as RTE_ETHER_TYPE_QINQ.
- rename ETHER_TYPE_ETAG as RTE_ETHER_TYPE_ETAG.
- rename ETHER_TYPE_1588 as RTE_ETHER_TYPE_1588.
- rename ETHER_TYPE_SLOW as RTE_ETHER_TYPE_SLOW.
- rename ETHER_TYPE_TEB as RTE_ETHER_TYPE_TEB.
- rename ETHER_TYPE_LLDP as RTE_ETHER_TYPE_LLDP.
- rename ETHER_TYPE_MPLS as RTE_ETHER_TYPE_MPLS.
- rename ETHER_TYPE_MPLSM as RTE_ETHER_TYPE_MPLSM.
- rename ETHER_VXLAN_HLEN as RTE_ETHER_VXLAN_HLEN.
- rename ETHER_ADDR_FMT_SIZE as RTE_ETHER_ADDR_FMT_SIZE.
- rename VXLAN_GPE_TYPE_IPV4 as RTE_VXLAN_GPE_TYPE_IPV4.
- rename VXLAN_GPE_TYPE_IPV6 as RTE_VXLAN_GPE_TYPE_IPV6.
- rename VXLAN_GPE_TYPE_ETH as RTE_VXLAN_GPE_TYPE_ETH.
- rename VXLAN_GPE_TYPE_NSH as RTE_VXLAN_GPE_TYPE_NSH.
- rename VXLAN_GPE_TYPE_MPLS as RTE_VXLAN_GPE_TYPE_MPLS.
- rename VXLAN_GPE_TYPE_GBP as RTE_VXLAN_GPE_TYPE_GBP.
- rename VXLAN_GPE_TYPE_VBNG as RTE_VXLAN_GPE_TYPE_VBNG.
- rename ETHER_VXLAN_GPE_HLEN as RTE_ETHER_VXLAN_GPE_HLEN.
Do not update the command line library to avoid adding a dependency to
librte_net.
Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
Reviewed-by: Stephen Hemminger <stephen@networkplumber.org>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
This fix adds a ecore_mcp_update_stag() handler to handle the STAG update
events from management FW and program the STAG value.
It also clears the stag config on PF, when management FW invalidates
the stag value.
Fixes: ec94dbc57362 ("qede: add base driver")
Cc: stable@dpdk.org
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
We were using LICENSE.qede_pmd to reference inclusion of SPDX licensing
tag from all the source file. Remove the LICENSE.qede_pmd file and
directly include SPDX tags in source files.
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
8ea656f8c app/testpmd: request link status interrupt
requires QEDE PMD to populate the device link structure without
having to query the driver for link status change event.
This patch updates the device link structure when link status event is
received.
Remove unused param from qed_link_update()
Fixes: 86a2265e59d7 ("qede: add SRIOV support")
Fixes: ec94dbc57362 ("qede: add base driver")
Cc: stable@dpdk.org
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
Renamed data type from phys_addr_t to rte_iova_t.
Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Reviewed-by: Anatoly Burakov <anatoly.burakov@intel.com>
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
- Introduce OSAL_IOV_VF_VPORT_STOP to allow VF to carry out required
operations and prevent a potential assert before closing vport
- Add OSAL_DIV_S64() for 64-bit division on 32-bit platforms.
- Add OSAL for transceiver update OSAL_TRANSCEIVER_UPDATE()
- Add OSAL for MFW command preemption OSAL_MFW_CMD_PREEMPT() within the
spinning loops while sending a mailbox command to the MFW
- Implement OSAL_SPIN_LOCK_IRQSAVE macro
- Rename OSAL_NUM_ACTIVE_CPU() to OSAL_NUM_CPUS()
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
This is an attempt to clean up many unused API parameters across the base
code. Most of the changes are related to removing unused p_hwfn or p_ptt
handlers. The warnings are generated using 'unused-parameter' cflags.
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
Add support for doorbell overflow recovery mechanism:
The doorbell recovery mechanism consists of a list of entries which
represent doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath
spq, etc). Each entity needs to register with the mechanism and provide
the parameters describing it's doorbell, including a location where last
used doorbell data can be found. The doorbell execute function will
traverse the list and doorbell all of the registered entries.
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
Revise the manamgement FW mbox access locking scheme for the access to the
MFW mailbox:
- add a new linked list called cmd_list to ecore_mcp_info that tracks all
the mailbox commands sent to management FW and ones waiting for
response.
- add a mutex lock called cmd_lock to ecore_mcp_info, a spinlock used to
serialize the access to this cmd_list and makes sure that the mbox is
not a pending one before sending a new mbox request. It protects the
access to the mailbox commands list and sending of the commands.
- add ecore_mcp_cmd_add|del|get_elem() APIs for new access scheme
- remove ecore_mcp_mb_lock() and ecore_mcp_mb_unlock()
- add a mutex lock called link_lock to ecore_mcp_info, a spinlock used for
syncing SW link-changes and link-changes originating from attention
context. This locking scheme prevents possible race conditions that may
occur, such as during link status reporting.
- Surround OSAL_{MUTEX,SPIN_LOCK}_{ALLOC,DEALLOC} with
'#ifdef CONFIG_ECORE_LOCK_ALLOC'. In case memory has to be allocated for
lock primitives, then compile driver with CONFIG_ECORE_LOCK_ALLOC flag.
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
Use the ptt[PF translation table] handler that is passed rather than using
main ptt from the HW function.
In ecore_hw_get_resc()'s error flow, release the MFW generic resource lock
only if needed.
Change the verbosity level of GRC timeout from DP_INFO() to DP_NOTICE().
Reduce verbosity of print in ecore_hw_bar_size().
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
Move ecore_crc32() macro to within base driver to qede_crc32() and use
OSAL_CRC32() where required.
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
Log HW errmsg on the stdout and do minimal handling to prevent HW
attentions from being reasserted.
Signed-off-by: Harish Patil <harish.patil@cavium.com>
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
Implement the macro OSAL_DMA_FREE_COHERENT to release DMA memories.
Track all DMA memory allocations using an array of memzone pointers and
use that to free memory resources along with other resource deallocation.
With this change there is no need to alter the base code to additionally
pass an unique string needed for memzone creation.
Fixes: ec94dbc57362 ("qede: add base driver")
Cc: stable@dpdk.org
Signed-off-by: Harish Patil <harish.patil@cavium.com>
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
Merge hw_stop and hw_reset into one function.
Prevent race condition between MFW attentions and pf stop command during
unload flow that causes an ASSERT.
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
Set pointers to NULL after freeing the allocations. Change OSAL_FREE
macro to take care of this and cleanup relevant code.
Fixes: 26ae839d06e9 ("qede: add DCBX support")
Fixes: ec94dbc57362 ("qede: add base driver")
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
Replace the raw I/O device memory read/write access with eal
abstraction for I/O device memory read/write access to fix
portability issues across different architectures.
CC: Harish Patil <harish.patil@cavium.com>
CC: Rasesh Mody <rasesh.mody@cavium.com>
Signed-off-by: Santosh Shukla <santosh.shukla@caviumnetworks.com>
Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Receive indication that VFs are malicious and pass it to the
caller/clients and stop serving those VF's additional resource requests.
Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
This patch updates the base driver and incorporates necessary changes
required to bring in the new firmware 8.10.9.0.
In addition, it would allow driver to add new functionalities that might
be needed in future.
Signed-off-by: Rasesh Mody <rasesh.mody@qlogic.com>
Change ecore_mcp_cmd_and_union() to accept pointer to a structure rather
than accepting multiple arguments. A new struct ecore_mcp_mb_params is
added for that purpose. Also make this function static. This change is
mostly keeping in mind the future requests which needs additional
arguments.
Signed-off-by: Harish Patil <harish.patil@qlogic.com>
In case of attention from a signal that's represented by multiple bits
in misc AEU, add the format string which is populated with proper index
and resulting prints will show string as a prefix.
Signed-off-by: Rasesh Mody <rasesh.mody@qlogic.com>
Under certain scenarios, management firmware (MFW) periodically polls
the driver for LAN statistics. This patch implements the osal hook to
fill in the stats.
Fixes: ec94dbc57362 ("qede: add base driver")
Signed-off-by: Harish Patil <harish.patil@qlogic.com>
This patch adds LLDP and DCBX capabilities to the qede PMD.
Signed-off-by: Harish Patil <harish.patil@qlogic.com>
Signed-off-by: Rasesh Mody <rasesh.mody@qlogic.com>
Signed-off-by: Sony Chacko <sony.chacko@qlogic.com>
The base driver is the backend module for the QLogic FastLinQ QL4xxxx
25G/40G CNA family of adapters as well as their virtual functions (VF)
in SR-IOV context.
The purpose of the base module is to:
- provide all the common code that will be shared between the various
drivers that would be used with said line of products. Flows such as
chip initialization and de-initialization fall under this category.
- abstract the protocol-specific HW & FW components, allowing the
protocol drivers to have clean APIs, which are detached in its
slowpath configuration from the actual Hardware Software Interface(HSI).
This patch adds a base module without any protocol-specific bits.
I.e., this adds a basic implementation that almost entirely falls under
the first category.
Signed-off-by: Harish Patil <harish.patil@qlogic.com>
Signed-off-by: Rasesh Mody <rasesh.mody@qlogic.com>
Signed-off-by: Sony Chacko <sony.chacko@qlogic.com>
