26e09db6cb
The tests are registered with their command name by adding a structure to a list. The structure of each test was declared in each test file and passed to the register macro. This rework generate the structure inside the register macro. Signed-off-by: Thomas Monjalon <thomas.monjalon@6wind.com> Reviewed-by: Jan Viktorin <viktorin@rehivetech.com>
206 lines
5.5 KiB
C
206 lines
5.5 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright(c) 2015 Akamai Technologies.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "test.h"
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#include <stdio.h>
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#include <unistd.h>
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#include <inttypes.h>
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#include <rte_cycles.h>
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#include <rte_timer.h>
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#include <rte_common.h>
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#include <rte_lcore.h>
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#include <rte_random.h>
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#include <rte_malloc.h>
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#undef TEST_TIMER_RACECOND_VERBOSE
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#ifdef RTE_EXEC_ENV_LINUXAPP
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#define usec_delay(us) usleep(us)
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#else
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#define usec_delay(us) rte_delay_us(us)
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#endif
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#define BILLION (1UL << 30)
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#define TEST_DURATION_S 20 /* in seconds */
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#define N_TIMERS 50
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static struct rte_timer timer[N_TIMERS];
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static unsigned timer_lcore_id[N_TIMERS];
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static unsigned master;
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static volatile unsigned stop_slaves;
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static int reload_timer(struct rte_timer *tim);
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static void
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timer_cb(struct rte_timer *tim, void *arg __rte_unused)
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{
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/* Simulate slow callback function, 100 us. */
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rte_delay_us(100);
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#ifdef TEST_TIMER_RACECOND_VERBOSE
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if (tim == &timer[0])
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printf("------------------------------------------------\n");
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printf("timer_cb: core %u timer %lu\n",
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rte_lcore_id(), tim - timer);
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#endif
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(void)reload_timer(tim);
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}
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RTE_DEFINE_PER_LCORE(unsigned, n_reset_collisions);
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static int
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reload_timer(struct rte_timer *tim)
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{
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/* Make timer expire roughly when the TSC hits the next BILLION
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* multiple. Add in timer's index to make them expire in nearly
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* sorted order. This makes all timers somewhat synchronized,
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* firing ~2-3 times per second, assuming 2-3 GHz TSCs.
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*/
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uint64_t ticks = BILLION - (rte_get_timer_cycles() % BILLION) +
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(tim - timer);
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int ret;
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ret = rte_timer_reset(tim, ticks, PERIODICAL, master, timer_cb, NULL);
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if (ret != 0) {
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#ifdef TEST_TIMER_RACECOND_VERBOSE
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printf("- core %u failed to reset timer %lu (OK)\n",
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rte_lcore_id(), tim - timer);
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#endif
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RTE_PER_LCORE(n_reset_collisions) += 1;
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}
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return ret;
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}
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static int
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slave_main_loop(__attribute__((unused)) void *arg)
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{
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unsigned lcore_id = rte_lcore_id();
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unsigned i;
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RTE_PER_LCORE(n_reset_collisions) = 0;
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printf("Starting main loop on core %u\n", lcore_id);
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while (!stop_slaves) {
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/* Wait until the timer manager is running.
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* We know it's running when we see timer[0] NOT pending.
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*/
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if (rte_timer_pending(&timer[0])) {
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rte_pause();
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continue;
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}
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/* Now, go cause some havoc!
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* Reload our timers.
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*/
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for (i = 0; i < N_TIMERS; i++) {
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if (timer_lcore_id[i] == lcore_id)
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(void)reload_timer(&timer[i]);
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}
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usec_delay(100*1000); /* sleep 100 ms */
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}
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if (RTE_PER_LCORE(n_reset_collisions) != 0) {
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printf("- core %u, %u reset collisions (OK)\n",
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lcore_id, RTE_PER_LCORE(n_reset_collisions));
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}
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return 0;
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}
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static int
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test_timer_racecond(void)
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{
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int ret;
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uint64_t hz;
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uint64_t cur_time;
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uint64_t end_time;
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int64_t diff = 0;
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unsigned lcore_id;
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unsigned i;
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master = lcore_id = rte_lcore_id();
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hz = rte_get_timer_hz();
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/* init and start timers */
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for (i = 0; i < N_TIMERS; i++) {
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rte_timer_init(&timer[i]);
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ret = reload_timer(&timer[i]);
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TEST_ASSERT(ret == 0, "reload_timer failed");
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/* Distribute timers to slaves.
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* Note that we assign timer[0] to the master.
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*/
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timer_lcore_id[i] = lcore_id;
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lcore_id = rte_get_next_lcore(lcore_id, 1, 1);
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}
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/* calculate the "end of test" time */
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cur_time = rte_get_timer_cycles();
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end_time = cur_time + (hz * TEST_DURATION_S);
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/* start slave cores */
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stop_slaves = 0;
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printf("Start timer manage race condition test (%u seconds)\n",
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TEST_DURATION_S);
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rte_eal_mp_remote_launch(slave_main_loop, NULL, SKIP_MASTER);
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while (diff >= 0) {
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/* run the timers */
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rte_timer_manage();
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/* wait 100 ms */
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usec_delay(100*1000);
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cur_time = rte_get_timer_cycles();
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diff = end_time - cur_time;
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}
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/* stop slave cores */
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printf("Stopping timer manage race condition test\n");
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stop_slaves = 1;
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rte_eal_mp_wait_lcore();
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/* stop timers */
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for (i = 0; i < N_TIMERS; i++) {
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ret = rte_timer_stop(&timer[i]);
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TEST_ASSERT(ret == 0, "rte_timer_stop failed");
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}
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return TEST_SUCCESS;
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}
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REGISTER_TEST_COMMAND(timer_racecond_autotest, test_timer_racecond);
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