numam-dpdk/drivers
Suanming Mou a1978aa23b crypto/mlx5: add maximum segments configuration
The mlx5 HW crypto operations are done by attaching crypto property
to a memory region. Once done, every access to the memory via the
crypto-enabled memory region will result with in-line encryption or
decryption of the data.

As a result, the design choice is to provide two types of WQEs. One
is UMR WQE which sets the crypto property and the other is rdma write
WQE which sends DMA command to copy data from local MR to remote MR.

The size of the WQEs will be defined by a new devarg called
max_segs_num.

This devarg also defines the maximum segments in mbuf chain that will be
supported for crypto operations.

Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
2021-07-20 22:27:00 +02:00
..
baseband log: register with standardized names 2021-05-11 15:17:55 +02:00
bus bus/pci: fix leak for unbound devices 2021-07-06 11:27:55 +02:00
common crypto/mlx5: introduce Mellanox crypto driver 2021-07-20 21:45:58 +02:00
compress compress/isal: support Arm platform 2021-07-20 10:32:05 +02:00
crypto crypto/mlx5: add maximum segments configuration 2021-07-20 22:27:00 +02:00
event event/cnxk: support vectorized Tx event fast path 2021-07-16 14:16:50 +02:00
mempool mempool/octeontx2: fix shift calculation 2021-06-30 18:42:54 +02:00
net net/octeontx2: clear SA valid during session destroy 2021-07-20 10:32:05 +02:00
raw raw/ioat: fix termination descriptor for batch 2021-07-20 15:28:43 +02:00
regex log: register with standardized names 2021-05-11 15:17:55 +02:00
vdpa net/mlx5: support matching on VXLAN reserved field 2021-07-13 15:06:43 +02:00
meson.build log: register with standardized names 2021-05-11 15:17:55 +02:00