Tal Shnaiderman c1a320bf89 net/mlx5: fix tunneling support query ... Currently, the PMD decides if the tunneling offload can enable VXLAN/GRE/GENEVE tunneled TSO support by checking config->tunnel_en (single bit) and config->tso. This is incorrect, the right way is to check the following flags returned by the mlx5dv_query_device function: MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN - if supported the offload DEV_TX_OFFLOAD_VXLAN_TNL_TSO can be enabled. MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE - if supported the offload DEV_TX_OFFLOAD_GRE_TNL_TSO can be enabled. MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE - if supported the offload DEV_TX_OFFLOAD_GENEVE_TNL_TSO can be enabled. The fix enables the offloads according to the correct flags returned by the kernel. Fixes: dbccb4cddc ("net/mlx5: convert to new Tx offloads API") Cc: stable@dpdk.org Signed-off-by: Tal Shnaiderman <talshn@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com> Tested-by: Idan Hackmon <idanhac@nvidia.com>		2021-10-12 15:29:34 +02:00
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baseband	baseband/la12xx: support enqueue and dequeue	2021-10-18 20:12:08 +02:00
bus	bus/vmbus: fix ring buffer mapping in secondary process	2021-10-13 13:55:09 +02:00
common	common/mlx5: read software parsing capabilities from DevX	2021-10-12 15:29:33 +02:00
compress	compress/mlx5: refactor HW queue object	2021-10-05 18:15:40 +02:00
crypto	crypto/dpaa_sec: support AEAD and proto with raw API	2021-10-17 19:32:13 +02:00
dma	dmadev: add burst capacity API	2021-10-18 11:17:30 +02:00
event	mempool: add namespace to internal helpers	2021-10-20 10:00:18 +02:00
mempool	mempool: add namespace to driver register macro	2021-10-20 10:00:18 +02:00
net	net/mlx5: fix tunneling support query	2021-10-12 15:29:34 +02:00
raw	raw/cnxk_bphy: use ROC calls for max IRQ get	2021-10-07 13:02:48 +02:00
regex	regex/mlx5: refactor HW queue objects	2021-10-05 18:15:40 +02:00
vdpa	common/mlx5: share DevX queue pair operations	2021-10-05 18:15:40 +02:00
meson.build	dmadev: introduce DMA device library	2021-10-17 20:49:57 +02:00