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freebsd-dev/sys/mips/conf/DB120.hints

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Add some initial board support for the AR934x and the Qualcomm Atheros DB120 development board. The AR934x SoCs are a MIPS74k based system with increased RAM addressing space, some scratch-pad RAM, an improved gige switch PHY and 2x2 or 3x3 on-board dual-band wifi. This support isn't complete by any stretch; it's just enough to bring the board up for others to tinker with. Notably, the MIPS74k support is broken. However it boots enough to echo some basic probe/attach messages, before dying somewhere in the TLB code. Thankyou to Qualcomm Atheros for their continued support of me doing open source work with their hardware. Tested: * AR9344, mips74k
2013-07-21 04:00:48 +00:00
# $FreeBSD$
# This is a placeholder until the hardware support is complete.
Now that all of the on-chip switch and basic platform support is updated, we can now add all the hardware bits for the DB120. * arge0/argemdio0 is hooked up to an AR8327 switch - which there's currently no support for. However, the bootloader on this board does set it up as a basic switch so we can at least _use_ it ourselves. So we should at least configure the arge0 side of things, including the GMAC register. * .. the GMAC config peels off arge0 from the internal switch and exposes it as an RGMII to said AR8327. * arge1/argemdio1 are hooked up to an internal 10/100 switch. So, that also needs configuring. * Add support for the NOR flash layout. * Add support for the wifi (which works, with bugs, but it works.) What's missing! * No GPIO stuff yet! * No sound (I2S) and no NAND flash support yet, sorry! * The normal DB120 has an external AR95xx wifi chip on PCIe but with the actual calibration data in the NOR flash. My DB120 has been modified to let me use the PCIe slot as a normal PCIe slot. I'll add the "default" settings later when I have access to a non-modified one. * Other stuff, like why the wifi unit gets upset and spits out stuck beacons and interrupt storms everywhere. Sigh. Tested: * DB120 board - AR9344 (mips74k SoC) booting off of SPI flash into multi-user mode.
2013-10-16 04:22:26 +00:00
# mdiobus0 on arge0
hint.argemdio.0.at="nexus0"
hint.argemdio.0.maddr=0x19000000
hint.argemdio.0.msize=0x1000
hint.argemdio.0.order=0
# DB120 GMAC configuration
# + AR934X_ETH_CFG_RGMII_GMAC0 (1 << 0)
# + AR934X_ETH_CFG_SW_ONLY_MODE (1 << 6)
hint.ar934x_gmac.0.gmac_cfg=0x41
# GMAC0 here - connected to an AR8327
Add the AR8327 bits to the DB120 config file. There's plenty of hints that I haven't yet fleshed out and are hardcoded in arswitch_8327.c. They're listed here (from OpenWRT) for completeness. This is enough to get the thing up, running and pinging. Note that the mdiobus for the on-switch switch changes - the AR8327 probes first, which exposes mdio1, and thus the arge1 mdiobus will probe and attach as mdio2. That is what the AR9344 on-chip switch has to attach to. Tested: * Qualcomm Atheros DB120
2014-02-24 04:48:46 +00:00
hint.arswitch.0.at="mdio0"
hint.arswitch.0.is_7240=0
hint.arswitch.0.is_9340=0 # not the internal switch!
hint.arswitch.0.numphys=5
hint.arswitch.0.phy4cpu=0
hint.arswitch.0.is_rgmii=1
hint.arswitch.0.is_gmii=0
Add the DB120 specific hints for the AR8327. Tested: * DB120
2014-02-26 01:32:27 +00:00
# Other AR8327 configuration parameters
Add the AR8327 bits to the DB120 config file. There's plenty of hints that I haven't yet fleshed out and are hardcoded in arswitch_8327.c. They're listed here (from OpenWRT) for completeness. This is enough to get the thing up, running and pinging. Note that the mdiobus for the on-switch switch changes - the AR8327 probes first, which exposes mdio1, and thus the arge1 mdiobus will probe and attach as mdio2. That is what the AR9344 on-chip switch has to attach to. Tested: * Qualcomm Atheros DB120
2014-02-24 04:48:46 +00:00
Add the DB120 specific hints for the AR8327. Tested: * DB120
2014-02-26 01:32:27 +00:00
# AR8327_PAD_MAC_RGMII
hint.arswitch.0.pad.0.mode=6
hint.arswitch.0.pad.0.txclk_delay_en=1
hint.arswitch.0.pad.0.rxclk_delay_en=1
# AR8327_CLK_DELAY_SEL1
hint.arswitch.0.pad.0.txclk_delay_sel=1
# AR8327_CLK_DELAY_SEL2
hint.arswitch.0.pad.0.rxclk_delay_sel=2
Add the AR8327 bits to the DB120 config file. There's plenty of hints that I haven't yet fleshed out and are hardcoded in arswitch_8327.c. They're listed here (from OpenWRT) for completeness. This is enough to get the thing up, running and pinging. Note that the mdiobus for the on-switch switch changes - the AR8327 probes first, which exposes mdio1, and thus the arge1 mdiobus will probe and attach as mdio2. That is what the AR9344 on-chip switch has to attach to. Tested: * Qualcomm Atheros DB120
2014-02-24 04:48:46 +00:00
Add the DB120 specific hints for the AR8327. Tested: * DB120
2014-02-26 01:32:27 +00:00
# XXX there's no LED management just yet!
hint.arswitch.0.led.ctrl0=0x00000000
hint.arswitch.0.led.ctrl1=0xc737c737
hint.arswitch.0.led.ctrl2=0x00000000
hint.arswitch.0.led.ctrl3=0x00c30c00
hint.arswitch.0.led.open_drain=1
Add the AR8327 bits to the DB120 config file. There's plenty of hints that I haven't yet fleshed out and are hardcoded in arswitch_8327.c. They're listed here (from OpenWRT) for completeness. This is enough to get the thing up, running and pinging. Note that the mdiobus for the on-switch switch changes - the AR8327 probes first, which exposes mdio1, and thus the arge1 mdiobus will probe and attach as mdio2. That is what the AR9344 on-chip switch has to attach to. Tested: * Qualcomm Atheros DB120
2014-02-24 04:48:46 +00:00
Add the DB120 specific hints for the AR8327. Tested: * DB120
2014-02-26 01:32:27 +00:00
# force_link=1 is required for the rest of the parameters
# to be configured.
hint.arswitch.0.port.0.force_link=1
hint.arswitch.0.port.0.speed=1000
hint.arswitch.0.port.0.duplex=1
hint.arswitch.0.port.0.txpause=1
hint.arswitch.0.port.0.rxpause=1
Now that all of the on-chip switch and basic platform support is updated, we can now add all the hardware bits for the DB120. * arge0/argemdio0 is hooked up to an AR8327 switch - which there's currently no support for. However, the bootloader on this board does set it up as a basic switch so we can at least _use_ it ourselves. So we should at least configure the arge0 side of things, including the GMAC register. * .. the GMAC config peels off arge0 from the internal switch and exposes it as an RGMII to said AR8327. * arge1/argemdio1 are hooked up to an internal 10/100 switch. So, that also needs configuring. * Add support for the NOR flash layout. * Add support for the wifi (which works, with bugs, but it works.) What's missing! * No GPIO stuff yet! * No sound (I2S) and no NAND flash support yet, sorry! * The normal DB120 has an external AR95xx wifi chip on PCIe but with the actual calibration data in the NOR flash. My DB120 has been modified to let me use the PCIe slot as a normal PCIe slot. I'll add the "default" settings later when I have access to a non-modified one. * Other stuff, like why the wifi unit gets upset and spits out stuck beacons and interrupt storms everywhere. Sigh. Tested: * DB120 board - AR9344 (mips74k SoC) booting off of SPI flash into multi-user mode.
2013-10-16 04:22:26 +00:00
# XXX OpenWRT DB120 BSP doesn't have media/duplex set?
hint.arge.0.phymask=0x0
hint.arge.0.media=1000
hint.arge.0.fduplex=1
hint.arge.0.miimode=3 # RGMII
hint.arge.0.pll_1000=0x06000000
* Add ethernet MAC configuration from the EEPROM for arge0/arge1 * The AR9344 switch has 5 ports in use, not four. Tested: * DB120 reference board
2014-03-16 02:34:33 +00:00
# MAC for arge0 is the first 6 bytes of the ART
hint.arge.0.eeprommac=0x1f7f0000
Now that all of the on-chip switch and basic platform support is updated, we can now add all the hardware bits for the DB120. * arge0/argemdio0 is hooked up to an AR8327 switch - which there's currently no support for. However, the bootloader on this board does set it up as a basic switch so we can at least _use_ it ourselves. So we should at least configure the arge0 side of things, including the GMAC register. * .. the GMAC config peels off arge0 from the internal switch and exposes it as an RGMII to said AR8327. * arge1/argemdio1 are hooked up to an internal 10/100 switch. So, that also needs configuring. * Add support for the NOR flash layout. * Add support for the wifi (which works, with bugs, but it works.) What's missing! * No GPIO stuff yet! * No sound (I2S) and no NAND flash support yet, sorry! * The normal DB120 has an external AR95xx wifi chip on PCIe but with the actual calibration data in the NOR flash. My DB120 has been modified to let me use the PCIe slot as a normal PCIe slot. I'll add the "default" settings later when I have access to a non-modified one. * Other stuff, like why the wifi unit gets upset and spits out stuck beacons and interrupt storms everywhere. Sigh. Tested: * DB120 board - AR9344 (mips74k SoC) booting off of SPI flash into multi-user mode.
2013-10-16 04:22:26 +00:00
# mdiobus1 on arge1
hint.argemdio.1.at="nexus0"
hint.argemdio.1.maddr=0x1a000000
hint.argemdio.1.msize=0x1000
hint.argemdio.1.order=0
# Embedded switch on the AR9344
Add the AR8327 bits to the DB120 config file. There's plenty of hints that I haven't yet fleshed out and are hardcoded in arswitch_8327.c. They're listed here (from OpenWRT) for completeness. This is enough to get the thing up, running and pinging. Note that the mdiobus for the on-switch switch changes - the AR8327 probes first, which exposes mdio1, and thus the arge1 mdiobus will probe and attach as mdio2. That is what the AR9344 on-chip switch has to attach to. Tested: * Qualcomm Atheros DB120
2014-02-24 04:48:46 +00:00
# mdio1 is actually created as the AR8327 internal bus; so
# this pops up as mdio2.
hint.arswitch.1.at="mdio2"
Now that all of the on-chip switch and basic platform support is updated, we can now add all the hardware bits for the DB120. * arge0/argemdio0 is hooked up to an AR8327 switch - which there's currently no support for. However, the bootloader on this board does set it up as a basic switch so we can at least _use_ it ourselves. So we should at least configure the arge0 side of things, including the GMAC register. * .. the GMAC config peels off arge0 from the internal switch and exposes it as an RGMII to said AR8327. * arge1/argemdio1 are hooked up to an internal 10/100 switch. So, that also needs configuring. * Add support for the NOR flash layout. * Add support for the wifi (which works, with bugs, but it works.) What's missing! * No GPIO stuff yet! * No sound (I2S) and no NAND flash support yet, sorry! * The normal DB120 has an external AR95xx wifi chip on PCIe but with the actual calibration data in the NOR flash. My DB120 has been modified to let me use the PCIe slot as a normal PCIe slot. I'll add the "default" settings later when I have access to a non-modified one. * Other stuff, like why the wifi unit gets upset and spits out stuck beacons and interrupt storms everywhere. Sigh. Tested: * DB120 board - AR9344 (mips74k SoC) booting off of SPI flash into multi-user mode.
2013-10-16 04:22:26 +00:00
hint.arswitch.1.is_7240=0
hint.arswitch.1.is_9340=1
* Add ethernet MAC configuration from the EEPROM for arge0/arge1 * The AR9344 switch has 5 ports in use, not four. Tested: * DB120 reference board
2014-03-16 02:34:33 +00:00
hint.arswitch.1.numphys=5
Now that all of the on-chip switch and basic platform support is updated, we can now add all the hardware bits for the DB120. * arge0/argemdio0 is hooked up to an AR8327 switch - which there's currently no support for. However, the bootloader on this board does set it up as a basic switch so we can at least _use_ it ourselves. So we should at least configure the arge0 side of things, including the GMAC register. * .. the GMAC config peels off arge0 from the internal switch and exposes it as an RGMII to said AR8327. * arge1/argemdio1 are hooked up to an internal 10/100 switch. So, that also needs configuring. * Add support for the NOR flash layout. * Add support for the wifi (which works, with bugs, but it works.) What's missing! * No GPIO stuff yet! * No sound (I2S) and no NAND flash support yet, sorry! * The normal DB120 has an external AR95xx wifi chip on PCIe but with the actual calibration data in the NOR flash. My DB120 has been modified to let me use the PCIe slot as a normal PCIe slot. I'll add the "default" settings later when I have access to a non-modified one. * Other stuff, like why the wifi unit gets upset and spits out stuck beacons and interrupt storms everywhere. Sigh. Tested: * DB120 board - AR9344 (mips74k SoC) booting off of SPI flash into multi-user mode.
2013-10-16 04:22:26 +00:00
hint.arswitch.1.phy4cpu=0 # phy 4 is not a "CPU port" PHY here
hint.arswitch.1.is_rgmii=0
hint.arswitch.1.is_gmii=1 # arge1 <-> switch PHY is GMII
# arge1 - lock up to 1000/full
hint.arge.1.phymask=0x0 # Nothing attached here (XXX?)
hint.arge.1.media=1000
hint.arge.1.fduplex=1
hint.arge.1.miimode=1 # GMII
* Add ethernet MAC configuration from the EEPROM for arge0/arge1 * The AR9344 switch has 5 ports in use, not four. Tested: * DB120 reference board
2014-03-16 02:34:33 +00:00
# MAC for arge1 is the second 6 bytes of the ART
hint.arge.1.eeprommac=0x1f7f0006
Add the ath0 EEPROM hints required to detect the on-chip wifi. This allows the on-chip wifi to work; however it's not yet fully tested. ath0: Vendor=0x168c, Device=0x0031 ath0: Vendor=0x168c, Device=0x0031 ath0: <Atheros AR934x> at mem 0x18100000-0x1811ffff irq 0 on nexus0 ... ath0: [HT] enabling HT modes ath0: [HT] enabling short-GI in 20MHz mode ath0: [HT] 1 stream STBC receive enabled ath0: [HT] 1 stream STBC transmit enabled ath0: [HT] 2 RX streams; 2 TX streams Tested: * DB120 development board
2014-02-14 04:03:17 +00:00
# ath0: Where the ART is - last 64k in the flash
hint.ath.0.eepromaddr=0x1fff0000
hint.ath.0.eepromsize=16384
# ath1: it's different; it's a PCIe attached device, so
# we instead need to teach the PCIe bridge code about it
# (ie, the 'early pci fixup' stuff that programs the PCIe
# host registers on the NIC) and then we teach ath where
# to find it.
Enable use of the PCIe connected wifi on the DB120 (AR9344) board. The on-board NIC is an 3x3 AR9380 with 5GHz only. * enable pci code in AR9344_BASE * enable ath_pci and the firmware loading bits in DB120 * add in the relevant hints in DB120.hints to inform the probe/attach code where the PCIe fixup data is for the onboard chip. This is only relevant for a default development board. I also have a DB120 with the on-board PCIe wifi NIC disabled and it's exposed as a real PCIe slot (to put normal PCIe NICs in); the fixup code will need to be disabled to make this work correctly. Tested: * DB120
2014-02-14 05:25:15 +00:00
# ath1 hint - pcie slot 0
hint.pcib.0.bus.0.0.0.ath_fixup_addr=0x1fff4000
hint.pcib.0.bus.0.0.0.ath_fixup_size=16384
# ath0 - eeprom comes from here
hint.ath.1.eeprom_firmware="pcib.0.bus.0.0.0.eeprom_firmware"
Now that all of the on-chip switch and basic platform support is updated, we can now add all the hardware bits for the DB120. * arge0/argemdio0 is hooked up to an AR8327 switch - which there's currently no support for. However, the bootloader on this board does set it up as a basic switch so we can at least _use_ it ourselves. So we should at least configure the arge0 side of things, including the GMAC register. * .. the GMAC config peels off arge0 from the internal switch and exposes it as an RGMII to said AR8327. * arge1/argemdio1 are hooked up to an internal 10/100 switch. So, that also needs configuring. * Add support for the NOR flash layout. * Add support for the wifi (which works, with bugs, but it works.) What's missing! * No GPIO stuff yet! * No sound (I2S) and no NAND flash support yet, sorry! * The normal DB120 has an external AR95xx wifi chip on PCIe but with the actual calibration data in the NOR flash. My DB120 has been modified to let me use the PCIe slot as a normal PCIe slot. I'll add the "default" settings later when I have access to a non-modified one. * Other stuff, like why the wifi unit gets upset and spits out stuck beacons and interrupt storms everywhere. Sigh. Tested: * DB120 board - AR9344 (mips74k SoC) booting off of SPI flash into multi-user mode.
2013-10-16 04:22:26 +00:00
# flash layout:
#
# bootargs=console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),64k(mib0),64k(ART)
# 256KiB u-boot
hint.map.0.at="flash/spi0"
hint.map.0.start=0x00000000
hint.map.0.end=0x00040000 # 256k u-boot
hint.map.0.name="u-boot"
hint.map.0.readonly=1
# 64KiB u-boot-env
hint.map.1.at="flash/spi0"
hint.map.1.start=0x00040000
hint.map.1.end=0x00050000 # 64k u-boot-env
hint.map.1.name="u-boot-env"
hint.map.1.readonly=1
# 6336KiB rootfs
hint.map.2.at="flash/spi0"
hint.map.2.start=0x00050000
hint.map.2.end=0x00680000 # 6336k rootfs
hint.map.2.name="rootfs"
hint.map.2.readonly=1
# 1344KiB uImage
hint.map.3.at="flash/spi0"
hint.map.3.start=0x00680000
hint.map.3.end=0x007d0000 # 1408k uImage, 64k off the end..
hint.map.3.name="uImage"
hint.map.3.readonly=1
# 64KiB cfg
hint.map.4.at="flash/spi0"
hint.map.4.start=0x007d0000
hint.map.4.end=0x007e0000
hint.map.4.name="cfg"
hint.map.4.readonly=0
# 64KiB mib0
hint.map.5.at="flash/spi0"
hint.map.5.start=0x007e0000
hint.map.5.end=0x007f0000 # 64k mib0
hint.map.5.name="mib0"
hint.map.5.readonly=1
# 64KiB ART
hint.map.6.at="flash/spi0"
hint.map.6.start=0x007f0000
hint.map.6.end=0x00800000 # 64k ART
hint.map.6.name="ART"
hint.map.6.readonly=1
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