2011-03-21 09:58:24 +00:00
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/*
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2014-09-23 12:37:01 +00:00
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* Copyright (c) 2007, 2014 Mellanox Technologies. All rights reserved.
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2011-03-21 09:58:24 +00:00
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*/
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2014-10-15 13:40:29 +00:00
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#include <linux/page.h>
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2011-03-21 09:58:24 +00:00
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#include <linux/mlx4/cq.h>
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2014-09-23 12:37:01 +00:00
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#include <linux/slab.h>
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2011-03-21 09:58:24 +00:00
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#include <linux/mlx4/qp.h>
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2014-09-23 12:37:01 +00:00
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#include <linux/if_vlan.h>
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2011-03-21 09:58:24 +00:00
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#include <linux/vmalloc.h>
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2014-09-23 12:37:01 +00:00
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#include <linux/moduleparam.h>
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2011-03-21 09:58:24 +00:00
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#include <netinet/in_systm.h>
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#include <netinet/in.h>
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#include <netinet/if_ether.h>
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#include <netinet/ip.h>
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#include <netinet/ip6.h>
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#include <netinet/tcp.h>
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#include <netinet/tcp_lro.h>
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#include <netinet/udp.h>
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2014-09-23 12:37:01 +00:00
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#include "mlx4_en.h"
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2011-03-21 09:58:24 +00:00
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enum {
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MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
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MAX_BF = 256,
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2014-09-23 12:37:01 +00:00
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MIN_PKT_LEN = 17,
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2011-03-21 09:58:24 +00:00
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};
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2014-09-23 12:37:01 +00:00
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static int inline_thold __read_mostly = MAX_INLINE;
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2011-03-21 09:58:24 +00:00
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2014-09-23 12:37:01 +00:00
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module_param_named(inline_thold, inline_thold, uint, 0444);
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MODULE_PARM_DESC(inline_thold, "threshold for using inline data");
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2011-03-21 09:58:24 +00:00
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int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
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2014-09-23 12:37:01 +00:00
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struct mlx4_en_tx_ring **pring, u32 size,
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u16 stride, int node, int queue_idx)
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2011-03-21 09:58:24 +00:00
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{
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struct mlx4_en_dev *mdev = priv->mdev;
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2014-09-23 12:37:01 +00:00
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struct mlx4_en_tx_ring *ring;
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2015-12-03 14:56:17 +00:00
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uint32_t x;
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2011-03-21 09:58:24 +00:00
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int tmp;
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int err;
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2014-09-23 12:37:01 +00:00
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ring = kzalloc_node(sizeof(struct mlx4_en_tx_ring), GFP_KERNEL, node);
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if (!ring) {
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ring = kzalloc(sizeof(struct mlx4_en_tx_ring), GFP_KERNEL);
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if (!ring) {
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en_err(priv, "Failed allocating TX ring\n");
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return -ENOMEM;
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}
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}
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2015-12-03 14:56:17 +00:00
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/* Create DMA descriptor TAG */
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if ((err = -bus_dma_tag_create(
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bus_get_dma_tag(mdev->pdev->dev.bsddev),
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1, /* any alignment */
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0, /* no boundary */
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BUS_SPACE_MAXADDR, /* lowaddr */
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BUS_SPACE_MAXADDR, /* highaddr */
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NULL, NULL, /* filter, filterarg */
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MLX4_EN_TX_MAX_PAYLOAD_SIZE, /* maxsize */
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MLX4_EN_TX_MAX_MBUF_FRAGS, /* nsegments */
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MLX4_EN_TX_MAX_MBUF_SIZE, /* maxsegsize */
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0, /* flags */
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NULL, NULL, /* lockfunc, lockfuncarg */
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&ring->dma_tag)))
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goto done;
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2011-03-21 09:58:24 +00:00
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ring->size = size;
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ring->size_mask = size - 1;
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ring->stride = stride;
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2015-12-03 14:56:17 +00:00
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ring->inline_thold = MAX(MIN_PKT_LEN, MIN(inline_thold, MAX_INLINE));
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2011-03-21 09:58:24 +00:00
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mtx_init(&ring->tx_lock.m, "mlx4 tx", NULL, MTX_DEF);
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mtx_init(&ring->comp_lock.m, "mlx4 comp", NULL, MTX_DEF);
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/* Allocate the buf ring */
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ring->br = buf_ring_alloc(MLX4_EN_DEF_TX_QUEUE_SIZE, M_DEVBUF,
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2014-09-23 12:37:01 +00:00
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M_WAITOK, &ring->tx_lock.m);
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2011-03-21 09:58:24 +00:00
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if (ring->br == NULL) {
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en_err(priv, "Failed allocating tx_info ring\n");
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2015-12-03 14:56:17 +00:00
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err = -ENOMEM;
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goto err_free_dma_tag;
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2011-03-21 09:58:24 +00:00
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}
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tmp = size * sizeof(struct mlx4_en_tx_info);
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2015-12-03 14:56:17 +00:00
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ring->tx_info = kzalloc_node(tmp, GFP_KERNEL, node);
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2011-03-21 09:58:24 +00:00
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if (!ring->tx_info) {
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2015-12-03 14:56:17 +00:00
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ring->tx_info = kzalloc(tmp, GFP_KERNEL);
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2014-09-23 12:37:01 +00:00
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if (!ring->tx_info) {
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err = -ENOMEM;
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goto err_ring;
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}
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2011-03-21 09:58:24 +00:00
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}
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2014-09-23 12:37:01 +00:00
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2015-12-03 14:56:17 +00:00
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/* Create DMA descriptor MAPs */
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for (x = 0; x != size; x++) {
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err = -bus_dmamap_create(ring->dma_tag, 0,
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&ring->tx_info[x].dma_map);
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if (err != 0) {
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while (x--) {
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bus_dmamap_destroy(ring->dma_tag,
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ring->tx_info[x].dma_map);
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}
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2014-09-23 12:37:01 +00:00
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goto err_info;
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}
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2011-03-21 09:58:24 +00:00
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}
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2015-12-03 14:56:17 +00:00
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en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n",
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ring->tx_info, tmp);
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2011-03-21 09:58:24 +00:00
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ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE);
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2014-09-23 12:37:01 +00:00
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/* Allocate HW buffers on provided NUMA node */
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2011-03-21 09:58:24 +00:00
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err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size,
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2 * PAGE_SIZE);
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if (err) {
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en_err(priv, "Failed allocating hwq resources\n");
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2015-12-03 14:56:17 +00:00
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goto err_dma_map;
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2011-03-21 09:58:24 +00:00
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}
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err = mlx4_en_map_buffer(&ring->wqres.buf);
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if (err) {
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en_err(priv, "Failed to map TX buffer\n");
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goto err_hwq_res;
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}
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ring->buf = ring->wqres.buf.direct.buf;
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en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d "
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"buf_size:%d dma:%llx\n", ring, ring->buf, ring->size,
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ring->buf_size, (unsigned long long) ring->wqres.buf.direct.map);
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2014-09-23 12:37:01 +00:00
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err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn,
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MLX4_RESERVE_BF_QP);
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2011-03-21 09:58:24 +00:00
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if (err) {
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2014-09-23 12:37:01 +00:00
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en_err(priv, "failed reserving qp for TX ring\n");
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2011-03-21 09:58:24 +00:00
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goto err_map;
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}
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err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp);
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if (err) {
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en_err(priv, "Failed allocating qp %d\n", ring->qpn);
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goto err_reserve;
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}
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ring->qp.event = mlx4_en_sqp_event;
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2014-09-23 12:37:01 +00:00
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err = mlx4_bf_alloc(mdev->dev, &ring->bf, node);
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2011-03-21 09:58:24 +00:00
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if (err) {
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2014-09-23 12:37:01 +00:00
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en_dbg(DRV, priv, "working without blueflame (%d)", err);
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2011-03-21 09:58:24 +00:00
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ring->bf.uar = &mdev->priv_uar;
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ring->bf.uar->map = mdev->uar_map;
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ring->bf_enabled = false;
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} else
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ring->bf_enabled = true;
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2014-09-23 12:37:01 +00:00
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ring->queue_index = queue_idx;
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if (queue_idx < priv->num_tx_rings_p_up )
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CPU_SET(queue_idx, &ring->affinity_mask);
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2011-03-21 09:58:24 +00:00
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2014-09-23 12:37:01 +00:00
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*pring = ring;
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2011-03-21 09:58:24 +00:00
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return 0;
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err_reserve:
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mlx4_qp_release_range(mdev->dev, ring->qpn, 1);
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err_map:
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mlx4_en_unmap_buffer(&ring->wqres.buf);
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err_hwq_res:
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mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
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2015-12-03 14:56:17 +00:00
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err_dma_map:
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for (x = 0; x != size; x++)
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bus_dmamap_destroy(ring->dma_tag, ring->tx_info[x].dma_map);
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2014-09-23 12:37:01 +00:00
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err_info:
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vfree(ring->tx_info);
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err_ring:
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2011-03-21 09:58:24 +00:00
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buf_ring_free(ring->br, M_DEVBUF);
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2015-12-03 14:56:17 +00:00
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err_free_dma_tag:
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bus_dma_tag_destroy(ring->dma_tag);
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done:
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2014-09-23 12:37:01 +00:00
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kfree(ring);
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2011-03-21 09:58:24 +00:00
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return err;
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}
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void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
|
2014-09-23 12:37:01 +00:00
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struct mlx4_en_tx_ring **pring)
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2011-03-21 09:58:24 +00:00
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{
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struct mlx4_en_dev *mdev = priv->mdev;
|
2014-09-23 12:37:01 +00:00
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struct mlx4_en_tx_ring *ring = *pring;
|
2015-12-03 14:56:17 +00:00
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uint32_t x;
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2011-03-21 09:58:24 +00:00
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en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn);
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buf_ring_free(ring->br, M_DEVBUF);
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if (ring->bf_enabled)
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mlx4_bf_free(mdev->dev, &ring->bf);
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mlx4_qp_remove(mdev->dev, &ring->qp);
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mlx4_qp_free(mdev->dev, &ring->qp);
|
2014-09-23 12:37:01 +00:00
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mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1);
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2011-03-21 09:58:24 +00:00
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mlx4_en_unmap_buffer(&ring->wqres.buf);
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mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
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2015-12-03 14:56:17 +00:00
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for (x = 0; x != ring->size; x++)
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bus_dmamap_destroy(ring->dma_tag, ring->tx_info[x].dma_map);
|
2014-09-23 12:37:01 +00:00
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vfree(ring->tx_info);
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2011-03-21 09:58:24 +00:00
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mtx_destroy(&ring->tx_lock.m);
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mtx_destroy(&ring->comp_lock.m);
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2015-12-03 14:56:17 +00:00
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bus_dma_tag_destroy(ring->dma_tag);
|
2014-09-23 12:37:01 +00:00
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kfree(ring);
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*pring = NULL;
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2011-03-21 09:58:24 +00:00
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}
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int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
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struct mlx4_en_tx_ring *ring,
|
2014-09-23 12:37:01 +00:00
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int cq, int user_prio)
|
2011-03-21 09:58:24 +00:00
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{
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struct mlx4_en_dev *mdev = priv->mdev;
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int err;
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ring->cqn = cq;
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ring->prod = 0;
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ring->cons = 0xffffffff;
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ring->last_nr_txbb = 1;
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ring->poll_cnt = 0;
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ring->blocked = 0;
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memset(ring->buf, 0, ring->buf_size);
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ring->qp_state = MLX4_QP_STATE_RST;
|
2014-09-23 12:37:01 +00:00
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ring->doorbell_qpn = ring->qp.qpn << 8;
|
2011-03-21 09:58:24 +00:00
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mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn,
|
2014-09-23 12:37:01 +00:00
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ring->cqn, user_prio, &ring->context);
|
2011-03-21 09:58:24 +00:00
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if (ring->bf_enabled)
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ring->context.usr_page = cpu_to_be32(ring->bf.uar->index);
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err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context,
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&ring->qp, &ring->qp_state);
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return err;
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}
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void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
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|
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struct mlx4_en_tx_ring *ring)
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|
|
{
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struct mlx4_en_dev *mdev = priv->mdev;
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mlx4_qp_modify(mdev->dev, NULL, ring->qp_state,
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MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp);
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}
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|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
static volatile struct mlx4_wqe_data_seg *
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|
|
mlx4_en_store_inline_lso_data(volatile struct mlx4_wqe_data_seg *dseg,
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|
|
struct mbuf *mb, int len, __be32 owner_bit)
|
2014-09-23 12:37:01 +00:00
|
|
|
{
|
2015-12-03 14:56:17 +00:00
|
|
|
uint8_t *inl = __DEVOLATILE(uint8_t *, dseg);
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|
/* copy data into place */
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|
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m_copydata(mb, 0, len, inl + 4);
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|
|
dseg += DIV_ROUND_UP(4 + len, DS_SIZE_ALIGNMENT);
|
|
|
|
return (dseg);
|
2014-09-23 12:37:01 +00:00
|
|
|
}
|
2011-03-21 09:58:24 +00:00
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
static void
|
|
|
|
mlx4_en_store_inline_lso_header(volatile struct mlx4_wqe_data_seg *dseg,
|
|
|
|
int len, __be32 owner_bit)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
mlx4_en_stamp_wqe(struct mlx4_en_priv *priv,
|
|
|
|
struct mlx4_en_tx_ring *ring, u32 index, u8 owner)
|
2011-03-21 09:58:24 +00:00
|
|
|
{
|
|
|
|
struct mlx4_en_tx_info *tx_info = &ring->tx_info[index];
|
2015-12-03 13:29:20 +00:00
|
|
|
struct mlx4_en_tx_desc *tx_desc = (struct mlx4_en_tx_desc *)
|
2015-12-03 14:56:17 +00:00
|
|
|
(ring->buf + (index * TXBB_SIZE));
|
|
|
|
volatile __be32 *ptr = (__be32 *)tx_desc;
|
|
|
|
const __be32 stamp = cpu_to_be32(STAMP_VAL |
|
|
|
|
((u32)owner << STAMP_SHIFT));
|
|
|
|
u32 i;
|
|
|
|
|
|
|
|
/* Stamp the freed descriptor */
|
|
|
|
for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; i += STAMP_STRIDE) {
|
|
|
|
*ptr = stamp;
|
|
|
|
ptr += STAMP_DWORDS;
|
|
|
|
}
|
|
|
|
}
|
2014-09-23 12:37:01 +00:00
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
static u32
|
|
|
|
mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
|
|
|
|
struct mlx4_en_tx_ring *ring, u32 index)
|
|
|
|
{
|
|
|
|
struct mlx4_en_tx_info *tx_info;
|
|
|
|
struct mbuf *mb;
|
2014-09-23 12:37:01 +00:00
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
tx_info = &ring->tx_info[index];
|
|
|
|
mb = tx_info->mb;
|
|
|
|
|
|
|
|
if (mb == NULL)
|
|
|
|
goto done;
|
|
|
|
|
|
|
|
bus_dmamap_sync(ring->dma_tag, tx_info->dma_map,
|
|
|
|
BUS_DMASYNC_POSTWRITE);
|
|
|
|
bus_dmamap_unload(ring->dma_tag, tx_info->dma_map);
|
2014-09-23 12:37:01 +00:00
|
|
|
|
|
|
|
m_freem(mb);
|
2015-12-03 14:56:17 +00:00
|
|
|
done:
|
|
|
|
return (tx_info->nr_txbb);
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring)
|
|
|
|
{
|
|
|
|
struct mlx4_en_priv *priv = netdev_priv(dev);
|
|
|
|
int cnt = 0;
|
|
|
|
|
|
|
|
/* Skip last polled descriptor */
|
|
|
|
ring->cons += ring->last_nr_txbb;
|
|
|
|
en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n",
|
|
|
|
ring->cons, ring->prod);
|
|
|
|
|
|
|
|
if ((u32) (ring->prod - ring->cons) > ring->size) {
|
2014-09-23 12:37:01 +00:00
|
|
|
en_warn(priv, "Tx consumer passed producer!\n");
|
2011-03-21 09:58:24 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
while (ring->cons != ring->prod) {
|
|
|
|
ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring,
|
2015-12-03 14:56:17 +00:00
|
|
|
ring->cons & ring->size_mask);
|
2011-03-21 09:58:24 +00:00
|
|
|
ring->cons += ring->last_nr_txbb;
|
|
|
|
cnt++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cnt)
|
|
|
|
en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt);
|
|
|
|
|
|
|
|
return cnt;
|
|
|
|
}
|
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
static bool
|
|
|
|
mlx4_en_tx_ring_is_full(struct mlx4_en_tx_ring *ring)
|
|
|
|
{
|
|
|
|
int wqs;
|
|
|
|
wqs = ring->size - (ring->prod - ring->cons);
|
|
|
|
return (wqs < (HEADROOM + (2 * MLX4_EN_TX_WQE_MAX_WQEBBS)));
|
|
|
|
}
|
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
static int mlx4_en_process_tx_cq(struct net_device *dev,
|
|
|
|
struct mlx4_en_cq *cq)
|
2011-03-21 09:58:24 +00:00
|
|
|
{
|
|
|
|
struct mlx4_en_priv *priv = netdev_priv(dev);
|
|
|
|
struct mlx4_cq *mcq = &cq->mcq;
|
2014-09-23 12:37:01 +00:00
|
|
|
struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring];
|
|
|
|
struct mlx4_cqe *cqe;
|
2011-03-21 09:58:24 +00:00
|
|
|
u16 index;
|
2014-09-23 12:37:01 +00:00
|
|
|
u16 new_index, ring_index, stamp_index;
|
2011-03-21 09:58:24 +00:00
|
|
|
u32 txbbs_skipped = 0;
|
2014-09-23 12:37:01 +00:00
|
|
|
u32 txbbs_stamp = 0;
|
|
|
|
u32 cons_index = mcq->cons_index;
|
|
|
|
int size = cq->size;
|
|
|
|
u32 size_mask = ring->size_mask;
|
|
|
|
struct mlx4_cqe *buf = cq->buf;
|
|
|
|
int factor = priv->cqe_factor;
|
2011-03-21 09:58:24 +00:00
|
|
|
|
|
|
|
if (!priv->port_up)
|
2014-09-23 12:37:01 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
index = cons_index & size_mask;
|
|
|
|
cqe = &buf[(index << factor) + factor];
|
|
|
|
ring_index = ring->cons & size_mask;
|
|
|
|
stamp_index = ring_index;
|
|
|
|
|
|
|
|
/* Process all completed CQEs */
|
|
|
|
while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
|
|
|
|
cons_index & size)) {
|
|
|
|
/*
|
|
|
|
* make sure we read the CQE after we read the
|
|
|
|
* ownership bit
|
|
|
|
*/
|
|
|
|
rmb();
|
|
|
|
|
|
|
|
if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
|
|
|
|
MLX4_CQE_OPCODE_ERROR)) {
|
|
|
|
en_err(priv, "CQE completed in error - vendor syndrom: 0x%x syndrom: 0x%x\n",
|
|
|
|
((struct mlx4_err_cqe *)cqe)->
|
|
|
|
vendor_err_syndrome,
|
|
|
|
((struct mlx4_err_cqe *)cqe)->syndrome);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Skip over last polled CQE */
|
|
|
|
new_index = be16_to_cpu(cqe->wqe_index) & size_mask;
|
2011-03-21 09:58:24 +00:00
|
|
|
|
|
|
|
do {
|
|
|
|
txbbs_skipped += ring->last_nr_txbb;
|
2014-09-23 12:37:01 +00:00
|
|
|
ring_index = (ring_index + ring->last_nr_txbb) & size_mask;
|
|
|
|
/* free next descriptor */
|
2011-03-21 09:58:24 +00:00
|
|
|
ring->last_nr_txbb = mlx4_en_free_tx_desc(
|
2015-12-03 14:56:17 +00:00
|
|
|
priv, ring, ring_index);
|
2014-09-23 12:37:01 +00:00
|
|
|
mlx4_en_stamp_wqe(priv, ring, stamp_index,
|
|
|
|
!!((ring->cons + txbbs_stamp) &
|
|
|
|
ring->size));
|
|
|
|
stamp_index = ring_index;
|
|
|
|
txbbs_stamp = txbbs_skipped;
|
|
|
|
} while (ring_index != new_index);
|
|
|
|
|
|
|
|
++cons_index;
|
|
|
|
index = cons_index & size_mask;
|
|
|
|
cqe = &buf[(index << factor) + factor];
|
|
|
|
}
|
2011-03-21 09:58:24 +00:00
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* To prevent CQ overflow we first update CQ consumer and only then
|
|
|
|
* the ring consumer.
|
|
|
|
*/
|
2014-09-23 12:37:01 +00:00
|
|
|
mcq->cons_index = cons_index;
|
2011-03-21 09:58:24 +00:00
|
|
|
mlx4_cq_set_ci(mcq);
|
|
|
|
wmb();
|
|
|
|
ring->cons += txbbs_skipped;
|
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
/* Wakeup Tx queue if it was stopped and ring is not full */
|
2015-12-03 14:56:17 +00:00
|
|
|
if (unlikely(ring->blocked) && !mlx4_en_tx_ring_is_full(ring)) {
|
2014-09-23 12:37:01 +00:00
|
|
|
ring->blocked = 0;
|
|
|
|
if (atomic_fetchadd_int(&priv->blocked, -1) == 1)
|
|
|
|
atomic_clear_int(&dev->if_drv_flags ,IFF_DRV_OACTIVE);
|
|
|
|
ring->wake_queue++;
|
|
|
|
priv->port_stats.wake_queue++;
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
2015-12-03 14:56:17 +00:00
|
|
|
return (0);
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void mlx4_en_tx_irq(struct mlx4_cq *mcq)
|
|
|
|
{
|
|
|
|
struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
|
|
|
|
struct mlx4_en_priv *priv = netdev_priv(cq->dev);
|
2014-09-23 12:37:01 +00:00
|
|
|
struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring];
|
2011-03-21 09:58:24 +00:00
|
|
|
|
|
|
|
if (!spin_trylock(&ring->comp_lock))
|
|
|
|
return;
|
|
|
|
mlx4_en_process_tx_cq(cq->dev, cq);
|
|
|
|
mod_timer(&cq->timer, jiffies + 1);
|
|
|
|
spin_unlock(&ring->comp_lock);
|
|
|
|
}
|
|
|
|
|
|
|
|
void mlx4_en_poll_tx_cq(unsigned long data)
|
|
|
|
{
|
|
|
|
struct mlx4_en_cq *cq = (struct mlx4_en_cq *) data;
|
|
|
|
struct mlx4_en_priv *priv = netdev_priv(cq->dev);
|
2014-09-23 12:37:01 +00:00
|
|
|
struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring];
|
2011-03-21 09:58:24 +00:00
|
|
|
u32 inflight;
|
|
|
|
|
|
|
|
INC_PERF_COUNTER(priv->pstats.tx_poll);
|
|
|
|
|
|
|
|
if (!spin_trylock(&ring->comp_lock)) {
|
|
|
|
mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
mlx4_en_process_tx_cq(cq->dev, cq);
|
|
|
|
inflight = (u32) (ring->prod - ring->cons - ring->last_nr_txbb);
|
|
|
|
|
|
|
|
/* If there are still packets in flight and the timer has not already
|
|
|
|
* been scheduled by the Tx routine then schedule it here to guarantee
|
|
|
|
* completion processing of these packets */
|
|
|
|
if (inflight && priv->port_up)
|
|
|
|
mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
|
|
|
|
|
|
|
|
spin_unlock(&ring->comp_lock);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void mlx4_en_xmit_poll(struct mlx4_en_priv *priv, int tx_ind)
|
|
|
|
{
|
2014-09-23 12:37:01 +00:00
|
|
|
struct mlx4_en_cq *cq = priv->tx_cq[tx_ind];
|
|
|
|
struct mlx4_en_tx_ring *ring = priv->tx_ring[tx_ind];
|
2011-03-21 09:58:24 +00:00
|
|
|
|
|
|
|
/* If we don't have a pending timer, set one up to catch our recent
|
|
|
|
post in case the interface becomes idle */
|
|
|
|
if (!timer_pending(&cq->timer))
|
|
|
|
mod_timer(&cq->timer, jiffies + MLX4_EN_TX_POLL_TIMEOUT);
|
|
|
|
|
|
|
|
/* Poll the CQ every mlx4_en_TX_MODER_POLL packets */
|
|
|
|
if ((++ring->poll_cnt & (MLX4_EN_TX_POLL_MODER - 1)) == 0)
|
|
|
|
if (spin_trylock(&ring->comp_lock)) {
|
|
|
|
mlx4_en_process_tx_cq(priv->dev, cq);
|
|
|
|
spin_unlock(&ring->comp_lock);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
static u16
|
|
|
|
mlx4_en_get_inline_hdr_size(struct mlx4_en_tx_ring *ring, struct mbuf *mb)
|
2011-03-21 09:58:24 +00:00
|
|
|
{
|
2015-12-03 14:56:17 +00:00
|
|
|
u16 retval;
|
2011-03-21 09:58:24 +00:00
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
/* only copy from first fragment, if possible */
|
|
|
|
retval = MIN(ring->inline_thold, mb->m_len);
|
2011-03-21 09:58:24 +00:00
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
/* check for too little data */
|
|
|
|
if (unlikely(retval < MIN_PKT_LEN))
|
|
|
|
retval = MIN(ring->inline_thold, mb->m_pkthdr.len);
|
|
|
|
return (retval);
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
static int
|
|
|
|
mlx4_en_get_header_size(struct mbuf *mb)
|
2011-03-21 09:58:24 +00:00
|
|
|
{
|
2014-09-23 12:37:01 +00:00
|
|
|
struct ether_vlan_header *eh;
|
|
|
|
struct tcphdr *th;
|
|
|
|
struct ip *ip;
|
|
|
|
int ip_hlen, tcp_hlen;
|
|
|
|
struct ip6_hdr *ip6;
|
|
|
|
uint16_t eth_type;
|
|
|
|
int eth_hdr_len;
|
|
|
|
|
|
|
|
eh = mtod(mb, struct ether_vlan_header *);
|
|
|
|
if (mb->m_len < ETHER_HDR_LEN)
|
|
|
|
return (0);
|
|
|
|
if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
|
|
|
|
eth_type = ntohs(eh->evl_proto);
|
|
|
|
eth_hdr_len = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
|
|
|
|
} else {
|
|
|
|
eth_type = ntohs(eh->evl_encap_proto);
|
|
|
|
eth_hdr_len = ETHER_HDR_LEN;
|
|
|
|
}
|
|
|
|
if (mb->m_len < eth_hdr_len)
|
2011-03-21 09:58:24 +00:00
|
|
|
return (0);
|
2014-09-23 12:37:01 +00:00
|
|
|
switch (eth_type) {
|
|
|
|
case ETHERTYPE_IP:
|
|
|
|
ip = (struct ip *)(mb->m_data + eth_hdr_len);
|
|
|
|
if (mb->m_len < eth_hdr_len + sizeof(*ip))
|
|
|
|
return (0);
|
|
|
|
if (ip->ip_p != IPPROTO_TCP)
|
|
|
|
return (0);
|
|
|
|
ip_hlen = ip->ip_hl << 2;
|
|
|
|
eth_hdr_len += ip_hlen;
|
|
|
|
break;
|
|
|
|
case ETHERTYPE_IPV6:
|
|
|
|
ip6 = (struct ip6_hdr *)(mb->m_data + eth_hdr_len);
|
|
|
|
if (mb->m_len < eth_hdr_len + sizeof(*ip6))
|
|
|
|
return (0);
|
|
|
|
if (ip6->ip6_nxt != IPPROTO_TCP)
|
|
|
|
return (0);
|
|
|
|
eth_hdr_len += sizeof(*ip6);
|
|
|
|
break;
|
|
|
|
default:
|
2011-03-21 09:58:24 +00:00
|
|
|
return (0);
|
2014-09-23 12:37:01 +00:00
|
|
|
}
|
|
|
|
if (mb->m_len < eth_hdr_len + sizeof(*th))
|
2011-03-21 09:58:24 +00:00
|
|
|
return (0);
|
2014-09-23 12:37:01 +00:00
|
|
|
th = (struct tcphdr *)(mb->m_data + eth_hdr_len);
|
2011-03-21 09:58:24 +00:00
|
|
|
tcp_hlen = th->th_off << 2;
|
2014-09-23 12:37:01 +00:00
|
|
|
eth_hdr_len += tcp_hlen;
|
|
|
|
if (mb->m_len < eth_hdr_len)
|
2011-03-21 09:58:24 +00:00
|
|
|
return (0);
|
2014-09-23 12:37:01 +00:00
|
|
|
return (eth_hdr_len);
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
static volatile struct mlx4_wqe_data_seg *
|
|
|
|
mlx4_en_store_inline_data(volatile struct mlx4_wqe_data_seg *dseg,
|
|
|
|
struct mbuf *mb, int len, __be32 owner_bit)
|
2011-03-21 09:58:24 +00:00
|
|
|
{
|
2015-12-03 14:56:17 +00:00
|
|
|
uint8_t *inl = __DEVOLATILE(uint8_t *, dseg);
|
|
|
|
const int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - 4;
|
|
|
|
|
|
|
|
if (unlikely(len < MIN_PKT_LEN)) {
|
|
|
|
m_copydata(mb, 0, len, inl + 4);
|
|
|
|
memset(inl + 4 + len, 0, MIN_PKT_LEN - len);
|
|
|
|
dseg += DIV_ROUND_UP(4 + MIN_PKT_LEN, DS_SIZE_ALIGNMENT);
|
|
|
|
} else if (len <= spc) {
|
|
|
|
m_copydata(mb, 0, len, inl + 4);
|
|
|
|
dseg += DIV_ROUND_UP(4 + len, DS_SIZE_ALIGNMENT);
|
|
|
|
} else {
|
|
|
|
m_copydata(mb, 0, spc, inl + 4);
|
|
|
|
m_copydata(mb, spc, len - spc, inl + 8 + spc);
|
|
|
|
dseg += DIV_ROUND_UP(8 + len, DS_SIZE_ALIGNMENT);
|
|
|
|
}
|
|
|
|
return (dseg);
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
static void
|
|
|
|
mlx4_en_store_inline_header(volatile struct mlx4_wqe_data_seg *dseg,
|
|
|
|
int len, __be32 owner_bit)
|
2011-03-21 09:58:24 +00:00
|
|
|
{
|
2015-12-03 14:56:17 +00:00
|
|
|
uint8_t *inl = __DEVOLATILE(uint8_t *, dseg);
|
|
|
|
const int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - 4;
|
|
|
|
|
|
|
|
if (unlikely(len < MIN_PKT_LEN)) {
|
|
|
|
*(volatile uint32_t *)inl =
|
|
|
|
SET_BYTE_COUNT((1 << 31) | MIN_PKT_LEN);
|
|
|
|
} else if (len <= spc) {
|
|
|
|
*(volatile uint32_t *)inl =
|
|
|
|
SET_BYTE_COUNT((1 << 31) | len);
|
2011-03-21 09:58:24 +00:00
|
|
|
} else {
|
2015-12-03 14:56:17 +00:00
|
|
|
*(volatile uint32_t *)(inl + 4 + spc) =
|
|
|
|
SET_BYTE_COUNT((1 << 31) | (len - spc));
|
2011-03-21 09:58:24 +00:00
|
|
|
wmb();
|
2015-12-03 14:56:17 +00:00
|
|
|
*(volatile uint32_t *)inl =
|
|
|
|
SET_BYTE_COUNT((1 << 31) | spc);
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-03-11 16:02:24 +00:00
|
|
|
static uint32_t hashrandom;
|
2014-09-23 12:37:01 +00:00
|
|
|
static void hashrandom_init(void *arg)
|
|
|
|
{
|
2015-08-04 09:45:10 +00:00
|
|
|
/*
|
|
|
|
* It is assumed that the random subsystem has been
|
|
|
|
* initialized when this function is called:
|
|
|
|
*/
|
2015-03-11 16:02:24 +00:00
|
|
|
hashrandom = m_ether_tcpip_hash_init();
|
2014-09-23 12:37:01 +00:00
|
|
|
}
|
2015-08-04 09:45:10 +00:00
|
|
|
SYSINIT(hashrandom_init, SI_SUB_RANDOM, SI_ORDER_ANY, &hashrandom_init, NULL);
|
2014-09-23 12:37:01 +00:00
|
|
|
|
2011-03-21 09:58:24 +00:00
|
|
|
u16 mlx4_en_select_queue(struct net_device *dev, struct mbuf *mb)
|
|
|
|
{
|
|
|
|
struct mlx4_en_priv *priv = netdev_priv(dev);
|
2014-09-23 12:37:01 +00:00
|
|
|
u32 rings_p_up = priv->num_tx_rings_p_up;
|
|
|
|
u32 up = 0;
|
|
|
|
u32 queue_index;
|
2011-03-21 09:58:24 +00:00
|
|
|
|
2015-03-04 09:30:03 +00:00
|
|
|
#if (MLX4_EN_NUM_UP > 1)
|
2011-03-21 09:58:24 +00:00
|
|
|
/* Obtain VLAN information if present */
|
|
|
|
if (mb->m_flags & M_VLANTAG) {
|
2015-03-04 09:30:03 +00:00
|
|
|
u32 vlan_tag = mb->m_pkthdr.ether_vtag;
|
|
|
|
up = (vlan_tag >> 13) % MLX4_EN_NUM_UP;
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
2015-03-04 09:30:03 +00:00
|
|
|
#endif
|
2015-12-03 13:29:20 +00:00
|
|
|
queue_index = m_ether_tcpip_hash(MBUF_HASHFLAG_L3 | MBUF_HASHFLAG_L4, mb, hashrandom);
|
2011-03-21 09:58:24 +00:00
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
return ((queue_index % rings_p_up) + (up * rings_p_up));
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
|
|
|
|
2015-12-03 13:29:20 +00:00
|
|
|
static void mlx4_bf_copy(void __iomem *dst, volatile unsigned long *src, unsigned bytecnt)
|
2011-03-21 09:58:24 +00:00
|
|
|
{
|
2015-12-03 13:29:20 +00:00
|
|
|
__iowrite64_copy(dst, __DEVOLATILE(void *, src), bytecnt / 8);
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
static u64 mlx4_en_mac_to_u64(u8 *addr)
|
|
|
|
{
|
|
|
|
u64 mac = 0;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < ETHER_ADDR_LEN; i++) {
|
|
|
|
mac <<= 8;
|
|
|
|
mac |= addr[i];
|
|
|
|
}
|
|
|
|
return mac;
|
|
|
|
}
|
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
static int mlx4_en_xmit(struct mlx4_en_priv *priv, int tx_ind, struct mbuf **mbp)
|
2011-03-21 09:58:24 +00:00
|
|
|
{
|
2015-12-03 14:56:17 +00:00
|
|
|
enum {
|
|
|
|
DS_FACT = TXBB_SIZE / DS_SIZE_ALIGNMENT,
|
|
|
|
CTRL_FLAGS = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE |
|
|
|
|
MLX4_WQE_CTRL_SOLICITED),
|
|
|
|
};
|
|
|
|
bus_dma_segment_t segs[MLX4_EN_TX_MAX_MBUF_FRAGS];
|
|
|
|
volatile struct mlx4_wqe_data_seg *dseg;
|
|
|
|
volatile struct mlx4_wqe_data_seg *dseg_inline;
|
|
|
|
volatile struct mlx4_en_tx_desc *tx_desc;
|
|
|
|
struct mlx4_en_tx_ring *ring = priv->tx_ring[tx_ind];
|
|
|
|
struct ifnet *ifp = priv->dev;
|
2011-03-21 09:58:24 +00:00
|
|
|
struct mlx4_en_tx_info *tx_info;
|
2015-12-03 14:56:17 +00:00
|
|
|
struct mbuf *mb = *mbp;
|
2011-03-21 09:58:24 +00:00
|
|
|
struct mbuf *m;
|
2015-12-03 14:56:17 +00:00
|
|
|
__be32 owner_bit;
|
2011-03-21 09:58:24 +00:00
|
|
|
int nr_segs;
|
2015-12-03 14:56:17 +00:00
|
|
|
int pad;
|
|
|
|
int err;
|
|
|
|
u32 bf_size;
|
|
|
|
u32 bf_prod;
|
|
|
|
u32 opcode;
|
|
|
|
u16 index;
|
|
|
|
u16 ds_cnt;
|
|
|
|
u16 ihs;
|
2011-03-21 09:58:24 +00:00
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
if (unlikely(!priv->port_up)) {
|
|
|
|
err = EINVAL;
|
2011-03-21 09:58:24 +00:00
|
|
|
goto tx_drop;
|
|
|
|
}
|
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
/* check if TX ring is full */
|
|
|
|
if (unlikely(mlx4_en_tx_ring_is_full(ring))) {
|
|
|
|
/* every full native Tx ring stops queue */
|
|
|
|
if (ring->blocked == 0)
|
|
|
|
atomic_add_int(&priv->blocked, 1);
|
|
|
|
/* Set HW-queue-is-full flag */
|
|
|
|
atomic_set_int(&ifp->if_drv_flags, IFF_DRV_OACTIVE);
|
|
|
|
priv->port_stats.queue_stopped++;
|
2011-03-21 09:58:24 +00:00
|
|
|
ring->blocked = 1;
|
|
|
|
priv->port_stats.queue_stopped++;
|
2014-09-23 12:37:01 +00:00
|
|
|
ring->queue_stopped++;
|
2011-03-21 09:58:24 +00:00
|
|
|
|
|
|
|
/* Use interrupts to find out when queue opened */
|
2015-12-03 14:56:17 +00:00
|
|
|
mlx4_en_arm_cq(priv, priv->tx_cq[tx_ind]);
|
|
|
|
return (ENOBUFS);
|
2014-09-23 12:37:01 +00:00
|
|
|
}
|
2011-03-21 09:58:24 +00:00
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
/* sanity check we are not wrapping around */
|
|
|
|
KASSERT(((~ring->prod) & ring->size_mask) >=
|
|
|
|
(MLX4_EN_TX_WQE_MAX_WQEBBS - 1), ("Wrapping around TX ring"));
|
|
|
|
|
2011-03-21 09:58:24 +00:00
|
|
|
/* Track current inflight packets for performance analysis */
|
|
|
|
AVG_PERF_COUNTER(priv->pstats.inflight_avg,
|
|
|
|
(u32) (ring->prod - ring->cons - 1));
|
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
/* Track current mbuf packet header length */
|
|
|
|
AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, mb->m_pkthdr.len);
|
|
|
|
|
|
|
|
/* Grab an index and try to transmit packet */
|
|
|
|
owner_bit = (ring->prod & ring->size) ?
|
|
|
|
cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0;
|
2011-03-21 09:58:24 +00:00
|
|
|
index = ring->prod & ring->size_mask;
|
2015-12-03 14:56:17 +00:00
|
|
|
tx_desc = (volatile struct mlx4_en_tx_desc *)
|
|
|
|
(ring->buf + index * TXBB_SIZE);
|
|
|
|
tx_info = &ring->tx_info[index];
|
|
|
|
dseg = &tx_desc->data;
|
|
|
|
|
|
|
|
/* send a copy of the frame to the BPF listener, if any */
|
|
|
|
if (ifp != NULL && ifp->if_bpf != NULL)
|
|
|
|
ETHER_BPF_MTAP(ifp, mb);
|
|
|
|
|
|
|
|
/* get default flags */
|
|
|
|
tx_desc->ctrl.srcrb_flags = CTRL_FLAGS;
|
|
|
|
|
|
|
|
if (mb->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))
|
|
|
|
tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM);
|
|
|
|
|
|
|
|
if (mb->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP |
|
|
|
|
CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
|
|
|
|
tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_TCP_UDP_CSUM);
|
|
|
|
|
|
|
|
/* do statistics */
|
|
|
|
if (likely(tx_desc->ctrl.srcrb_flags != CTRL_FLAGS)) {
|
|
|
|
priv->port_stats.tx_chksum_offload++;
|
|
|
|
ring->tx_csum++;
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
/* check for VLAN tag */
|
|
|
|
if (mb->m_flags & M_VLANTAG) {
|
|
|
|
tx_desc->ctrl.vlan_tag = cpu_to_be16(mb->m_pkthdr.ether_vtag);
|
|
|
|
tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN;
|
|
|
|
} else {
|
|
|
|
tx_desc->ctrl.vlan_tag = 0;
|
|
|
|
tx_desc->ctrl.ins_vlan = 0;
|
2014-09-23 12:37:01 +00:00
|
|
|
}
|
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
/* clear immediate field */
|
|
|
|
tx_desc->ctrl.imm = 0;
|
2014-09-23 12:37:01 +00:00
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
/* Handle LSO (TSO) packets */
|
|
|
|
if (mb->m_pkthdr.csum_flags & CSUM_TSO) {
|
|
|
|
u32 payload_len;
|
|
|
|
u32 mss = mb->m_pkthdr.tso_segsz;
|
|
|
|
u32 num_pkts;
|
|
|
|
|
|
|
|
opcode = cpu_to_be32(MLX4_OPCODE_LSO | MLX4_WQE_CTRL_RR) |
|
|
|
|
owner_bit;
|
|
|
|
ihs = mlx4_en_get_header_size(mb);
|
|
|
|
if (unlikely(ihs > MAX_INLINE)) {
|
|
|
|
ring->oversized_packets++;
|
|
|
|
err = EINVAL;
|
|
|
|
goto tx_drop;
|
|
|
|
}
|
|
|
|
tx_desc->lso.mss_hdr_size = cpu_to_be32((mss << 16) | ihs);
|
|
|
|
payload_len = mb->m_pkthdr.len - ihs;
|
|
|
|
if (unlikely(payload_len == 0))
|
|
|
|
num_pkts = 1;
|
|
|
|
else
|
|
|
|
num_pkts = DIV_ROUND_UP(payload_len, mss);
|
|
|
|
ring->bytes += payload_len + (num_pkts * ihs);
|
|
|
|
ring->packets += num_pkts;
|
|
|
|
priv->port_stats.tso_packets++;
|
|
|
|
/* store pointer to inline header */
|
|
|
|
dseg_inline = dseg;
|
|
|
|
/* copy data inline */
|
|
|
|
dseg = mlx4_en_store_inline_lso_data(dseg,
|
|
|
|
mb, ihs, owner_bit);
|
2014-09-23 12:37:01 +00:00
|
|
|
} else {
|
2015-12-03 14:56:17 +00:00
|
|
|
opcode = cpu_to_be32(MLX4_OPCODE_SEND) |
|
|
|
|
owner_bit;
|
|
|
|
ihs = mlx4_en_get_inline_hdr_size(ring, mb);
|
|
|
|
ring->bytes += max_t (unsigned int,
|
|
|
|
mb->m_pkthdr.len, ETHER_MIN_LEN - ETHER_CRC_LEN);
|
|
|
|
ring->packets++;
|
|
|
|
/* store pointer to inline header */
|
|
|
|
dseg_inline = dseg;
|
|
|
|
/* copy data inline */
|
|
|
|
dseg = mlx4_en_store_inline_data(dseg,
|
|
|
|
mb, ihs, owner_bit);
|
|
|
|
}
|
|
|
|
m_adj(mb, ihs);
|
|
|
|
|
|
|
|
/* trim off empty mbufs */
|
|
|
|
while (mb->m_len == 0) {
|
|
|
|
mb = m_free(mb);
|
|
|
|
/* check if all data has been inlined */
|
|
|
|
if (mb == NULL) {
|
|
|
|
nr_segs = 0;
|
|
|
|
goto skip_dma;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
err = bus_dmamap_load_mbuf_sg(ring->dma_tag, tx_info->dma_map,
|
|
|
|
mb, segs, &nr_segs, BUS_DMA_NOWAIT);
|
|
|
|
if (unlikely(err == EFBIG)) {
|
|
|
|
/* Too many mbuf fragments */
|
|
|
|
m = m_defrag(mb, M_NOWAIT);
|
|
|
|
if (m == NULL) {
|
|
|
|
ring->oversized_packets++;
|
|
|
|
goto tx_drop;
|
|
|
|
}
|
|
|
|
mb = m;
|
|
|
|
/* Try again */
|
|
|
|
err = bus_dmamap_load_mbuf_sg(ring->dma_tag, tx_info->dma_map,
|
|
|
|
mb, segs, &nr_segs, BUS_DMA_NOWAIT);
|
|
|
|
}
|
|
|
|
/* catch errors */
|
|
|
|
if (unlikely(err != 0)) {
|
|
|
|
ring->oversized_packets++;
|
|
|
|
goto tx_drop;
|
2014-09-23 12:37:01 +00:00
|
|
|
}
|
2015-12-03 14:56:17 +00:00
|
|
|
/* make sure all mbuf data is written to RAM */
|
|
|
|
bus_dmamap_sync(ring->dma_tag, tx_info->dma_map,
|
|
|
|
BUS_DMASYNC_PREWRITE);
|
2014-09-23 12:37:01 +00:00
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
skip_dma:
|
|
|
|
/* compute number of DS needed */
|
|
|
|
ds_cnt = (dseg - ((volatile struct mlx4_wqe_data_seg *)tx_desc)) + nr_segs;
|
2014-09-23 12:37:01 +00:00
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
/*
|
|
|
|
* Check if the next request can wrap around and fill the end
|
|
|
|
* of the current request with zero immediate data:
|
|
|
|
*/
|
|
|
|
pad = DIV_ROUND_UP(ds_cnt, DS_FACT);
|
|
|
|
pad = (~(ring->prod + pad)) & ring->size_mask;
|
|
|
|
|
|
|
|
if (unlikely(pad < (MLX4_EN_TX_WQE_MAX_WQEBBS - 1))) {
|
|
|
|
/*
|
|
|
|
* Compute the least number of DS blocks we need to
|
|
|
|
* pad in order to achieve a TX ring wraparound:
|
|
|
|
*/
|
|
|
|
pad = (DS_FACT * (pad + 1));
|
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* The hardware will automatically jump to the next
|
|
|
|
* TXBB. No need for padding.
|
|
|
|
*/
|
|
|
|
pad = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* compute total number of DS blocks */
|
|
|
|
ds_cnt += pad;
|
|
|
|
/*
|
|
|
|
* When modifying this code, please ensure that the following
|
|
|
|
* computation is always less than or equal to 0x3F:
|
|
|
|
*
|
|
|
|
* ((MLX4_EN_TX_WQE_MAX_WQEBBS - 1) * DS_FACT) +
|
|
|
|
* (MLX4_EN_TX_WQE_MAX_WQEBBS * DS_FACT)
|
|
|
|
*
|
|
|
|
* Else the "ds_cnt" variable can become too big.
|
|
|
|
*/
|
|
|
|
tx_desc->ctrl.fence_size = (ds_cnt & 0x3f);
|
|
|
|
|
|
|
|
/* store pointer to mbuf */
|
|
|
|
tx_info->mb = mb;
|
|
|
|
tx_info->nr_txbb = DIV_ROUND_UP(ds_cnt, DS_FACT);
|
|
|
|
bf_size = ds_cnt * DS_SIZE_ALIGNMENT;
|
|
|
|
bf_prod = ring->prod;
|
|
|
|
|
|
|
|
/* compute end of "dseg" array */
|
|
|
|
dseg += nr_segs + pad;
|
|
|
|
|
|
|
|
/* pad using zero immediate dseg */
|
|
|
|
while (pad--) {
|
|
|
|
dseg--;
|
|
|
|
dseg->addr = 0;
|
|
|
|
dseg->lkey = 0;
|
|
|
|
wmb();
|
|
|
|
dseg->byte_count = SET_BYTE_COUNT((1 << 31)|0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* fill segment list */
|
|
|
|
while (nr_segs--) {
|
|
|
|
if (unlikely(segs[nr_segs].ds_len == 0)) {
|
|
|
|
dseg--;
|
|
|
|
dseg->addr = 0;
|
|
|
|
dseg->lkey = 0;
|
|
|
|
wmb();
|
|
|
|
dseg->byte_count = SET_BYTE_COUNT((1 << 31)|0);
|
|
|
|
} else {
|
|
|
|
dseg--;
|
|
|
|
dseg->addr = cpu_to_be64((uint64_t)segs[nr_segs].ds_addr);
|
|
|
|
dseg->lkey = cpu_to_be32(priv->mdev->mr.key);
|
|
|
|
wmb();
|
|
|
|
dseg->byte_count = SET_BYTE_COUNT((uint32_t)segs[nr_segs].ds_len);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
wmb();
|
|
|
|
|
|
|
|
/* write owner bits in reverse order */
|
|
|
|
if ((opcode & cpu_to_be32(0x1F)) == cpu_to_be32(MLX4_OPCODE_LSO))
|
|
|
|
mlx4_en_store_inline_lso_header(dseg_inline, ihs, owner_bit);
|
|
|
|
else
|
|
|
|
mlx4_en_store_inline_header(dseg_inline, ihs, owner_bit);
|
2011-03-21 09:58:24 +00:00
|
|
|
|
|
|
|
if (unlikely(priv->validate_loopback)) {
|
|
|
|
/* Copy dst mac address to wqe */
|
2014-09-23 12:37:01 +00:00
|
|
|
struct ether_header *ethh;
|
|
|
|
u64 mac;
|
|
|
|
u32 mac_l, mac_h;
|
|
|
|
|
|
|
|
ethh = mtod(mb, struct ether_header *);
|
|
|
|
mac = mlx4_en_mac_to_u64(ethh->ether_dhost);
|
|
|
|
if (mac) {
|
|
|
|
mac_h = (u32) ((mac & 0xffff00000000ULL) >> 16);
|
|
|
|
mac_l = (u32) (mac & 0xffffffff);
|
|
|
|
tx_desc->ctrl.srcrb_flags |= cpu_to_be32(mac_h);
|
|
|
|
tx_desc->ctrl.imm = cpu_to_be32(mac_l);
|
|
|
|
}
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
/* update producer counter */
|
|
|
|
ring->prod += tx_info->nr_txbb;
|
2011-03-21 09:58:24 +00:00
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
if (ring->bf_enabled && bf_size <= MAX_BF &&
|
|
|
|
(tx_desc->ctrl.ins_vlan != MLX4_WQE_CTRL_INS_VLAN)) {
|
2011-03-21 09:58:24 +00:00
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
/* store doorbell number */
|
|
|
|
*(volatile __be32 *) (&tx_desc->ctrl.vlan_tag) |= cpu_to_be32(ring->doorbell_qpn);
|
2011-03-21 09:58:24 +00:00
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
/* or in producer number for this WQE */
|
|
|
|
opcode |= cpu_to_be32((bf_prod & 0xffff) << 8);
|
2014-09-23 12:37:01 +00:00
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
/*
|
|
|
|
* Ensure the new descriptor hits memory before
|
|
|
|
* setting ownership of this descriptor to HW:
|
|
|
|
*/
|
2011-03-21 09:58:24 +00:00
|
|
|
wmb();
|
2015-12-03 14:56:17 +00:00
|
|
|
tx_desc->ctrl.owner_opcode = opcode;
|
2011-03-21 09:58:24 +00:00
|
|
|
wmb();
|
2015-12-03 14:56:17 +00:00
|
|
|
mlx4_bf_copy(((u8 *)ring->bf.reg) + ring->bf.offset,
|
|
|
|
(volatile unsigned long *) &tx_desc->ctrl, bf_size);
|
2011-03-21 09:58:24 +00:00
|
|
|
wmb();
|
|
|
|
ring->bf.offset ^= ring->bf.buf_size;
|
|
|
|
} else {
|
2015-12-03 14:56:17 +00:00
|
|
|
/*
|
|
|
|
* Ensure the new descriptor hits memory before
|
|
|
|
* setting ownership of this descriptor to HW:
|
|
|
|
*/
|
2011-03-21 09:58:24 +00:00
|
|
|
wmb();
|
2015-12-03 14:56:17 +00:00
|
|
|
tx_desc->ctrl.owner_opcode = opcode;
|
2011-03-21 09:58:24 +00:00
|
|
|
wmb();
|
2015-12-03 14:56:17 +00:00
|
|
|
writel(cpu_to_be32(ring->doorbell_qpn),
|
|
|
|
((u8 *)ring->bf.uar->map) + MLX4_SEND_DOORBELL);
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
|
|
|
|
2015-12-03 14:56:17 +00:00
|
|
|
return (0);
|
2011-03-21 09:58:24 +00:00
|
|
|
tx_drop:
|
|
|
|
*mbp = NULL;
|
|
|
|
m_freem(mb);
|
2015-12-03 14:56:17 +00:00
|
|
|
return (err);
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
mlx4_en_transmit_locked(struct ifnet *dev, int tx_ind, struct mbuf *m)
|
|
|
|
{
|
|
|
|
struct mlx4_en_priv *priv = netdev_priv(dev);
|
|
|
|
struct mlx4_en_tx_ring *ring;
|
|
|
|
struct mbuf *next;
|
|
|
|
int enqueued, err = 0;
|
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
ring = priv->tx_ring[tx_ind];
|
2011-03-21 09:58:24 +00:00
|
|
|
if ((dev->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
|
|
|
|
IFF_DRV_RUNNING || priv->port_up == 0) {
|
|
|
|
if (m != NULL)
|
|
|
|
err = drbr_enqueue(dev, ring->br, m);
|
2014-09-23 12:37:01 +00:00
|
|
|
return (err);
|
2011-03-21 09:58:24 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
enqueued = 0;
|
2015-12-03 13:29:20 +00:00
|
|
|
if (m != NULL)
|
|
|
|
/*
|
|
|
|
* If we can't insert mbuf into drbr, try to xmit anyway.
|
|
|
|
* We keep the error we got so we could return that after xmit.
|
|
|
|
*/
|
|
|
|
err = drbr_enqueue(dev, ring->br, m);
|
|
|
|
|
2011-03-21 09:58:24 +00:00
|
|
|
/* Process the queue */
|
2013-02-09 04:13:45 +00:00
|
|
|
while ((next = drbr_peek(dev, ring->br)) != NULL) {
|
2015-12-03 14:56:17 +00:00
|
|
|
if (mlx4_en_xmit(priv, tx_ind, &next) != 0) {
|
2013-02-07 15:20:54 +00:00
|
|
|
if (next == NULL) {
|
2013-02-09 04:13:45 +00:00
|
|
|
drbr_advance(dev, ring->br);
|
2013-02-07 15:20:54 +00:00
|
|
|
} else {
|
2013-02-09 04:13:45 +00:00
|
|
|
drbr_putback(dev, ring->br, next);
|
2013-02-07 15:20:54 +00:00
|
|
|
}
|
2011-03-21 09:58:24 +00:00
|
|
|
break;
|
|
|
|
}
|
2013-02-09 04:13:45 +00:00
|
|
|
drbr_advance(dev, ring->br);
|
2011-03-21 09:58:24 +00:00
|
|
|
enqueued++;
|
|
|
|
if ((dev->if_drv_flags & IFF_DRV_RUNNING) == 0)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (enqueued > 0)
|
|
|
|
ring->watchdog_time = ticks;
|
|
|
|
|
|
|
|
return (err);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
mlx4_en_tx_que(void *context, int pending)
|
|
|
|
{
|
|
|
|
struct mlx4_en_tx_ring *ring;
|
|
|
|
struct mlx4_en_priv *priv;
|
|
|
|
struct net_device *dev;
|
|
|
|
struct mlx4_en_cq *cq;
|
|
|
|
int tx_ind;
|
|
|
|
cq = context;
|
|
|
|
dev = cq->dev;
|
|
|
|
priv = dev->if_softc;
|
|
|
|
tx_ind = cq->ring;
|
2014-09-23 12:37:01 +00:00
|
|
|
ring = priv->tx_ring[tx_ind];
|
2011-03-21 09:58:24 +00:00
|
|
|
if (dev->if_drv_flags & IFF_DRV_RUNNING) {
|
|
|
|
mlx4_en_xmit_poll(priv, tx_ind);
|
|
|
|
spin_lock(&ring->tx_lock);
|
|
|
|
if (!drbr_empty(dev, ring->br))
|
|
|
|
mlx4_en_transmit_locked(dev, tx_ind, NULL);
|
|
|
|
spin_unlock(&ring->tx_lock);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int
|
|
|
|
mlx4_en_transmit(struct ifnet *dev, struct mbuf *m)
|
|
|
|
{
|
|
|
|
struct mlx4_en_priv *priv = netdev_priv(dev);
|
|
|
|
struct mlx4_en_tx_ring *ring;
|
|
|
|
struct mlx4_en_cq *cq;
|
2014-12-01 11:45:24 +00:00
|
|
|
int i, err = 0;
|
|
|
|
|
|
|
|
/* Compute which queue to use */
|
2015-12-03 13:29:20 +00:00
|
|
|
if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) {
|
|
|
|
i = m->m_pkthdr.flowid % priv->tx_ring_num;
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
i = mlx4_en_select_queue(dev, m);
|
|
|
|
}
|
2011-03-21 09:58:24 +00:00
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
ring = priv->tx_ring[i];
|
2011-03-21 09:58:24 +00:00
|
|
|
if (spin_trylock(&ring->tx_lock)) {
|
|
|
|
err = mlx4_en_transmit_locked(dev, i, m);
|
|
|
|
spin_unlock(&ring->tx_lock);
|
|
|
|
/* Poll CQ here */
|
|
|
|
mlx4_en_xmit_poll(priv, i);
|
|
|
|
} else {
|
|
|
|
err = drbr_enqueue(dev, ring->br, m);
|
2014-09-23 12:37:01 +00:00
|
|
|
cq = priv->tx_cq[i];
|
2011-03-21 09:58:24 +00:00
|
|
|
taskqueue_enqueue(cq->tq, &cq->cq_task);
|
|
|
|
}
|
|
|
|
|
|
|
|
return (err);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Flush ring buffers.
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
mlx4_en_qflush(struct ifnet *dev)
|
|
|
|
{
|
|
|
|
struct mlx4_en_priv *priv = netdev_priv(dev);
|
2014-09-23 12:37:01 +00:00
|
|
|
struct mlx4_en_tx_ring *ring;
|
2011-03-21 09:58:24 +00:00
|
|
|
struct mbuf *m;
|
|
|
|
|
2014-09-23 12:37:01 +00:00
|
|
|
for (int i = 0; i < priv->tx_ring_num; i++) {
|
|
|
|
ring = priv->tx_ring[i];
|
2011-03-21 09:58:24 +00:00
|
|
|
spin_lock(&ring->tx_lock);
|
|
|
|
while ((m = buf_ring_dequeue_sc(ring->br)) != NULL)
|
|
|
|
m_freem(m);
|
|
|
|
spin_unlock(&ring->tx_lock);
|
|
|
|
}
|
|
|
|
if_qflush(dev);
|
|
|
|
}
|