Commit Graph

2714 Commits

Author SHA1 Message Date
Pedro F. Giffuni
71e3c3083b sys/powerpc: further adoption of SPDX licensing ID tags.
Mainly focus on files that use BSD 2-Clause license, however the tool I
was using misidentified many licenses so this was mostly a manual - error
prone - task.

The Software Package Data Exchange (SPDX) group provides a specification
to make it easier for automated tools to detect and summarize well known
opensource licenses. We are gradually adopting the specification, noting
that the tags are considered only advisory and do not, in any way,
superceed or replace the license texts.
2017-11-27 15:09:59 +00:00
Justin Hibbits
41eeef87ca Synchronize TLB1 mappings when created
This allows modules creating mappings to be loaded post-boot, after SMP has
started.  Without this, the TLB1 mappings can become unsynchronized and lead
to kernel page faults when accessed on the alternate CPUs.

MFC after:	3 weeks
2017-11-26 20:30:02 +00:00
Nathan Whitehorn
b78f74e564 Remove another extern int n_slbs made redundant by declaring this in
mmu_oea64.h.

MFC after:	3 weeks
2017-11-26 04:34:13 +00:00
Nathan Whitehorn
47f69f4f2b Use the cookie now set by loader to determine whether the value passed to
PowerPC kernels in r6 is actually metadata from loader(8) or gibberish
left in r6, which is not required to be anything under the
PAPR/ePAPR/CHRP/OF standards, by another boot loader.

Note that, as a result, systems need a new boot loader to boot PPC kernels
after this revision without ending up at a mountroot prompt. New boot
loaders are backwards compatible and can boot older kernels.

Reviewed by:	jhibbits
MFC after:	2 months
2017-11-26 03:53:20 +00:00
Nathan Whitehorn
91419bdafd Avoid assumptions about the BSP being CPU 0.
MFC after:	3 weeks
2017-11-25 23:23:24 +00:00
Nathan Whitehorn
8a92c52a84 On AIM systems, it is not actually possible to stop the CPU timer, so we
just set it to a large default value (and inherit any previously existing
value), hoping it never turns over. Instead, silently allow spurious
one-shots from rollovers.

MFC after:	10 days
2017-11-25 22:43:52 +00:00
Nathan Whitehorn
e54979488d Return base IRQ of PIC when added and massively increase the number of
available IRQs per PIC for large systems.

MFC after:	3 weeks
2017-11-25 22:42:05 +00:00
Nathan Whitehorn
50d82d6f6a Missed gate on __powerpc64__ for setting LPCR in r326207.
MFC after:	3 weeks
X-MFC-with:	r326207
2017-11-25 22:15:56 +00:00
Nathan Whitehorn
c0650b2f69 When booting from an FDT, make sure the FDT itself isn't included the range
of available memory. Boot loaders are supposed to add a reserved entry for
it, but not all do.

MFC after:	2 weeks
2017-11-25 22:14:30 +00:00
Nathan Whitehorn
5bcc3e4277 Allow platform modules to set the size of large pizes, as potentially
discovered from firmware, and better handle highly-discontiguous memory
and CPU maps.

MFC after:	3 weeks
2017-11-25 22:13:19 +00:00
Nathan Whitehorn
312fb3d8dd Invalidate TLB at boot using the correct IS settings on newer-than-POWER5
CPUs.

MFC after:	3 weeks
2017-11-25 22:10:10 +00:00
Nathan Whitehorn
d225a2a9c9 Definitions for registers and trap types found on new POWER CPUs.
MFC after:	3 weeks
2017-11-25 22:08:40 +00:00
Nathan Whitehorn
66d6978c27 Missed platform_smp_timebase_sync() in r326205.
MFC after:	3 weeks
X-MFC-With:	r326205
2017-11-25 22:06:40 +00:00
Nathan Whitehorn
5d7c76afc6 Make n_slbs public in a more straightforward way. Some platforms (like
PowerNV) use firmware-assisted mechanisms to discover it and need access
to the variable.

MFC after:	3 weeks
2017-11-25 22:05:05 +00:00
Nathan Whitehorn
cb74659e0c Preserve the LPCR on new-ish (POWER7 and POWER8) CPUs, preventing exceptions
and such from ending on the wrong CPU on SMP systems. It would be good to
have this be more generic somehow as POWER9s appear, but PPC does not
have features bits, unfortunately.

MFC after:	3 weeks
2017-11-25 22:03:25 +00:00
Nathan Whitehorn
f04a8fd6a9 Yield while spinning on APs and avoid announcing all CPUs unless bootverbose
is set. These improve startup performance on massively multithreaded systems
with 8-way SMT and dozens to hundreds of CPUs.

MFC after:	3 weeks
2017-11-25 22:01:55 +00:00
Nathan Whitehorn
de2dd83fb9 Whether you can use mttb() or not is more complicated than whether PSL_HV
is set and the right thing to do may be platform-dependent (it requires
firmware on PowerNV, for instance). Make it a new platform method called
platform_smp_timebase_sync().

MFC after:	3 weeks
2017-11-25 21:59:59 +00:00
Ed Schouten
814629dd64 Don't let cpu_set_syscall_retval() clobber exec_setregs().
Upon successful completion, the execve() system call invokes
exec_setregs() to initialize the registers of the initial thread of the
newly executed process. What is weird is that when execve() returns, it
still goes through the normal system call return path, clobbering the
registers with the system call's return value (td->td_retval).

Though this doesn't seem to be problematic for x86 most of the times (as
the value of eax/rax doesn't matter upon startup), this can be pretty
frustrating for architectures where function argument and return
registers overlap (e.g., ARM). On these systems, exec_setregs() also
needs to initialize td_retval.

Even worse are architectures where cpu_set_syscall_retval() sets
registers to values not derived from td_retval. On these architectures,
there is no way cpu_set_syscall_retval() can set registers to the way it
wants them to be upon the start of execution.

To get rid of this madness, let sys_execve() return EJUSTRETURN. This
will cause cpu_set_syscall_retval() to leave registers intact. This
makes process execution easier to understand. It also eliminates the
difference between execution of the initial process and successive ones.
The initial call to sys_execve() is not performed through a system call
context.

Reviewed by:	kib, jhibbits
Differential Revision:	https://reviews.freebsd.org/D13180
2017-11-24 07:35:08 +00:00
Justin Hibbits
1ccb14588b Check the page table before TLB1 in pmap_kextract()
The vast majority of pmap_kextract() calls are looking for a physical memory
address, not a device address.  By checking the page table first this saves
the formerly inevitable 64 (on e500mc and derivatives) iteration loop
through TLB1 in the most common cases.

Benchmarking this on the P5020 (e5500 core) yields a 300% throughput
improvement on dtsec(4) (115Mbit/s -> 460Mbit/s) measured with iperf.

Benchmarked on the P1022 (e500v2 core, 16 TLB1 entries) yields a 50%
throughput improvement on tsec(4) (~93Mbit/s -> 165Mbit/s) measured with
iperf.

MFC after:	1 week
Relnotes:	Maybe (significant performance improvement)
2017-11-21 03:12:16 +00:00
Pedro F. Giffuni
51369649b0 sys: further adoption of SPDX licensing ID tags.
Mainly focus on files that use BSD 3-Clause license.

The Software Package Data Exchange (SPDX) group provides a specification
to make it easier for automated tools to detect and summarize well known
opensource licenses. We are gradually adopting the specification, noting
that the tags are considered only advisory and do not, in any way,
superceed or replace the license texts.

Special thanks to Wind River for providing access to "The Duke of
Highlander" tool: an older (2014) run over FreeBSD tree was useful as a
starting point.
2017-11-20 19:43:44 +00:00
Pedro F. Giffuni
df57947f08 spdx: initial adoption of licensing ID tags.
The Software Package Data Exchange (SPDX) group provides a specification
to make it easier for automated tools to detect and summarize well known
opensource licenses. We are gradually adopting the specification, noting
that the tags are considered only advisory and do not, in any way,
superceed or replace the license texts.

Special thanks to Wind River for providing access to "The Duke of
Highlander" tool: an older (2014) run over FreeBSD tree was useful as a
starting point.

Initially, only tag files that use BSD 4-Clause "Original" license.

RelNotes:	yes
Differential Revision:	https://reviews.freebsd.org/D13133
2017-11-18 14:26:50 +00:00
Justin Hibbits
bb7137e1a3 Stop special casing 32-bit AIM in memory parsing
There's no need to special case 32-bit AIM to short circuit processing.
Some AIM CPUs can handle 36 bit addresses, and 64-bit CPUs can run 32-bit
OSes, so this will allow us to expand for that in the future if we desire.
2017-11-17 04:10:52 +00:00
Justin Hibbits
27353776c4 Expand the Freescale PCIe root complex driver with the ofw_pcib_pci
The interrupt map wasn't being allocated properly, preventing IRQs from being
allocated to children of the PCIe bus.  Fix this by cloning the ofw_pcib_pci
code, which handles all cases -- device tree and probed.

In the future this may become a subclass of the ofw_pcib_pci driver, but as
that's not an exported class, it's cloned for now.

MFC after:	3 weeks
2017-11-14 03:53:15 +00:00
Justin Hibbits
2d968f6dd4 Properly initialize the full md_page structure 2017-11-10 04:23:58 +00:00
Justin Hibbits
06ba753a7a Book-E pmap_mapdev_attr() improvements
* Check TLB1 in all mapdev cases, in case the memattr matches an existing
  mapping (doesn't need to be MAP_DEFAULT).
* Fix mapping where the starting address is not a multiple of the widest size
  base.  For instance, it will now properly map 0xffffef000, size 0x11000 using
  2 TLB entries, basing it at 0x****f000, instead of 0x***00000.

MFC after:	2 weeks
2017-11-10 04:14:48 +00:00
Jeff Roberson
8d6fbbb867 Replace manyinstances of VM_WAIT with blocking page allocation flags
similar to the kernel memory allocator.

This simplifies NUMA allocation because the domain will be known at wait
time and races between failure and sleeping are eliminated.  This also
reduces boilerplate code and simplifies callers.

A wait primitive is supplied for uma zones for similar reasons.  This
eliminates some non-specific VM_WAIT calls in favor of more explicit
sleeps that may be satisfied without new pages.

Reviewed by:	alc, kib, markj
Tested by:	pho
Sponsored by:	Netflix, Dell/EMC Isilon
2017-11-08 02:39:37 +00:00
Justin Hibbits
81d7ebb695 Add the ISEL feature macro for those powerpc cores that have it
This is mostly for completeness, we don't currently use it for anything else.
2017-11-08 01:26:44 +00:00
Justin Hibbits
bc3acf82cc Clear the WE bit in C code rather than the asm
According to EREF rlwinm is supposed to clear the upper 32 bits of the
register of 64-bit cores.  However, from experience it seems there's a bug
in the e5500 which causes the result to be duplicated in the upper bits of
the register.  This causes problems when applied to stashed SRR1 accessed
to retrieve context, as the upper bits are not masked out, so a
set_mcontext() fails.  This causes sigreturn() to in turn return with
EINVAL, causing make(1) to exit with error.

This bit is unused in e500mc derivatives (including e5500), so could just be
conditional on non-powerpc64, but there may be other non-Freescale cores
which do use it.  This is also the same as the POW bit on Book-S, so could
be cleared unconditionally with the only penalty being a few clock cycles
for these two interrupts.
2017-11-08 01:23:37 +00:00
Justin Hibbits
37f275860c Set the PRD extension list base address in little endian
All data accesses with the SATA controller are little endian.  This was
missed when writing the extension code.
2017-11-06 05:09:18 +00:00
Justin Hibbits
78220c7be8 Fix an off-by-one error missed in the initial commit of this driver
When the segment count is > 16 it spills into an 'indirect descriptor list',
which immediately follows the main table, but the indirect list is entry 15, so
needs to be skipped for the general list.
2017-11-05 22:09:59 +00:00
Justin Hibbits
809cd50ff5 Add Freescale QorIQ SATA controller support.
The Freescale SATA controller has many similarities to AHCI controllers, so
this driver is a heavily modified AHCI driver.  Currently it seems to only
do SATA 1.0 speeds (~100-150MB/s), so there is still room for improvement.

Still to be done:
* Address erratum SATA-A-006187 -- Spread Spectrum Support (intermittent
  non-recoverable transient data integrity error seen when SSC enabled).
* Linux doesn't read the log page as it hangs on the P1022.  See if that's
  applicable to this, and address accordingly.
* Try to determine what's holding back performance, and address it.

MFC after:	3 weeks
Differential Revision:	https://reviews.freebsd.org/D6071
2017-11-05 02:47:46 +00:00
Justin Hibbits
51cfee5d13 Stop passing -me500 to the assembler for Book-E kernels
We already pass -many to the assembler, and -me500 drops 64-bit instruction
handling, for some reason only breaking module building for 64-bit kernels.

Additionally, build with CTF for dtrace.
2017-11-04 00:47:21 +00:00
Justin Hibbits
8c6037c4f8 Fix integer type and format in debug print
gcc complains "cast to pointer from integer of different size".  phandle_t is
*always* a uint32_t, so treat it as such, not as a pointer.  Fixes 64-bit build.
2017-11-03 03:13:15 +00:00
Justin Hibbits
140db60323 Enable a bunch more options in the QORIQ64 kernel
This brings it closer to par with GENERIC64.  In the future I hope to have a
GENERIC64-E and GENERIC-E kernels as Book-E analogues to the GENERIC64/GENERIC
AIM kernels.
2017-11-01 03:54:07 +00:00
Justin Hibbits
7561a31ed9 Rename a couple files to not conflict with ZFS filenames
Now a kernel can be built with both ZFS and DPAA compiled in.
2017-11-01 03:09:16 +00:00
Justin Hibbits
8ccebb4435 Add Guest State (GS) bit to MSR bits
For completeness only.  It will be used by a hypervisor if/when one is written.
While here, sort the MSR bits into the proper categories.
2017-11-01 02:54:48 +00:00
Justin Hibbits
61b9e7ef6a Fix debug interrupts on 64-bit Book-E
Use a WORD_SIZE macro to define the correct offset to the second word
needed.  This corrects the offset calculation in 64-bit builds.
2017-11-01 02:40:15 +00:00
Justin Hibbits
a32b54357f Make DPAA work in 64-bit mode
Rework the dTSEC and FMan drivers to be more like a full bus relationship,
so that dtsec can use bus_alloc_resource() instead of trying to handle the
offset from the dts.  This required taking some code from the sparc64 ebus
driver to allow subdividing the fman region for the dTSEC devices.
2017-10-31 02:53:50 +00:00
Justin Hibbits
852ba10081 Update DPAA SDK to SDK 2.0
This adds some support for ARM as well as 64-bit.  64-bit on PowerPC is
currently not working, and ARM support has not been completed or tested on the
FreeBSD side.

As this was imported from a Linux tree, it includes some Linux-isms
(ioread/iowrite), so compile with the LinuxKPI for now.  This may change in the
future.
2017-10-30 03:41:04 +00:00
Justin Hibbits
f6bd9666a5 Add P5010/P5010E for completeness 2017-10-30 01:55:38 +00:00
Eitan Adler
a2aef24aa3 Update several more URLs
- Primarily http -> https
- Primarily FreeBSD project URLs
2017-10-29 08:17:03 +00:00
Michal Meloun
904d8c492f Add AT_HWCAP2 ELF auxiliary vector.
- allocate value for new AT_HWCAP2 auxiliary vector on all platforms.
 - expand 'struct sysentvec' by new 'u_long *sv_hwcap2', in exactly
   same way as for AT_HWCAP.

MFC after:	1 month
Reviewed by:	kib
Differential Revision:	https://reviews.freebsd.org/D12699
2017-10-21 12:05:01 +00:00
Bjoern A. Zeeb
8e94025b41 With r181803 on 2008-08-17 23:27:27Z the first VIMAGE commit went into
HEAD.  Enable VIMAGE in GENERIC kernels and some others (where GENERIC does
not exist) on HEAD.

Disable building LINT-VIMAGE with VIMAGE being default.

This should give it a lot more exposure in the run-up to 12 to help
us evaluate whether to keep it on by default or not.
We are also hoping to get better performance testing.
The feature can be disabled using nooptions.

Requested by:		many
Reviewed by:		kristof, emaste, hiren
X-MFC after:		never
Relnotes:		yes
Differential Revision:	https://reviews.freebsd.org/D12639
2017-10-20 21:40:59 +00:00
Justin Hibbits
d41742b585 Expand the TLB nest level mask to 3 bits to match the 32-bit mask
This really doesn't change anything right now, because BOOKE_TLB_MAXNEST is only
3, which fits into the 2 bits currently used.
2017-10-20 03:31:23 +00:00
Justin Hibbits
95ce4c00ec No need to check for AIM here
This block is already in a #ifdef AIM block.
2017-10-20 03:13:31 +00:00
Justin Hibbits
15f9620e36 Book-E debug trace fixes
* Book-E can have Altivec exceptions, so move it out of the AIM-only block.
* Print the right DSI trap mode (read vs write) for Book-E

While here, fix some whitespace found while reviewing other diffs.
2017-10-20 03:03:04 +00:00
Justin Hibbits
12accff186 Add some more devices to the MPC85XX-based configs
These devices bring the configs closer to a desktop-like (GENERIC) kernel
config.
* The Freescale DIU support was added to the config in r306358.
  Without keyboard support video support is nearly pointless, so add ukbd and
  ums.
* The AmigaOne X5000, and P1022 devboard, both use a variant of the ds1307 RTC
* cpufreq scaling is currently supported by the p1022.  More SoCs will be added
  eventually.
2017-10-19 03:38:53 +00:00
Justin Hibbits
5ff24e4eb4 Remove some unnecessary includes 2017-10-19 02:14:39 +00:00
Wojciech Macek
10b980e75b PPC: increase MAX_PICS to 32
Previous value was too low on dual-socket POWER8 system.

Submitted by:          Wojciech Macek <wma@freebsd.org>
Reviewed by:           nwhitehorn
Obtained from:         Semihalf
Sponsored by:          QCM Technologies
Differential revision: https://reviews.freebsd.org/D12540
2017-10-02 06:05:19 +00:00
Josh Paetzel
c77037f16f Fix indentation for r323068
PR:	220170
Reported by:	lidl
MFC after:	3 days
Pointyhat to:	jpaetzel
2017-09-19 20:40:05 +00:00