universal.
(1) New struct intr_map_data is defined as a container for arbitrary
description of an interrupt used by a device. Typically, an interrupt
number and configuration relevant to an interrupt controller is encoded
in such description. However, any additional information may be encoded
too like a set of cpus on which an interrupt should be enabled or vendor
specific data needed for setup of an interrupt in controller. The struct
intr_map_data itself is meant to be opaque for INTRNG.
(2) An intr_map_irq() function is created which takes an interrupt
controller identification and struct intr_map_data as arguments and
returns global interrupt number which identifies an interrupt.
(3) A set of functions to be used by bus drivers is created as well as
a corresponding set of methods for interrupt controller drivers. These
sets take both struct resource and struct intr_map_data as one of the
arguments. There is a goal to keep struct intr_map_data in struct
resource, however, this way a final solution is not limited to that.
(4) Other small changes are done to reflect new situation.
This is only first step aiming to create stable interface for interrupt
controller drivers. Thus, some temporary solution is taken. Interrupt
descriptions for devices are stored in INTRNG and two specific mapping
function are created to be temporary used by bus drivers. That's why
the struct intr_map_data is not opaque for INTRNG now. This temporary
solution will be replaced by final one in next step.
Differential Revision: https://reviews.freebsd.org/D5730
This driver works in PIO mode for now, interrupts are available only when
FIFO is enabled. The FIFO cannot be used with arbitrary sizes which defeat
its general use.
At some point we can add DMA transfers where the FIFO can be more useful.
Tested on uBMC (microBMC) and BBB.
Sponsored by: Rubicon Communications (Netgate)
a DRIVER_MODULE() referencing mmc_driver has a MODULE_DEPEND() on mmc. This
is because the kernel linker only searches for symbols in dependent modules,
so loading sdhci_pci (and other bus-flavors of sdhci) would fail when mmc
was not compiled into the kernel (even if you hand-loaded mmc first).
(Thanks to jilles@ for providing the vital clue about the kernel linker.)
In dual emac mode, the CPSW subsystem provides two independent ethernets.
This is implemented (as recommended by TI's TRM) with a mixture of switch
settings (vlans) and specific features of CPSW subsystem.
The driver was splitted to accommodate the shared parts (RX and TX rings
for example) while it still provides two independent ethernets.
Each of the ethernet ports driver has it's own set of MDIO registers among
the other private settings.
Previously this driver always operate in promisc mode, now the Switch ALE
(address table entry) is properly initialized and enabled.
The driver is also tested (and known to work) with both ports operating in
single port mode (active_slave 0 or 1).
Tested on uBMC (dual emac mode, both ports in single mode, giga and fast
ethernet) and BBB (single port, fast ethernet).
Sponsored by: Rubicon Communications (Netgate)
taskqueue_enqueue() was changed to support both fast and non-fast
taskqueues 10 years ago in r154167. It has been a compat shim ever
since. It's time for the compat shim to go.
Submitted by: Howard Su <howard0su@gmail.com>
Reviewed by: sephe
Differential Revision: https://reviews.freebsd.org/D5131
intr_pic_init_secondary. Replace them with a direct call. On BCM2836
and ARMADA XP we need to add this function, but it can be empty.
Reviewed by: ian, imp
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D5460
slightly wrong on the others. We should just check if mp_ncpus is set to
more than one CPU as we may wish to run on a single core even when SMP is
available.
Reviewed by: ian
Sponsored by: ABT Systems Ltd
Differential Revision: https://reviews.freebsd.org/D5458
Only L2 PIPT cache is supported for __ARM_ARCH >= 6.
In fact, this is just a pure proclamation as this option is used
only in armv4 specific files now.
am335x_prcm driver which uses it. Used BUS_PASS_BUS is a quick pick
for now and may be revised when other drivers start using multipass
feature.
This is needed after an update of Linux dts files done in r295436.
The ci20 port (by kan@) is going to reuse almost all of the intrng code
since the SoC in question looks suspiciously like someone took an ARM
SoC design and replaced the ARM core with a MIPS core.
* migrate out the code;
* rename ARM_ -> INTR_;
* rename arm_ -> intr_;
* move the interrupt flush routine from intr.c / intrng.c into
arm/machdep_intr.c - removing the code duplication and removing
the ARM specific bits from here.
Thanks to the Star Wars: The Force Awakens premiere line for allowing
me a couple hours of quiet time to finish the universe builds.
Tested:
* make universe
TODO:
* The structure definitions in subr_intr.c still includes machine/intr.h
which requires one duplicates all of the intrng definitions in
the platform code (which kan has done, and I think we don't have to.)
Instead I should break out the generic things (function declarations,
common intr structures, etc) into a separate header.
* Kan has requested I make the PIC based IPI stuff optional.
variable during mp_start() which is too late. Move this to mp_setmaxid()
where other architectures set it and move x86 assertions to MI code.
Reviewed by: kib (x86 part)
represented in 7-bits format in DT files, but system expect it in 8-bit
format. Also, fix two drivers that locally hack around this bug.
Submitted by: Michal Meloun <meloun@miracle.cz>
the name the function will have when the new ARM_INTRNG code is integrated,
and doing this rename first will make it easier to toggle the new interrupt
handling code on/off with a config option for debugging.
specific as we may use the pmu registers for other uses. No configs seem
to currently build this.
This will allow for more use of this device.
Discussed with: bz
Sponsored by: ABT Systems Ltd
redoing it as a separate driver. Now that each hardware timer is handled by
a separate instance of the timer driver, it no longer makes sense to bundle
the pps driver with the regular timecounter code. (When all 8 timers were
handled by one driver there was no choice about this.)
Split the hardware register definitions out to their own file, so that the
new pps driver (coming in a separate commit later) can share them.
With the PPS driver gone, the question of which hardware timer to use for
what purpose becomes much easier (some instances can't do the PPS capture).
Now we can just hardcore timer2 for eventtimer and timer3 for timecounter.
This also now only instantiates devices for the 2 hardware timers actually
used to implement eventtimer and timecounter. This is required so that
other drivers can come along and attach to other hardware timers to provide
other functionality. (In addition to PPS, this hardware can also do PWM
stuff, general pulse width and frequency measurements, etc. Maybe some
day we'll have drivers for those things.)
given the hardware name.
The ti,hwmods property is used (among other things) to associate an fdt node
with a specific instance of some hardware. For example given a device node
that contains the property ti,hwmods = "timer3", if you call this passing
"timer" as the hwmod string to look for it would return 3.
Some of FDT blobs for AM335x-based devices use pinmux pullup/pulldown
flag to setup initial GPIO ouputp value, e.g. 4DCAPE-43 sets LCD DATAEN
signal this way. It works for Linux because Linux driver does not enforce
pin direction until after it's requested by consumer. So input with pullup
flag set acts as output with GPIO_HIGH value
Reviewed by: loos
- Add driver for TDA19988 HDMI framer
- Add simple interface to communicate with HDMI sink: read EDID and set videomode
- Add event-based API to notify LCD controller when HDMI sink is available
- Add HDMI framer node and add refernce to it to lcdc node. This part of
DTS tree is custom and does not match Linux DTS because Linux uses
combination of pseudo-node in DTS and hardcoded driver information
that does not map to our model.
consumers can configure clock frequency
- Add ti_prcm_clk_set_source_freq wrapper for clk_set_source_freq
- Add am335x_clk_set_arm_disp_freq function to control pixel clock
frequency for LCD and HDMI output. Both of them are sensitive
to frequency skews and we need to get pixel clock matching requested
frequency as close to possible
charger configuration and provide some basic control knobs to
set charger voltage and dump config on boot. Two loader tunables
have been added:
o hw.am335x_pmic.bootverbose set to 1 to get more info on the
boot;
o hw.am335x_pmic.vo: set to charger voltage to be applied on
kernel initialization time, supported values are "4.10V",
"4.15V", "4.20V" and "4.25V".
Cleanup code a bit in general, move TPS65217 register
definitions into a separate header, convert bit-banging
defines into bitmap structures.
Also threat the case when power source is neither "AC" nor "USB"
as "Battery", not "Unknown".
files to vendor-provided ones. It should make easier to adopt platform
code to new revisions of hardware and to use DTS overlays for various
Beaglebone extensions (shields/capes).
Original dts filenames were not changed, they're now wrappers over dts
files provided by TI. So make sure you update .dtb files on your
devices as part of kernel update
GPIO addressing was changed: instead of one global /dev/gpioc0 there
are per-bank instances of /dev/gpiocX. Each bank has 32 pins so for
instance pin 121 on /dev/gpioc0 in old addressing scheme is now pin 25
on /dev/gpioc3
On Pandaboard serial console devices was changed from /dev/ttyu0 to
/dev/ttyu2 so you'll have to update /etc/ttys to get login prompt
on serial port in multiuser mode. Single user mode serial console
should work as-is
Differential Revision: https://reviews.freebsd.org/D2146
Reviewed by: rpaulo, ian, Michal Meloun, Svatopluk Kraus
ntpd is hard-coded to use /dev/ppsN, and typically when multiple PPS sources
are available the sysadmin will symlink the right one(s) to /dev/ppsN, so
it's best to not usurp those names directly.
both the post-filter and post-thread callbacks.
Also eliminate a completely unecessary write to INTC_ISR_CLEAR register,
which clears a software-generated interrupt that can only happen with a
write to INTC_ISR_SET (which nothing does).
The DISP DPLL clock is slower and was making the PRU programs slower
on FreeBSD than on Linux.
Submitted by: Manuel Stuehn <freebsdnewbie at freenet.de>
MFC after: 1 week
Minimum LCDC is 2 so clock freq shouild be 2*max_pixel_clock. Maximum pixel
clock for HDMI is 148500 (1920x1080). But AM335x can not run in this mode
due to bandwidth and clock limitations
1 second is not enugh for TDA19988 HDMI framer (e.g. on Beaglebone Black)
- Add per-device i2c_timout sysctl (dev.iichb.X.i2c_timeout) to control
I2C bus timeout manually
- Pass softc instead of device_t to all sysctl handlers
While in theory this should have been a transparent change (and was for all
other drivers), cpsw(4) never used the proper accessor macros in a few
places but spelt the indirect m_hdr.mh_* out itself. Convert those to
use m_len and m_data and unbreak the driver build.
To cut off the power we need to start the shutdown sequence by writing
the OFF bit on PMIC.
Once the PMIC is programmed the SoC needs to toggle the PMIC_PWR_ENABLE
pin when it is ready for the PMIC to cut off the power. This is done by
triggering the ALARM2 interrupt on SoC RTC.
The RTC driver only works in power management mode which means it won't
provide any kind of time keeping functionality. It only implements a way
to trigger the ALARM2 interrupt when requested.
Differential Revision: https://reviews.freebsd.org/D1489
Reviewed by: rpaulo
MFC after: 2 weeks
According to http://e2e.ti.com/support/arm/sitara_arm/f/791/t/210729 the
USB reset pulse has an undocumented duration of 200ns and during this
period the module must not be acessed.
We wait for 100us to take into account for some imprecision of the early
DELAY() loop.
This fixes the eventual 'External Non-Linefetch Abort (S)' that happens at
boot while resetting the musb subsystem.
While here, enable the USB subsystem clock before the first access.
Discussed with: ian, adrian
MFC after: 2 weeks
This enables the use of GPIO pins as interrupt sources for kernel devices
directly attached to gpiobus (userland notification will be added soon).
The use of gpio interrupts for other kernel devices will be possible when
intrng is complete.
All GPIO pins can be set to trigger on:
- active-low;
- active-high;
- rising edge;
- falling edge.
Tested on: Beaglebone-black
Fix the following issues:
- Removed revision from device softc, it isn't used anywhere else out of
device attach routine;
- Move the duplicated code for verification of valid banks (and pins) to
a single function;
- Use some macros to simplify the handling of some constants;
- Update some stale comments.
TI OMAP controllers which will return the reset-in-progress bit as zero if
you read the status register too fast after setting the reset bit.
The zero is apparently from a stale snapshot of the internal state presented
in the interface register, and leads to a false indication that the reset
is complete when it either hasn't started yet or is in-progress. The
workaround is to first loop until the bit is seen as asserted, then do the
normal loop waiting to see it de-asserted.
Submitted by: Michal Meloun <meloun@miracle.cz>
For OMAP4, the old values for 1MHz gave a bus frequency of about 890KHz.
The new numbers hit 1MHz exactly.
For AM335x the prescaler values are adjusted to give a 24MHz clock for
all 3 standard speeds, as the manual recommends (as near as we can tell,
there are errors and typos apparent in the document). Also, 1MHz speed
is added, and has been tested successfully on a BeagleboneWhite board.
PR: 195009
The current support for controlling i2c bus speed is an inconsistant mess.
There are 4 symbolic speed values defined, UNKNOWN, SLOW, FAST, FASTEST.
It seems to be universally assumed that SLOW means the standard 100KHz
rate from the original spec. Nothing ever calls iicbus_reset() with a
speed of FAST, although some drivers would treat it as the 400KHz standard
speed. Mostly iicbus_reset() is called with the speed set to UNKNOWN or
FASTEST, and there's really no telling what any individual driver will do
with those.
The speed of an i2c bus is limited by the speed of the slowest device on
the bus. This means that generally the bus speed needs to be configured
based on the board/system and the components within it. Historically for
i2c we've configured with device hints. Newer systems use FDT data and it
documents a clock-frequency property for i2c busses. Hobbyists and
developers are likely to want on the fly changes. These changes provide
all 3 methods, but do not require any existing drivers to change to use
the new facilities.
This adds an iicbus method, iicbus_get_frequency(dev, speed) that gets the
frequency for the requested symbolic speed. If the symbolic speed is SLOW
or if there is no speed configured for the bus, the returned value is
100KHz, always. Otherwise, if bus speed is configured by hints, fdt,
tunable, or sysctl, that speed is returned. It also adds a helper
function, iicbus_init_frequency() that any bus driver subclassed from
iicbus can initialize the frequency from some other source of info.
Initial driver implementations are provided for Freescale and TI.
Differential Revision: https://reviews.freebsd.org/D1174
PR: 195009
unit 0.
It seems that this 'simplification' was copied to all GPIO drivers in tree.
This fix a bug where a GPIO controller could fail to attach its children
(gpioc and gpiobus) if another GPIO driver attach first.
For an unkown reason (at moment), sometimes if_cpsw cannot read from PHY
and fails to attach calling cpsw_detach() which end up in a panic.
Fix it by doing the proper check before detach the miibus and also fix the
leak of few variables.
And to actually make it work, ether_ifattach() has to be moved to the end
of cpsw_attach() to avoid a race where calling ether_ifdetach() before
domain_init() (which will only run later on) would make it crash at
INP_INFO_RLOCK() on in_pcbpurgeif0().
Tested on: BBB (am335x)
MFC after: 1 week
to be present. Thsi creates a new per-SoC driver that handles probe and
setting/getting the gpio flags.
Differential Revision: https://reviews.freebsd.org/D943
Reviewed by: loos, rpaulo
MFC after: 1 week
The TI watchdog timer is present on BeagleBone's. Since 2014, U-Boot
has been booting the BeagleBone with the watchdog enabled. We need to
disable it on boot to avoid a spurious reset.
The timer isn't exactly precise, but it will do as a watchdog. This
is also a reflection of the watchdog(9) API.
In the future, we could handle interrupts, but the watchdog(9) API
needs to be a bit smarter before that can happen.
Differential Revision: https://reviews.freebsd.org/D965
Reviewed by: andrew
MFC after: 1 week
Relnotes: yes
few changes to drivers, no kernel config was added. As the SoCs are quite
old and the code is unmaintained start the process of removing support by
deleting the header file and code that depends on it along with the macro
SOC_OMAP3. Other Ti SoCs shouldn't be affected, other than for us to have
less code to maintain.
Differential Revision: https://reviews.freebsd.org/D936
Reviewed by: rpaulo, loos
. interrupt storm detected on "intr70:"; throttling interrupt source;
. Added access serialization on iicbus_transfer(), previously there was
no such protection and a new transfer could easily confuse the
controller;
. Add error checkings (i.e. stop the transfer when a error is detected
and do _not_ overwrite the previous error);
. On command done interrupt do not assume that the transfer was finished
sucessfully as we will receive the command done interrupt even after
errors;
. Simplify the FIFO handling;
. Reset the FIFO between the transfers as the FIFO may contain data from
the last (failed) transfer;
. Fix the iicbus speed for AM335x, which in turn will make better use of
the I2C noise filter (set to one internal clock cycle);
. Move the read and write handler to ithread instead of notifying the
requesting thread with wakeup(9);
. Fix the comments based on OMAP4 TRM.
The above changes allows me to read the EDID from my HDMI monitor on BBB
with gonzo's patches to support TDA19988 (which does 128 bytes reads) and
repeatedly scan the iicbus (with a modified i2c(8)) without lock up the bus.
Phabric: D465
(7-bit device address << 1), always leaving the room for the read/write bit.
This commit convert ti_i2c and revert r259127 on bcm2835_bsc to make them
compatible with 8-bit addresses. Previous to this commit an i2c device
would have different addresses depending on the controller it was attached
to (by example, when compared to any iicbb(4) based i2c controller), which
was a pretty annoying behavior.
Also, update the PMIC i2c address on beaglebone* DTS files to match the new
address scheme.
Now the userland utilities need to do the correct slave address shifting
(but it is going to work with any i2c controller on the system).
Discussed with: ian
MFC after: 2 weeks
The ti_i2c controller only works in the master mode and the i2c address
passed on iicbus_reset() is used to set the controller slave address when
operating as an i2c slave (which isn't currently supported).
When talking to a slave, the slave address is correctly provided to
ti_i2c_tranfer().
through a voltage divisor (R163 and R164 on page 4 of BBB schematic).
Add a note about this on ti_adc(4) man page. The ti_adc(4) man page will
first appear on 10.1-RELEASE.
MFC after: 1 week
Suggested by: Sulev-Madis Silber (ketas)
Manual page reviewed by: brueffer (D127)
and the actual PWM frequency.
Enforce the maximum value for the period sysctl.
The frequency systcl now allows the direct setting of the PWM frequency (it
will try to find the better clkdiv and period for a given frequency, i.e.
the ones that will give the better PWM resolution).
This allows the use lower frequencies on the PWM. Without changing the
clock prescaler the minimum PWM frequency was 1.52kHz.
PWM frequencies checked with an osciloscope.
PWM output tested with some R/C servos at 50Hz.
memory ordering model allows writes to different devices to complete out
of order, leading to a situation where the write that clears an interrupt
source at a device can complete after a write that unmasks and EOIs the
interrupt at the interrupt controller, leading to a spurious re-interrupt.
This adds a generic barrier function specific to the needs of interrupt
controllers, and calls that function from the GIC and TI AINTC controllers.
There may still be other soc-specific controllers that need to make the call.
Reviewed by: cognet, Svatopluk Kraus <onwahe@gmail.com>
MFC after: 3 days
platform code, it is expected these will be merged in the future when the
ARM code is more complete.
Until more boards can be tested only use this with the Raspberry Pi and
rrename the functions on the other SoCs.
Reviewed by: ian@
While it is the recommended initialization procedure, it hangs on the reset
of the second GPIO module on pandaboard.
Removes the module reset for now as more investigation would be needed.
Reported by: jceel
On AM335x each one of the four GPIO banks has two physical interrupt
lines, so we now allocate resources and setup our interrupt handler for
all the (8) available interrupts.
On OMAP3 and OMAP4 there is only one interrupt for each GPIO bank (6
banks, 6 interrupts), but there are two set of registers where the
first one is used to setup the delivery of interrupts to the MPU and
the second set, setup the delivery of interrupts to the DSP.
On AM335x, each set of registers controls each one of the interrupt
lines.
- Remove nonexistent registers for OMAP4 and AM335x, replace their use with
the correct ones for these SoCs.
- Remove stray whitespace.
Based on OMAP3, OMAP4 and AM335x TRMs.
Tested on Beaglebone-black.
- Don't allow high-speed mode on OMAP4 due to hardware erratum.
- Check the proper bit in the status register when waiting for the
controller to come out of reset.
- Add handling for the "non-removable" fdt property by always returning
"card is present" status.
- Add the non-removable property for the MMC card on a Beaglebone Black.
- Add the non-removable property for Pandaboard as a workaround.
For Pandaboard the card detect pin is handled by the twl6030 fpga device
which gets an interrupt on pin change and then has to query the fpga
for the actual status. We don't have code to do that yet.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>
errors.
Reset the GPIO module during the initialization. This is guaranteed to be
the same as a hardware reset. Tested on AM335x (BBB) and checked against
the omap3 and omap4 TRM.
Do a better job freeing resources when there are errors and on
ti_gpio_detach().
description was eaten by the dog (or an editor crash or something).
Add variable-frequency support to the arm mpcore eventtimer driver.
This allows a platform's early init code to tell the mpcore driver that the
clock frequency can vary. That causes the mpcore driver to register an
eventtimer, but not a timecounter. The platform has to provide a time
counter using some other fixed-frequency clock, but can still use the
per-cpu goodness of the mpcore hardware for event timers.
When the platform support code does something to change the frequency of
the CPU clocks (power saving, thermal management) it must tell the mpcore
driver code about it using arm_tmr_change_frequency().
The ADC has a 12bit resolution and its raw output can be read via sysctl(8)
interface.
The driver allows the setup of ADC clock, samples average and open delay
(the number of clock cycles to wait before start the conversion).
The TSC_ADC module is set in the general purpose mode (no touchscreen
support).
Tested on Beaglebone-black.
Written based on AM335x TRM.
Reviewed by: rpaulo
Approved by: adrian (mentor)
Tested by: me, Brian J. McGovern, Sulev-Madis Silber (ketas)
and the functionality it provided into arm/exception.S. Rename the main
irq handling routine from arm_handler_execute() to arm_irq_handler() to
make it more congruent with how other exception handlers are named, and
also update its signature to reflect what has long been reality: it is
passed just a trapframe pointer, no interrupt number argument.
appropriate for each of the 'foo' in the tree. This will allow us to
compile them together (although symbol conflicts prevent us from doing
that today, this just fixes the file name collision).
implementation in arm/machdep.c. Most arm platforms either don't need to
do anything, or just need to call the standard eventtimer init routines.
A generic implementation that does that is now provided via weak linkage.
Any platform that needs to do something different can provide a its own
implementation to override the generic one.
it into a bunch of different .c files. Remove declarations for the unused
mptramp() function from everywhere except AramadaXP (and I think it's
really not used there either, because the code that references it appears
to be insanely does-nothing in nature).
change the gpio children can be described as directly connected to the GPIO
controller without the need of describing the OFW GPIO bus itself on the
DTS file.
With this commit the OFW GPIO bus is fully functional on BBB and RPi.
GPIO controllers which want to use the OFW GPIO bus will need similar
changes.
Approved by: adrian (mentor, implicit)
to check the status property in their probe routines.
Simplebus used to only instantiate its children whose status="okay"
but that was improper behavior, fixed in r261352. Now that it doesn't
check anymore and probes all its children; the children all have to
do the check because really only the children know how to properly
interpret their status property strings.
Right now all existing drivers only understand "okay" versus something-
that's-not-okay, so they all use the new ofw_bus_status_okay() helper.
Note that this commit hasn't been compile tested because these files
are not hooked up to the build...
PR: 186129
Submitted by: Takanori Sawada
Approved by: rpaulo
and add static mappings that cover most of the on-chip peripherals with
1MB section mappings. This adds about 220MB or so available kva space
by not using a hard-coded 0xF0000000 as the mapping address.
searching. If you didn't configure a timer capture pin you'd get a data
abort as it wandered into the weeds, now you get a nice warning message
about your config, as originally intended.
capture mode together with the timecounter's PPS polling feature to get
very accurate PPS capture without any interrupt processing (or latency).
Hardware timers 4 through 7 have associated capture-trigger input pins.
When the PPS support is compiled in the code automatically chooses the
first timer it finds that has the capture-trigger pin set to input mode
(this is configured via the fdt data).
- Use named constants for register bits, instead of mystery numebrs
scattered around in the code.
- Use inline functions for bus space read/write, instead of macros
that rely on global variables.
- Move the timecounter struct into the softc instead of treating it
as a global variable. Backlink from it to the softc.
- This leaves a pointer to the softc as the only static/global variable
and it's now used only by DELAY().
this change we may end up with a panic (Fatal kernel mode data abort:
'External Non-Linefetch Abort (S)') as described in
http://e2e.ti.com/support/arm/sitara_arm/f/791/t/276862.aspx.
It is now possible to bring up I2C1 and I2C2 on BBB.
Approved by: adrian (mentor)
always returning '0' for all the reads, even for the outputs. It is now
known to work with gpioiic(4) and gpioled(4).
Approved by: adrian (mentor)
Tested on: BBB
host.host_ocr, examine the correct field when setting up the hardware. Also,
the offset for the capabilties register should be 0x140, not 0x240.
Submitted by: Ilya Bakulin <ilya@bakulin.de>
Pointy hat to: me
