The driver attempts to support all documented parts, but has only been
tested with the 512Mbit part on the Terasic DE4 FPGA board. It should be
trivial to adapt the driver's attach routine to other embedded boards
using with any parts in the family.
Also import isfctl(8) which can be used to erase sections of the flash.
Sponsored by: DARPA, AFRL
which presents a UART-like interface over the Avalon bus that can be
addressed over JTAG. This IP core proves extremely useful, allowing us to
connect trivially to the FreeBSD console over JTAG for FPGA-embedded hard
and soft cores. As interrupts are optionally configured for this soft
core, we support both interrupt-driven and polled modes of operation,
which must be selected using device.hints. UART instances appear in /dev
as ttyu0, ttyu1, etc.
However, it also contains a number of quirks, which make it difficult to
tell when JTAG is connected, and some buffering issues. We work around
these as best we can, using various heuristics.
While the majority of this device driver is not only not BERI-specific,
but also not MIPS-specific, for now add its defines in the BERI files
list, as the console-level parts are aware of where the first JTAG UART
is mapped on Avalon, and contain MIPS-specific address translation, to
use before Newbus and device.hints are available.
Sponsored by: DARPA, AFRL
Bluespec Extensible RISC Implementation (BERI) processor. BERI is a 64-bit
MIPS ISA soft CPU core that can be synthesised to Altera and Xilinx FPGAs,
and is being used for CPU and OS research at several institutions.
Sponsored by: DARPA, AFRL
on PowerPC support. This was clearly not something syscons was
designed to do (very specific assumptions about the nature of VGA
consoles on PCs), but fortunately others have long since blazed
the way on making it work regardless of that.
Sponsored by: DARPA, AFRL
type, explicitly print out "unknown" rather than the empty string, and
include the exception type number for ease of debugging.
Sponsored by: DARPA, AFRL
r239274 added support for ranges. Update XLP DTS to provide the correct
range parameter for the XLP SoC bus. Also fix bus_space_map method
for XLP bus space.
Submitted by: Sreekanth M. <sreekanth.molagavalli@broadcom.com>
First, pmap_clear_modify() is write protecting all mappings to the specified
page, not just clearing the modified bit. Specifically, it sets PTE_RO on
the PTE, which is wrong. Moreover, it is calling vm_page_dirty(), which is
not the expected behavior for pmap_clear_modify(). Generally speaking, the
machine-independent VM layer masks these mistakes. For example, setting
PTE_RO will result in additional soft faults, but not a catastrophe.
Second, pmap_clear_modify() may not clear the modified bits because it only
iterates over the PV list when the page has the PV_TABLE_MOD flag set and
elsewhere the pmap clears the PV_TABLE_MOD flag anytime a modified mapping
is write protected or destroyed. However, the page may still have other
mappings with the modified bit set.
Eliminate a stale comment.
to this pmap.
Tidy up the #include's.
Remove the (now) unused #define PMAP_SHPGPERPROC. (This should have
been removed in r239236.)
Tested by: jchandra
advantages. First, PV entries are roughly half the size. Second, this
allocator doesn't access the paging queues, and thus it will allow for the
removal of the page queues lock from this pmap.
Fix a rather serious bug in pmap_remove_write(). After removing write
access from the specified page's first mapping, pmap_remove_write() then
used the wrong "next" pointer. Consequently, the page's second, third,
etc. mappings were not write protected.
Tested by: jchandra
The machine-independent parts of the virtual memory system always pass a
valid pmap to the pmap functions that require one. Remove the checks for
NULL. (These checks have their origins in the Mach pmap.c that was
integrated into BSD. None of the new code written specifically for
FreeBSD included them.)
Reduce the size of a PV entry by eliminating pv_ptem. There is no need
to store a pointer to the page table page in the PV entry because it is
easily computed during the walk down the page table.
Eliminate the ptphint from the pmap. Long, long ago, page table pages
belonged to a vm object, and we would look up page table pages based
upon their offset within this vm object. In those days, this hint may
have had tangible benefits.
Tested by: jchandra
Modify MIPS page table entry (PTE) initialisation so that cachability
bits are set only once, using is_cacheable_mem() to determine what
caching properties are required, rather than also unconditionally
setting PTE_C_CACHE in init_pte_prot(). As PTE_C_CACHE |
PTE_C_UNCACHED == PTE_C_CACHE, this meant that all userspace memory
mappings of device memory (incorrectly) used caching TLB entries.
This is arguably not quite what we want, even though it is (more)
consistent with the MIPS pmap design: PTE caching properties should
be derived from machine-independent page table attributes, but this
is a substantially more complex change as the MIPS pmap doesn't yet
know about page attributes, causing it to ignore requests by device
drivers that want uncached userspace memory mappings as they
describe memory-mapped FIFOs or shared memory with a device not
participating in the cache coherence scheme.
This fixes cacheability issues (specifically, undesired and
unrequested caching) seen in userspace memory mappings of Avalon SoC
bus device memory on BERI MIPS.
Discussed with: jmallett, alc
Sponsored by: DARPA, AFRL
MFC after: 3 days
The last 12 bits of the limit registers have to be set to 1. These
bits are not significant in bridge BARs and are 0 on read, but the
bits are valid in the swap limit register and needs to be set.
This is required for ARM EABI. Section 7.1.1 of the Procedure Call for the
ARM Architecture (AAPCS) defines wchar_t as either an unsigned int or an
unsigned short with the former preferred.
Because of this requirement we need to move the definition of __wchar_t to
a machine dependent header. It also cleans up the macros defining the limits
of wchar_t by defining __WCHAR_MIN and __WCHAR_MAX in the same machine
dependent header then using them to define WCHAR_MIN and WCHAR_MAX
respectively.
Discussed with: bde
usermode, using shared page. The structures and functions have vdso
prefix, to indicate the intended location of the code in some future.
The versioned per-algorithm data is exported in the format of struct
vdso_timehands, which mostly repeats the content of in-kernel struct
timehands. Usermode reading of the structure can be lockless.
Compatibility export for 32bit processes on 64bit host is also
provided. Kernel also provides usermode with indication about
currently used timecounter, so that libc can fall back to syscall if
configured timecounter is unknown to usermode code.
The shared data updates are initiated both from the tc_windup(), where
a fast task is queued to do the update, and from sysctl handlers which
change timecounter. A manual override switch
kern.timecounter.fast_gettime allows to turn off the mechanism.
Only x86 architectures export the real algorithm data, and there, only
for tsc timecounter. HPET counters page could be exported as well, but
I prefer to not further glue the kernel and libc ABI there until
proper vdso-based solution is developed.
Minimal stubs neccessary for non-x86 architectures to still compile
are provided.
Discussed with: bde
Reviewed by: jhb
Tested by: flo
MFC after: 1 month
layer, but it is read directly by the MI VM layer. This change introduces
pmap_page_is_write_mapped() in order to completely encapsulate all direct
access to PGA_WRITEABLE in the pmap layer.
Aesthetics aside, I am making this change because amd64 will likely begin
using an alternative method to track write mappings, and having
pmap_page_is_write_mapped() in place allows me to make such a change
without further modification to the MI VM layer.
As an added bonus, tidy up some nearby comments concerning page flags.
Reviewed by: kib
MFC after: 6 weeks
in_cksum.h required ip.h to be included for struct ip. To be
able to use some general checksum functions like in_addword()
in a non-IPv4 context, limit the (also exported to user space)
IPv4 specific functions to the times, when the ip.h header is
present and IPVERSION is defined (to 4).
We should consider more general checksum (updating) functions
to also allow easier incremental checksum updates in the L3/4
stack and firewalls, as well as ponder further requirements by
certain NIC drivers needing slightly different pseudo values
in offloading cases. Thinking in terms of a better "library".
Sponsored by: The FreeBSD Foundation
Sponsored by: iXsystems
Reviewed by: gnn (as part of the whole)
MFC After: 3 days
The configuration is:
* RGMII, both ports
* arge0 - connected to PHY4 as a dedicated port (CPU port)
* arge1 - connected to the switch ports
I've verified this on my routerstation pro board.
* Add the i2c bitbang bus;
* Add the etherswitch/rtl8366rb drivers;
* "fix" the USB GPIO configuration so USB actually works.
Submitted by: Stefan Bethke <stb@lassitu.de>
The AP93 has:
* AR7240 - mips24k processor with integrated 10/100 switch and
various other peripherals;
* AR9283 - 2x2 2.4GHz 802.11n (with calibration data in flash);
* 64MB RAM;
* 16MB SPI flash.
The switch code detects as an AR8216 at the present moment, which isn't
_entirely_ strictly true. However, the MII/MDIO routing in AP93.hints
works - the arge0 MAC connects to PHY4 in the switch, but via the
switch internal MDIO bus. The switch connects to arge0's MDIO bus,
but only to export the switch registers.
Thanks to stb and ray for the switch work, and ray for helping determine
what the correct switch hints should be for this thing.
some of the IPI mechanisms used by the common MIPS SMP code so we could use
the multicast IPI facilities, on GXemul as well as on several real hardware
platforms, and the ability to have multiple hard IPI types.
This seems to break at least my test board here (AR71xx + AR8316 switch
PHY). Since I do have a whole sleuth of "normal" PHY boards (with
an AR71xx on a normal PHY port), I'll do some further testing with those
to determine whether this is a general issue, or whether it's limited
to the behaviour of the "fake" dedicated PHY port mode on these atheros
switches.
code and which had only stub implementations or no implementation on all
platforms. Makes gxemul compile.
Hinted by: rwatson
MFC after: 3 weeks
X-MFC by: rwatson:
1) Always implement missing bus space methods using a panic() stub rather
than a NULL pointer. This appeared not to trip up any existing device
drivers, but due to the nature of the devices I'm supporting locally,
I'm making use of some of the more obscure busspace methods, and
panic() is a preferred failure mode. For example, do this for the
setregion methods.
2) Hook up several existing busspace method implementations that were
provided in the file, but not actually present in the methods
structure. Especially, single-byte bus I/O routines. This should
allow bugs to be fixed in the Atheros 802.11 driver.
There are still some remaining unimplemented methods that would be
desirable to implement -- especially, 64-bit I/O calls that would
observably accelerate device performance on FPGA-based soft CPU cores
that are typically clocked an order of magnitude slower than
conventional hard core CPUs, but that remains for another day.
MFC after: 3 weeks
Discussed with: jmallett, scottl
Sponsored by: DARPA, AFRL
entirely of one machdep file lifted from the MALTA port, as well as
a low-level console and tty driver for the gxemul debugging console
device (the emulators stdio). As with many low-level embedded and
hypervisor console devices, it is polled only, so we drive TTY I/O
from a callout; we are perhaps a bit too aware of the MIPS physical
maps in order to attach the console before newbus comes to life.
The sample kernel configuration depends on an MD-based root file
system, which is not provided. However, any 64-bit, big-endian
userspace image (such as one generated for MALTA) should work.
This will hopefully be supplemented by additional device drivers for
gxemul-specific hardware simulations from Juli Mallett. We have
found oldtestmips quite useful for testing and improving aspects of
the MIPS port, so it's worth supporting better in FreeBSD.
Requested by: theraven, jmallett
Sponsored by: DARPA, AFRL
MFC after: 3 weeks
* Flesh out the PLL configuration fetch function, which will return the PLL
configuration based on the unit number and speed.
* Remove the PLL speed config logic from the AR71xx/AR91xx chip PLL config
function - pass in a 'pll' value instead.
* Modify arge_set_pll() to:
+ fetch the PLL configuration
+ write the PLL configuration
+ update the MII speed configuration.
This will allow if_arge to override the PLL configuration as required.
Obtained from: Linux/Atheros/OpenWRT
* Add a new method to set the MII mode - GMII, RGMII, RMII, MII.
+ arge0 supports all four (two for non-Gige interfaces.)
+ arge1 only supports two (one for non-gige interfaces.)
* Set the MII clock speed when changing the MAC PLL speed.
+ Needed for AR91xx and AR71xx; not needed for AR724x.
Tested:
* AR71xx only, I'll do AR913x testing tonight and fix whichever issues
creep up.
TODO:
* Implement the missing AR7242 arge0 PLL configuration, but don't
adjust the MII speed accordingly.
* .. the AR7240/AR7241 don't require this, so make sure it's not set
accidentally.
Bugs (not fixed here):
* Statically configured arge speeds are still broken - investigate why
that is on the AP96 board. Autonegotiate is working fine, but there
still seems to be an occasionally heavy packet loss issue.
Obtained from: Linux/Atheros/OpenWRT
arge1 still works (it's the standalone PHY) but arge0 and the other switch
ports don't work. They're enumerated though, demonstrating that the
mdiobus abstraction is correctly working.
This is only done if the ARGE_MDIO option is included.
* Shuffle the arge MDIO bus into a separate device, that needs to be
probed early (use hint.argemdio.X.order=0)
* hint.arge.X.mdio now specifies which miiproxy to rendezvous with.
* Call MAC/MDIO bus init during MDIO attach, not arge attach.
This is done regardless:
* Shift the arge MAC and MDIO bus reset code into separate functions
and call it early during MDIO bus attach. It's required for
correct MDIO bus IO to occur on AR71xx/AR91xx devices.
* Remove the AR71xx/AR91xx centric assumption that there's only one
MDIO bus. The initial code mapped miibus0(arge0) and miibus1(arge1)
MII register operations to the MII0 (arge0) register space. The
AR724x (and later, upcoming chipsets) have two MDIO busses and
the second is very much in use.
TODO:
* since the multiphy behaviour has changed (where now a phymask of >1
PHY will still be enumerated), multiphy setups may be quite wrong.
I'll go and fix these so they still have a chance of working, at least.
until the switch PHY support appears in -HEAD.
Submitted by: Stefan Bethke <stb@lassitu.de>
The default priority is now '1000' rather than '0'. This may cause some
unforseen regressions.
Submitted by: Stefan Bethke <stb@lassitu.de>
Reviewed by: imp
ar724x_pci.c.
* Move out the code which populates the firmware into ar71xx_fixup.c
* Shuffle around the ar724x fixup code to match what the ar71xx fixup
code does.
I've validated this on an AR7240 with AR9285 on-board NIC. It doesn't
yet load, as the AR9285 EEPROM code needs to be made "flash aware."
TODO:
* Validate that I haven't broken AR71xx
* Test AR9285/AR9287 onboard NICs, complete with EEPROM code changes
* Port over the needed BAR hacks for AR7240, AR7241 and AR7242 from
Linux OpenWRT. The current WAR has only been tested on the AR7240
and I'm not sure the way the BAR register is treated is "right".
The "fixup" method here is right when setting the BAR for local access -
ie, the BAR address is either 0xffff (AR7240) or 0x1000ffff (AR7241/AR7242),
but the ath9k-fixup.c code (Linux OpenWRT) does this when setting the
initial "fixup" BAR. It then restores the original BAR.
I'll have to read the ar724x PCI bus glue to see what other special cases
await.
* arge0 doesn't (yet) work via the switch PHY ports; I'm not sure why.
* arge1 maps to the WAN port. That works.
TODO:
* The PLL register needs a different (non-default) value for Gigabit
Ethernet. The board setup code needs to be extended a bit to allow
for non-default pll_1000 values - right now, those values come out
of hard-coded values in the per-chip set_pll_ge() routines.
Obtained from: Linux / OpenWRT
This uses the new firmware(9) method for squirreling away the EEPROM
contents from SPI flash so ath(4) can get to them later.
It won't work out of the box just yet - you have to add this to
if_ath_pci.c:
#define ATH_EEPROM_FIRMWARE
.. until I've added it as a configuration option and updated things.
future use by the ath(4) driver.
These embedded devices put the calibration/PCI bootstrap data on the
on board SPI flash rather than on an EEPROM connected to the NIC.
For some boards, there's two NICs and two sets of EEPROM data in the
main SPI flash.
The particulars:
* Introduce ath_fixup_size, which is the size of the EEPROM area in
bytes.
* Create a firmware image with a name based on the PCI device identifier
(bus/slot/device/function).
* Hide some verbose debugging behind 'bootverbose'.
ath(4) can then use this to load in the EEPROM data.
This requires AR71XX_ATH_EEPROM to be defined.
* the openwrt code doesn't treat 0/0/0 any differently
from other bus/slot/func combinations.
* A "local write" function writes to the LCONF area, and
so I've added it.
* The PCI workaround at attach time uses this LCONF code,
which it already did ..
* .. but it is a 4 byte write, not a 2 byte write.
Even though it's PCIR_COMMAND which is a two byte PCI register.
Tested on: AR7161
TODO: The other two AR71xx derivatives
TODO: More thoroughly stare at the datasheets I do have
and if it indeed is incorrect, push fixes to both
FreeBSD and Linux/OpenWRT.
Obtained from: Linux OpenWRT
This makes our naming scheme more closely match other systems and the
expectations of much third-party software. MIPS builds which are little-endian
should require and exhibit no changes. Big-endian TARGET_ARCHes must be
changed:
From: To:
mipseb mips
mipsn32eb mipsn32
mips64eb mips64
An entry has been added to UPDATING and some foot-shooting protection (complete
with warnings which should become errors in the near future) to the top-level
base system Makefile.
New kernel events can be added at various location for sampling or counting.
This will for example allow easy system profiling whatever the processor is
with known tools like pmcstat(8).
Simultaneous usage of software PMC and hardware PMC is possible, for example
looking at the lock acquire failure, page fault while sampling on
instructions.
Sponsored by: NETASQ
MFC after: 1 month
The on-chip SD slots do not have PCI BARs corresponding to them, so
this has to be handled in the custom SoC memory allocation.
Provide memory resource for rids corresponding to BAR 0 and 1 in
the custom allocation code.
The XLP on-chip devices have PCI configuration headers, but some of the
devices need custom resource allocation code.
- devices with no MEM/IO BARs with registers in PCIe extended reg
space have to be handled in memory resource allocation
- devices without INTPIN/INTLINE in PCI header can be supported
by having these faked with a shadow register.
- Some devices does not allow 8/16 bit access to the register space,
he default bus space cannot be used for these.
Subclass pci and override attach and resource allocation methods to
take care of this.
Remove earlier code which did this partially.
Move XLP PCI UART device to sys/mips/nlm/dev/ directory. Other
drivers for the XLP SoC devices will be added here as well.
Update uart_cpu_xlp.c and uart_pci_xlp.c use macros for uart port,
speed and IO frequency.
Features:
- network driver for the four 10G interfaces and two management ports
on XLP 8xx.
- Support 4xx and 3xx variants of the processor.
- Source code and firmware building for the 16 mips32r2 micro-code engines
in the Network Accelerator.
- Basic initialization code for Packet ordering Engine.
Submitted by: Prabhath Raman (prabhath at netlogicmicro com)
[refactored and fixed up for style by jchandra]
On XLP evaluation platform, the board information is stored
in an I2C eeprom and the network block configuration is available
from a CPLD connected to the GBU (NOR flash bus). Add support
for both of these.
Support for the Security and RSA blocks on XLP SoC. Even though
the XLP supports many more algorithms, only the ones supported
in OCF have been added.
Submitted by: Venkatesh J. V. (venkatesh at netlogicmicro com)
- XLP supports hardware swap for PCIe IO/MEM accesses. Since we
are in big-endian mode, enable hardware swap and use the normal
bus space.
- move some printfs to bootverbose, and remove others.
- fix SoC device resource allocation code
- Do not use '|' while updating PCIE_BRIDGE_MSI_ADDRL
- some style fixes
In collaboration with: Venkatesh J. V. (venkatesh at netlogicmicro com)
- Replace MIPS24K-specific code with more generic framework that will
make adding new CPU support easier
- Add MIPS24K support for new framework
- Limit backtrace depth to 1 for stability reasons and add option
HWPMC_MIPS_BACKTRACE to override this limitation
As of FreeBSD 8, this driver should not be used. Applications that use
posix_openpt(2) and openpty(3) use the pts(4) that is built into the
kernel unconditionally. If it turns out high profile depend on the
pty(4) module anyway, I'd rather get those fixed. So please report any
issues to me.
The pty(4) module is still available as a kernel module of course, so a
simple `kldload pty' can be used to run old-style pseudo-terminals.
These are needed for some particular port configurations where the default
speed isn't suitable for all link speed types. (Ie, changing 10/100/1000MBit
PLL rate requires a similar MII clock rate, rather than a fixed MII rate.)
This is:
* only currently implemented for the ar71xx;
* isn't used anywhere (yet), as the final interface for this hasn't yet
been determined.
function.
From the submitter:
This patch fixes an issue I encountered using an NFS root with an
ar71xx-based MikroTik RouterBoard 450G on -current where the kernel fails
to contact a DHCP/BOOTP server via if_arge when it otherwise should be able
to. This may be the same issue that Monthadar Al Jaberi reported against
an RSPRO on 6 March, as the signature is the same:
%%%
DHCP/BOOTP timeout for server 255.255.255.255
DHCP/BOOTP timeout for server 255.255.255.255
DHCP/BOOTP timeout for server 255.255.255.255
.
.
.
DHCP/BOOTP timeout for server 255.255.255.255
DHCP/BOOTP timeout for server 255.255.255.255
arge0: initialization failed: no memory for rx buffers
DHCP/BOOTP timeout for server 255.255.255.255
arge0: initialization failed: no memory for rx buffers
%%%
The primary issue that I found is that the DHCP/BOOTP message that
bootpc_call() is sending never makes it onto the wire, which I believe is
due to the following:
- Last December, a change was made to the ifioctl that bootpc_call() uses
to adjust the netmask around the sosend().
- The new ioctl (SIOCAIFADDR) performs an if_init when invoked, whereas the
old one (SIOCSIFNETMASK) did not.
- if_arge maintains its own sense of link state in sc->arge_link_status.
- On a single-phy interface, sc->arge_link_status is initialized to 0 in
arge_init_locked().
- sc->arge_link_status remains 0 until a phy state change notification
causes arge_link_task to run, notice the link is up, and set it to 1.
- The inits caused by the ifioctls in bootpc_call are reinitializing the
interface, but not the phy, so sc->arge_link_status goes to 0 and remains
there.
- arge_start_locked() always sees sc->arge_link_status == 0 and returns
without queuing anything.
The attached patch changes arge_init_locked() such that in the single-phy
case, instead of initializing sc->arge_link_status to 0, it runs
arge_link_task() to set it according to the current phy state. This change
has allowed my setup to mount an NFS root successfully.
Submitted by: Patrick Kelsey <kelsey@ieee.org>
Reviewed by: juli
I had some interesting hangs until I realised I should try flushing the
DDR FIFO register and lo and behold, hangs stopped occuring.
I've put in a few DDR flushes here and there in case people decide to
reuse some of these functions. It's very very likely they're almost
all superflous.
To test:
* Connect to a network with a _lot_ of broadcast traffic
* Do this:
# while true; do ifconfig arge0 down; ifconfig arge0 up; done
This fixes the mbuf exhaustion that has been reported when the interface
state flaps up/down.
required for the ABI the kernel is being built for.
XXX This is implemented in a kind-of nasty way that involves including source
files, but it's still an improvement.
o) Retire ISA_* options since they're unused and were always wrong.
* enable ALQ and net80211/ath ALQ logging by default, to make it possible
to get debug register traces.
* Update some comments
* Enable HWPMC for testing.
implementations or no implementation on all platforms.
Some of these functions might be good ideas, but their semantics were unclear
given the lack of implementation, and an unlucky porter could be fooled into
trying to implement them or, worse, being baffled when something like
platform_trap_enter() failed to be called.
- Pass interrupt trapframe for handlers dow the chain
- Add PMC interrupt handler
PMC interrupt is a special case, so we want handle it as soon as possible
with minimum overhead. So we handle it apb filter routine.
bootable image.
The kernel has to fit inside an 896KiB area in a 4MB SPI flash.
So a bunch of stuff can't be included (and more is to come), including
(unfortunately) IPv6.
TODO:
* GPIO modules need to be created
* Shrink the image a bit more by removing some of the CAM layer debugging
strings.
make use of it where possible.
This primarily brings in support for newer hardware, and FreeBSD is not yet
able to support the abundance of IRQs on new hardware and many features in the
Ethernet driver.
Because of the changes to IRQs in the Simple Executive, we have to maintain our
own list of Octeon IRQs now, which probably can be pared-down and be specific
to the CIU interrupt unit soon, and when other interrupt mechanisms are added
they can maintain their own definitions.
Remove unmasking of interrupts from within the UART device now that the
function used is no longer present in the Simple Executive. The unmasking
seems to have been gratuitous as this is more properly handled by the buses
above the UART device, and seems to work on that basis.
o) The MAC set must occur before the multicast list is set up as the former
will enable the CAM unconditionally, while promiscuous mode disables it,
so if promiscuous mode is to be set this must occur after the MAC is
programmed.
o) The multicast list must be set up unconditionally as even if flags have
not changed, if the interface has gone through a reinitialization, the
state of the CAM as changed by the MAC initialization could be incorrect.
o) Call octm_init when flags change, even if the interface is already running.
XXX It would be good to use a better way to size intrcnt.
o) Fix literal 4s that are supposed to be sizeof (u_long).
XXX Why the * 2 here? Is this an artifact of a different system that this
code came from? We seem to allocate twice as much space for intrcnt
as we admit to in sintrcnt.
