Commit Graph

37 Commits

Author SHA1 Message Date
Andrew Turner
59c3cb81c1 Rename ARM_INTRNG and MIPS_INTRNG to INTRNG. This will help with machine
independent code that needs to know about INTRNG such as PCI drivers.

Obtained from:	ABT Systems Ltd
Sponsored by:	The FreeBSD Foundation
2016-04-15 16:05:41 +00:00
Stanislav Galabov
915c6043b0 Make NIRQ configurable for MIPS
Submitted by:	kan
Reviewed by:	kan
Approved by:	adrian (mentor)
Differential Revision:	https://reviews.freebsd.org/D5964
2016-04-15 15:44:02 +00:00
Stanislav Galabov
448f746eb6 Add MIPS_INTRNG to sys/conf/options.mips
This was somehow missed in the commit of
https://reviews.freebsd.org/D5182
although it was in the original diff submitted for review.

Approved by:	adrian (mentor)
Differential Revision:	https://reviews.freebsd.org/D5568
2016-03-08 08:57:53 +00:00
Adrian Chadd
04b5e02371 Rename some CPU_MIPSxxx options and add new CPU_MIPSxxx options
This revision does the following renames:
CPU_MIPS24KC -> CPU_MIPS24K
CPU_MIPS74KC -> CPU_MIPS74K
CPU_MIPS1004KC -> CPU_MIPS1004K

It also adds the following new CPU_MIPSxxx options:
CPU_MIPS24KE, CPU_MIPS34K, CPU_MIPS1074K, CPU_INTERAPTIV, CPU_PROAPTIV

CPU_MIPSxxxxKC is limiting and possibly misleading as it implies the
MIPSxxxxK CPU has no FPU.
It would be better if the CPUs are named after their standard functionalities
only and the presence or absence of FPU can then be controlled via the
CPU_HAVEFPU option.

I will send out another dependent revision that moves MIPS 32 r2 and r3
CPUs to use the EHB instruction for clearing hazards instead of NOP/SSNOP.

Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
Reviewed by:	imp
Differential Revision:	https://reviews.freebsd.org/D5077
2016-02-02 07:47:38 +00:00
Adrian Chadd
8fa95ba8ff Flesh out some build time configuration options for the realtek/mediatek
ports.

The sys/mips/rt305x/ code currently has these hard-coded with a comment
to make them configurable; this is the first step towards that.

Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
2015-12-24 15:58:33 +00:00
Adrian Chadd
d06ccd84b3 Begin the initial support for the mips1004kc core.
* add build option;
* add initial coherence manager config register bits;
* use the right hazard instruction (ehb);
* add page attributes.

Tested:

* MT7621A SoC (not yet in-tree)

Submitted by:	Stanislav Galabov <sgalabov@gmail.com>
2015-12-24 15:52:21 +00:00
Bjoern A. Zeeb
62820660cc Introduce opt_netfpga.h and allow setting NF10BMAC_64BIT from mips kernel
configs.  Switch the BERI_NETFPGA_MDROOT to 64bit by default.

Give we have working interrupts also cleanup the extra polling CFLAGS from
the module Makefile.

MFC after:	2 weeks
2014-06-26 17:20:45 +00:00
Luiz Otavio O Souza
b7c7433150 Add support for reading RouterBoard's memory which is passed by the loader
(RouterBOOT).

Tested on RouterBoards, various and on RSPRO, TP-Link MR3x20
(for regressions).
2014-05-09 14:02:18 +00:00
Brooks Davis
f2de4d722e MFP4:
Change 231031 by brooks@brooks_zenith on 2013/07/11 16:22:08

        Turn the unused and uncompilable MIPS_DISABLE_L1_CACHE define in
        cache.c into an option and when set force I- and D-cache line
        sizes to 0 (the latter part might be better as a tunable).

        Fix some casts in an #if 0'd bit of code which attempts to
        disable L1 cache ops when the cache is coherent.

Sponsored by:	DARPA/AFRL
2013-10-22 21:16:57 +00:00
Brooks Davis
f66834b69a MFP4:
Change 228019 by bz@bz_zenith on 2013/04/23 13:55:30

	Add kernel side support for large TLB on BERI/CHERI.
	Modelled similar to NLM

MFC after:	3 days
Sponsored by:	DAPRA/AFRL
2013-10-22 21:08:25 +00:00
Adrian Chadd
57778cfec4 Add two new MIPS CPU families - mips24k and mips74k.
They're both different cores:

* mips24k is an 8-stage pipeline, mips32r1 ABI, non-superscalar core.
* mips74k is a dual-issue 15-stage superscalar design, mips32r2 ABI.

They have different sets of quirks and bugs; these #define entries
will be used to work around these.

Now, strictly speaking, we should have CPU ABI families (mips32r1, mips32r2,
etc) and CPU core types (mips4k, mips24k, mips74k, etc.)  But this is the
starting point of that particular tidy-up.

Reviewed by:	imp@
Approved by:	re@ (gjb)
2013-10-09 00:21:21 +00:00
Warner Losh
0cc59c05a3 Add an option for the GE FES based packet engines. Its board IDs
overlap with the standard ones, so kernels for this family of boards
need the option OCTEON_VENDOR_GEFES.
2013-04-23 09:40:42 +00:00
Juli Mallett
b29648facd Add basic support for the Ubiquiti EdgeRouter Lite.
Note that USB does not currently work, and the flash is connected via USB, so
local storage is not working.
2013-01-02 23:17:50 +00:00
Juli Mallett
01a310bd57 o) Add support for specifying a model of Octeon to target at compile-time,
reducing the number of runtime checks done by the SDK code.
o) Group board/CPU information at early startup by subject matter, so that e.g.
   CPU information is adjacent to CPU information and board information is
   adjacent to board information.
2012-11-24 02:00:29 +00:00
Juli Mallett
320a9376e9 Add support for Radisys as a vendor of Octeon hardware. Add some preliminary
support for what their boot loader refers to as the "RSYS4GBE", of which there
are two instances ("Data Processing Blocks") on the Radisys ATCA-7220.
2012-10-26 00:08:50 +00:00
Warner Losh
3ac5e4bbea List all the mips MACHINE_ARCH values in the options file to allow
conditional inclusion based on the MACHINE_ARCH we're compiling for.
Make ucmpdi2 conditional on mips or mipsel.
2012-10-25 04:21:05 +00:00
Aleksandr Rybalko
62a3930e06 Move AR71XX (MIPS SoCs family) options to options.mips file.
PR:		170859
Submitted by:	Luiz Otavio O Souza
Approved by:	adrian (mentor)
2012-08-26 20:22:43 +00:00
Robert Watson
c9790125b5 Add preliminary support for the SRI International / University of Cambridge
Bluespec Extensible RISC Implementation (BERI) processor.  BERI is a 64-bit
MIPS ISA soft CPU core that can be synthesised to Altera and Xilinx FPGAs,
and is being used for CPU and OS research at several institutions.

Sponsored by:   DARPA, AFRL
2012-08-25 08:31:21 +00:00
Robert Watson
8122a592ee Provide basic glue to allow syscons to be used on MIPS, modelled
on PowerPC support.  This was clearly not something syscons was
designed to do (very specific assumptions about the nature of VGA
consoles on PCs), but fortunately others have long since blazed
the way on making it work regardless of that.

Sponsored by:	DARPA, AFRL
2012-08-25 08:09:37 +00:00
Alan Cox
f167c4a762 Port the new PV entry allocator from amd64/i386. This allocator has two
advantages.  First, PV entries are roughly half the size.  Second, this
allocator doesn't access the paging queues, and thus it will allow for the
removal of the page queues lock from this pmap.

Fix a rather serious bug in pmap_remove_write().  After removing write
access from the specified page's first mapping, pmap_remove_write() then
used the wrong "next" pointer.  Consequently, the page's second, third,
etc. mappings were not write protected.

Tested by:	jchandra
2012-08-13 17:38:38 +00:00
Adrian Chadd
72b9c70e36 Break out the arge MDIO bus code into an optional argemdio device.
This is only done if the ARGE_MDIO option is included.

* Shuffle the arge MDIO bus into a separate device, that needs to be
  probed early (use hint.argemdio.X.order=0)
* hint.arge.X.mdio now specifies which miiproxy to rendezvous with.
* Call MAC/MDIO bus init during MDIO attach, not arge attach.

This is done regardless:

* Shift the arge MAC and MDIO bus reset code into separate functions
  and call it early during MDIO bus attach.  It's required for
  correct MDIO bus IO to occur on AR71xx/AR91xx devices.

* Remove the AR71xx/AR91xx centric assumption that there's only one
  MDIO bus.  The initial code mapped miibus0(arge0) and miibus1(arge1)
  MII register operations to the MII0 (arge0) register space.  The
  AR724x (and later, upcoming chipsets) have two MDIO busses and
  the second is very much in use.

TODO:

* since the multiphy behaviour has changed (where now a phymask of >1
  PHY will still be enumerated), multiphy setups may be quite wrong.
  I'll go and fix these so they still have a chance of working, at least.
  until the switch PHY support appears in -HEAD.

Submitted by:	Stefan Bethke <stb@lassitu.de>
2012-05-01 06:18:30 +00:00
Adrian Chadd
03cb2eedfd Migrate ARGE_DEBUG to opt_arge.h.
Submitted by:	Stefan Bethke <stb@lassitu.de>
2012-05-01 04:35:53 +00:00
Juli Mallett
379663d70b o) Use ABI, not ISA_* options, to determine whether to compile bits if libkern
required for the ABI the kernel is being built for.
   XXX This is implemented in a kind-of nasty way that involves including source
       files, but it's still an improvement.
o) Retire ISA_* options since they're unused and were always wrong.
2012-03-12 21:25:32 +00:00
Juli Mallett
9624d94701 o) Add COMPAT_FREEBSD32 support for MIPS kernels using the n64 ABI with userlands
using the o32 ABI.  This mostly follows nwhitehorn's lead in implementing
   COMPAT_FREEBSD32 on powerpc64.
o) Add a new type to the freebsd32 compat layer, time32_t, which is time_t in the
   32-bit ABI being used.  Since the MIPS port is relatively-new, even the 32-bit
   ABIs use a 64-bit time_t.
o) Because time{spec,val}32 has the same size and layout as time{spec,val} on MIPS
   with 32-bit compatibility, then, disable some code which assumes otherwise
   wrongly when built for MIPS.  A more general macro to check in this case would
   seem like a good idea eventually.  If someone adds support for using n32
   userland with n64 kernels on MIPS, then they will have to add a variety of
   flags related to each piece of the ABI that can vary.  That's probably the
   right time to generalize further.
o) Add MIPS to the list of architectures which use PAD64_REQUIRED in the
   freebsd32 compat code.  Probably this should be generalized at some point.

Reviewed by:	gonzo
2012-03-03 08:19:18 +00:00
Jayachandran C.
ae78a2ad86 MIPS changes for Netlogic XLP support.
This patch adds support for the Netlogic XLP mips64 processors in
the common MIPS code. The changes are :

- Add CPU_NLM processor type
- Add cases for CPU_NLM, mostly were CPU_RMI is used.
- Update cache flush changes for CPU_NLM
- Add kernel build configuration files for xLP.

In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com>

Approved by:	bz(re), jmallett, imp(mips)
2011-07-16 20:31:29 +00:00
Aleksandr Rybalko
a4e33603b2 Support of Ralink Ethernet MAC, used in RT3050F/RT3052F and I belive in other Ralink SoCs.
Approved by: adrian (mentor)
2011-07-11 08:23:59 +00:00
Adrian Chadd
ef2732b2ee Put the ARGE_DEBUG behind a kernel config option. 2011-04-05 05:29:10 +00:00
Warner Losh
071c626eed Nothing uses TARGET_EMULATOR, so gc it. 2010-08-15 19:07:44 +00:00
Jayachandran C.
a7834bac09 Rename TARGET_XLR_XLS to CPU_RMI to match other CPU_xxx definitions.
use CPU_RMI all XLR configurations. Update ident string for N32 and
N64 kernels.
2010-08-13 12:56:00 +00:00
Juli Mallett
cea2b8b915 Update the port of FreeBSD to Cavium Octeon to use the Cavium Simple Executive
library:
o) Increase inline unit / large function growth limits for MIPS to accommodate
   the needs of the Simple Executive, which uses a shocking amount of inlining.
o) Remove TARGET_OCTEON and use CPU_CNMIPS to do things required by cnMIPS and
   the Octeon SoC.
o) Add OCTEON_VENDOR_LANNER to use Lanner's allocation of vendor-specific
   board numbers, specifically to support the MR320.
o) Add OCTEON_BOARD_CAPK_0100ND to hard-wire configuration for the CAPK-0100nd,
   which improperly uses an evaluation board's board number and breaks board
   detection at runtime.  This board is sold by Portwell as the CAM-0100.
o) Add support for the RTC available on some Octeon boards.
o) Add support for the Octeon PCI bus.  Note that rman_[sg]et_virtual for IO
   ports can not work unless building for n64.
o) Clean up the CompactFlash driver to use Simple Executive macros and
   structures where possible (it would be advisable to use the Simple Executive
   API to set the PIO mode, too, but that is not done presently.)  Also use
   structures from FreeBSD's ATA layer rather than structures copied from
   Linux.
o) Print available Octeon SoC features on boot.
o) Add support for the Octeon timecounter.
o) Use the Simple Executive's routines rather than local copies for doing reads
   and writes to 64-bit addresses and use its macros for various device
   addresses rather than using local copies.
o) Rename octeon_board_real to octeon_is_simulation to reduce differences with
   Cavium-provided code originally written for Linux.  Also make it use the
   same simplified test that the Simple Executive and Linux both use rather
   than our complex one.
o) Add support for the Octeon CIU, which is the main interrupt unit, as a bus
   to use normal interrupt allocation and setup routines.
o) Use the Simple Executive's bootmem facility to allocate physical memory for
   the kernel, rather than assuming we know which addresses we can steal.
   NB: This may reduce the amount of RAM the kernel reports you as having if
       you are leaving large temporary allocations made by U-Boot allocated
       when starting FreeBSD.
o) Add a port of the Cavium-provided Ethernet driver for Linux.  This changes
   Ethernet interface naming from rgmxN to octeN.  The new driver has vast
   improvements over the old one, both in performance and functionality, but
   does still have some features which have not been ported entirely and there
   may be unimplemented code that can be hit in everyday use.  I will make
   every effort to correct those as they are reported.
o) Support loading the kernel on non-contiguous cores.
o) Add very conservative support for harvesting randomness from the Octeon
   random number device.
o) Turn SMP on by default.
o) Clean up the style of the Octeon kernel configurations a little and make
   them compile with -march=octeon.
o) Add support for the Lanner MR320 and the CAPK-0100nd to the Simple
   Executive.
o) Modify the Simple Executive to build on FreeBSD and to build without
   executive-config.h or cvmx-config.h.  In the future we may want to
   revert part of these changes and supply executive-config.h and
   cvmx-config.h and access to the options contained in those files via
   kernel configuration files.
o) Modify the Simple Executive USB routines to support getting and setting
   of the USB PID.
2010-07-20 19:25:11 +00:00
Warner Losh
bc49613a68 Add CPU_CNMIPS for the core that's in Octeon CPUs. 2010-02-25 11:54:10 +00:00
Neel Natu
40e359dc3a Get rid of unused options: KERNPHYSADDR, KERNVIRTADDR, PHYSADDR, PHYS_ADDR_64BIT
Discussed with: gonzo, imp
2010-02-20 06:39:14 +00:00
Neel Natu
9dcae110dc Remove the PCI_IOSPACE_SIZE and PCI_IOSPACE_ADDR hack from nexus.c. Implement
this in the Sibyte PCI hostbridge driver instead.

The nexus driver sees resource allocation requests for memory and irq
resources only. These are legitimate resources on all MIPS platforms.

Suggested by: imp
2010-02-12 02:59:49 +00:00
Warner Losh
97507d7183 Merge from projects/mips to head by hand:
r200593 | imp | 2009-12-15 16:22:19 -0700 (Tue, 15 Dec 2009) | 4 lines
Remove the now-obsolete comments about compile-with.  There are no
compile-with lines in this file at all.  So we don't need two warnings
about them.

r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines
With this commit our friend RMI will now compile. I have
not tested it and the chances of it running yet are about
ZERO.. but it will now compile. The hard part now begins,
making it run ;-)

r198311 | neel | 2009-10-20 18:56:13 -0600 (Tue, 20 Oct 2009) | 8 lines
Update options.mips to support config options required to build the SWARM
kernel.
The SWARM kernel does not build yet but at least it gets past the kernel
config stage.

r198154 | rrs | 2009-10-15 15:03:32 -0600 (Thu, 15 Oct 2009) | 10 lines
Does 4 things:
1) Adds future RMI directories
2) Places intr_machdep.c in specfic files.arch pointing to the generic
   intr_machdep.c.  This allows us to have an architecture dependant
   intr_machdep.c (which we will need for RMI) in the machine specific
   directory
3) removes intr_machdep.c from files.mips
4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We
   may need to look at finding a better place to put this. But first I want to
   get this thing compiling.

r196315 | imp | 2009-08-17 06:37:06 -0600 (Mon, 17 Aug 2009) | 5 lines
Like qdivrem, remove the other quad_t support stuff from 64-bit
kernels.

r195331 | imp | 2009-07-03 20:49:17 -0600 (Fri, 03 Jul 2009) | 4 lines
Merge in new cfe environment passing of kenv for swarm/sibyte boards.
Submitted by:   Neelkanth Natu

r195732 | gonzo | 2009-07-16 20:28:27 -0600 (Thu, 16 Jul 2009) | 2 lines
- Add DES and Blowfish implementstions to build. Required by crypto(4)

r195437 | imp | 2009-07-07 23:57:58 -0600 (Tue, 07 Jul 2009) | 2 lines
The kernel isn't quite ready for this to be optional...

r195401 | imp | 2009-07-06 02:16:25 -0600 (Mon, 06 Jul 2009) | 4 lines
Only build qdivrem on 32-bit ISA...

r195331 | imp | 2009-07-03 20:49:17 -0600 (Fri, 03 Jul 2009) | 4 lines
Merge in new cfe environment passing of kenv for swarm/sibyte boards.
Submitted by:   Neelkanth Natu

r195165 | gonzo | 2009-06-29 11:36:47 -0600 (Mon, 29 Jun 2009) | 2 lines
- add sys_machdep.c to build

r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines
- Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default
   we assume that there is no FPU, because majority of SoC does
   not have it.

r191085 | gonzo | 2009-04-14 20:41:35 -0600 (Tue, 14 Apr 2009) | 2 lines
- mainbus.c seems not to be used, disconnect it from build

r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines
Use FreeBSD/arm approach for handling bus space access: space tag is a pointer
to bus_space structure that defines access methods and hence every bus can
define own accessors. Default space is mips_bus_space_generic. It's a simple
interface to physical memory, values are read with regard to host system
byte order.

r187418 | gonzo | 2009-01-18 19:37:10 -0700 (Sun, 18 Jan 2009) | 4 lines
- Add trampoline stuff for bootloaders that do not support ELF
- Replace arm'ish KERNPHYSADDR/KERNVIRTADDR with
    KERNLOADADDR/TRAMPLOADADDR and clean configs

r187415 | gonzo | 2009-01-18 16:49:02 -0700 (Sun, 18 Jan 2009) | 3 lines
- Move Silicon Backplanes code out to system-wide level (dev/siba) as
    it's going to be used not only for siba5 devices.
2010-01-10 05:46:19 +00:00
Wojciech A. Koszek
8c96ef6247 Consistently use <TAB> instead of spaces as option name and file
separator.
2009-02-06 10:30:46 +00:00
Warner Losh
1ca5d948a3 Merge from p4: add Juniper license statement. 2008-09-19 03:36:37 +00:00
Warner Losh
b0c90d8c3d Merge in the mips specific configuration files and such from the
merged juniper and mips2 code base.  This represents the work of
Juniper Engineers, plus Oleksandr Tymoshenko, Wojciech Koszek, Warner
Losh, Olivier Houchard, Randall Stewert and others that have
contributed to the mips2 and/or mips2-jnpr perforce branches.
2008-04-13 06:25:43 +00:00