Commit Graph

72 Commits

Author SHA1 Message Date
John Baldwin
a28b3fc741 - Add a few more register defintions for the PCI express capability
registers.
- Cleanup PCI-X capability printf to not leave a dangling "supports" for
  some PCI-X bridges.
- Display additional PCI express details including the negotiated and max
  link width and the actual and maximum supported max payload.

MFC after:	1 month
2009-04-17 19:07:44 +00:00
John Baldwin
c4e8c9df9e Always read/write the full 64-bit value of 64-bit BARs. Specifically,
when determining the size of a BAR by writing all 1's to the BAR and
reading back the result, always operate on the full 64-bit size.

Reviewed by:	imp
MFC after:	1 month
2009-03-05 15:33:04 +00:00
Robert Noland
5884a846e7 Disable INTx when enabling MSI/MSIX
This addresses interrupt storms that were noticed after enabling MSI
in drm.  I think this is due to a loose interpretation of the PCI 2.3
spec, which states that a function using MSI is prohibitted from using
INTx.  It appears that some vendors interpretted that to mean that they
should handle it in hardware, while others felt it was the drivers
responsibility.

This fix will also likely resolve interrupt storm related issues with
devices other than drm.

Reviewed by:	jhb@
MFC after:	3 days
2009-03-02 19:00:41 +00:00
Alexander Motin
b8adaa5549 Add SATA and PCI Advanced Features capabilities constants. 2009-02-15 09:49:21 +00:00
John Baldwin
da1e0915c5 - Add a new ioctl to /dev/pci to fetch details on an individual BAR of a
device.  The details include the current value of the BAR (including all
  the flag bits and the current base address), its length, and whether or not
  it is enabled.  Since this operation is not invasive, non-root users are
  allowed to use it (unlike manual config register access which requires
  root).  The intention is that userland apps (such as Xorg) will use this
  interface rather than dangerously frobbing the BARs from userland to
  obtain this information.
- Add a new sub-mode to the 'list' mode of pciconf.  The -b flag when used
  with -l will now list all the active BARs for each device.

MFC after:	1 month
2009-02-02 19:54:16 +00:00
Warner Losh
8481e37b53 Nit: Add a few leading zeros to make this match other mask constants
in this file.  Also to make sure that I got other ASI constants right.
2008-11-03 15:38:45 +00:00
Alexander Motin
c5343d0981 Add HDA multimedia subclass. 2008-10-21 21:53:55 +00:00
John Baldwin
9c0e9e988e The config space registers holding the upper 32-bits of the prefetchable
memory area's base and limit are optional.  The low 4-bits of the "low"
prefetchable registers indicates whether or not a 32-bit or 64-bit
region is supported.  The PCI-PCI driver had been assuming that all bridges
supported a 64-bit region (and thus the two upper 32-bit registers).  Fix
the driver to only use those registers if the low 4-bits of the "low"
registers indicate that a 64-bit region is supported.  The PCI-PCI bridge
in the XBox happens to be a bridge that only supports a 32-bit region.

Reported by:	rink
MFC after:	1 week
2008-08-20 18:29:59 +00:00
Stephane E. Potvin
1a2952820d - Fix a small bit slip in PCIM_PCAP_D[0-2]PME defines.
- Add the definitions for D3PME_COLD and D3PME_HOT capabilities.

Reviewed by:	njl (mentor), imp
Approved by:	re (kensmith)
MFC after:	1 week
2007-09-19 13:05:58 +00:00
Warner Losh
4b3337405d Change PCIM_CIS_ASI_TUPLE to _CONFIG.
Add PCI_MAX_BAR_0
minor style nit.
Add PCIM_CIS_CONFIG_MASK
2007-05-16 18:42:38 +00:00
John Baldwin
d68b1825b7 - HT 2.00b added a new flag to the MSI mapping HT capability to indicate
that the MSI mapping window is fixed at 0xfee00000 and the capability
  does not include two more dwords used to program the address.  Supporting
  this mostly results in quieting spurious warnings during boot about
  non-default MSI mapping windows.
- HT 2.00b also added a new HT capability type, so support that in pciconf.

MFC after:	3 days
Tested by:	jmg
2007-04-25 14:45:46 +00:00
John Baldwin
4dc5078f81 Add constants for the fields in a BAR. Also, add two new macros
PCI_BAR_(IO|MEM)() that return true if the passed in value from a BAR
is for an IO or memory BAR, respectively.

Reviewed by:	imp
2007-03-31 21:39:02 +00:00
John Baldwin
657d9f9f55 - Add missing constants for subclasses.
- Add a few progif constants as well.
2007-03-31 20:41:00 +00:00
John Baldwin
976c400776 - Flesh out list of UART simple comms programming interfaces.
- Add list of PIC base peripheral programming interfaces.
- Add VPD capability register offsets.

MFC after:	3 days
2007-03-05 16:18:31 +00:00
John Baldwin
f50589d755 Add constants for the PCIY_VENDOR (vendor-specific), PCIY_DEBUG (EHCI
debug port), and PCIY_EXPRESS (PCI-express) capabilities.
2007-02-02 19:48:25 +00:00
John Baldwin
6eb7ebfe25 - Change the PCI-X registers constants to be relative to the PCI-X PCI
capability rather than hardcoded offsets for a particular card.  While
  I'm here, expand the constants some.
- Change the ahd(4) driver to use pci_find_extcap() to locate the PCI-X
  capability to keep up with the first change.

Reviewed by:	scottl, gibbs (earlier version)
2007-01-19 22:37:52 +00:00
John Baldwin
8bbeb21223 Fix the subvendor ID for PCI-PCI bridges.
- Retire the PCI_SUB*_1 constants and don't try to read a subvendor ID out
  of them.  There isn't a standard subvendor ID field for PCI-PCI bridges.
  Instead, the dword at offset 0x34 is actually mostly reserved except for
  the LSB which is the capabilities pointer.
- Add support for the PCI-PCI bridge subvendor ID capability (13) and use
  it to set the subvendor ID for PCI-PCI bridges.

MFC after:	 1 month
2007-01-16 17:04:42 +00:00
John Baldwin
2bbf9462ad Replace #define<space> with #define<tab> so the code is consistent with
style(9) and avoids mixing the two formats.
2006-12-14 16:53:48 +00:00
John Baldwin
3dcca30330 - Add constants for HT PCI capability registers including the various
subtypes of HT capabilities.
- Add constants for the MSI mapping window HT PCI capability.
- On i386 and amd64, enable the MSI mapping window on any HT bridges we
  encounter and report any non-standard mapping window addresses.
2006-12-12 19:33:25 +00:00
John Baldwin
9bf4c9c1b0 First cut at MI support for PCI Message Signalled Interrupts (MSI):
- Add 3 new functions to the pci_if interface along with suitable wrappers
  to provide the device driver visible API:
  - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI().  '*count'
    here is an in and out parameter.  The driver stores the desired number
    of messages in '*count' before calling the function.  On success,
    '*count' holds the number of messages allocated to the device.  Also on
    success, the driver can access the messages as SYS_RES_IRQ resources
    starting at rid 1.  Note that the legacy INTx interrupt resource will
    not be available when using MSI.  Note that this function will allocate
    either MSI or MSI-X messages depending on the devices capabilities and
    the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables.  Also note
    that the driver should activate the memory resource that holds the
    MSI-X table and pending bit array (PBA) before calling this function
    if the device supports MSI-X.
  - pci_release_msi(dev) backed by PCI_RELEASE_MSI().  This function
    releases the messages allocated for this device.  All of the
    SYS_RES_IRQ resources need to be released for this function to succeed.
  - pci_msi_count(dev) backed by PCI_MSI_COUNT().  This function returns
    the maximum number of MSI or MSI-X messages supported by this device.
    MSI-X is preferred if present, but this function will honor the
    'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables.  This function
    should return the largest value that pci_alloc_msi() can return
    (assuming the MD code is able to allocate sufficient backing resources
    for all of the messages).
- Add default implementations for these 3 methods to the pci_driver generic
  PCI bus driver.  (The various other PCI bus drivers such as for ACPI and
  OFW will inherit these default implementations.)  This default
  implementation depends on 4 new pcib_if methods that bubble up through
  the PCI bridges to the MD code to allocate IRQ values and perform any
  needed MD setup code needed:
  - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages.
  - PCIB_RELEASE_MSI() releases a group of MSI messages.
  - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message.
  - PCIB_RELEASE_MSIX() releases a single MSI-X message.
- Add default implementations for these 4 methods that just pass the
  request up to the parent bus's parent bridge driver and use the
  default implementation in the various MI PCI bridge drivers.
- Add MI functions for use by MD code when managing MSI and MSI-X
  interrupts:
  - pci_enable_msi(dev, address, data) programs the MSI capability address
    and data registers for a group of MSI messages
  - pci_enable_msix(dev, index, address, data) initializes a single MSI-X
    message in the MSI-X table
  - pci_mask_msix(dev, index) masks a single MSI-X message
  - pci_unmask_msix(dev, index) unmasks a single MSI-X message
  - pci_pending_msix(dev, index) returns true if the specified MSI-X
    message is currently pending
- Save the MSI capability address and data registers in the pci_cfgreg
  block in a PCI devices ivars and restore the values when a device is
  resumed.  Note that the MSI-X table is not currently restored during
  resume.
- Add constants for MSI-X register offsets and fields.
- Record interesting data about any MSI-X capability blocks we come
  across in the pci_cfgreg block in the ivars for PCI devices.

Tested on:	em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X)
Reviewed by:	scottl, grehan, jfv
MFC after:	2 months
2006-11-13 21:47:30 +00:00
Warner Losh
8cb2906936 Add a define for the Standard SD Host Controller Base Peripheral. 2006-05-30 21:36:12 +00:00
Warner Losh
8d10dd1a82 Make RID2BAR actually return a number that can be plugged into PCIR_BAR()
rather than a bitmask.

Submitted by: ru@
2005-12-30 20:25:40 +00:00
Warner Losh
b60c6f4683 Add a macro to map from BAR to rid # (inverse of PCIR_BARS). 2005-12-29 23:40:41 +00:00
John Baldwin
4f9795b9fe Add a new method PCI_FIND_EXTCAP() to the pci bus interface that is used
to search for a specific extended capability.  If the specified capability
is found for the given device, then the function returns success and
optionally returns the offset of that capability.  If the capability is
not found, the function returns an error.
2005-12-20 19:57:47 +00:00
Warner Losh
87623e8dd6 Use symbolic name rather thanhard coding the cap pointer offset for
type two devices.
2005-10-29 05:49:06 +00:00
Warner Losh
00b02fa185 Add PCIM_BIOS_ADDR_MASK too 2005-10-28 06:02:51 +00:00
Warner Losh
0ec342c524 Some cardbus CIS definitions moved here since they are PCI registers. 2005-10-28 05:57:10 +00:00
Warner Losh
f8749e3d9b As threatened by BURN_BRIDGES, restire PCIR_MAPS and PCIR_HEADERTYPE 2005-06-05 23:08:59 +00:00
Marcel Moolenaar
d1ee178775 Add defines for the Bridge Control Register bits.
Obtained from: jhb@
2005-04-29 01:58:27 +00:00
John-Mark Gurney
0e49742d03 fix misspelling of 0x30...
Spotted by:	reviewing MFC commit
2005-04-01 22:56:37 +00:00
John-Mark Gurney
1a82818b98 fix a copy/paste typo for scanner/gameport...
Spotted by:	Michal Mertl <mime@traveller.cz>
2005-03-26 22:17:48 +00:00
John-Mark Gurney
4ea3b0e7e2 add some additional pci classes and sub-classes..
Reviewed by:	imp (almost 6 months ago)
2005-03-26 20:31:09 +00:00
Warner Losh
098ca2bda9 Start each of the license/copyright comments with /*-, minor shuffle of lines 2005-01-06 01:43:34 +00:00
Scott Long
ec40a9f9d0 Teach the PCI code to parse MSI extended capabilities. Re-arrange the
pcicfg struct a bit to hold extcap structures instead of structure members.
2003-09-14 19:30:00 +00:00
Scott Long
3c358d0ca0 Expand the extended capabilities list and add definitions for MSI. 2003-09-14 14:42:26 +00:00
John Baldwin
b66752c4a1 Bring back PCIR_HEADERTYPE as an alias for PCIR_HDRTYPE under BURN_BRIDGES
for backwards compat.  The old name will be gone in 6.0, but will be
around in 5.x.  This will help unbreak 3rd party code, e.g. the nvidia
DRM module.
2003-09-03 17:48:22 +00:00
John Baldwin
56802c46e2 - Deprecate PCIR_MAPS under BURN_BRIDGES (meaning it will be gone in 6.0)
and replace it with the more intuitive name PCIR_BARS.
- Add a PCIR_BAR(x) macro that returns the config space register offset of
  the 32-bit BAR x.

MFC after:	3 days
2003-09-02 17:11:27 +00:00
John Baldwin
729d7ffbcf - Rename PCIx_HEADERTYPE* to PCIx_HDRTYPE* so the constants aren't so long.
- Add a new PCIM_HDRTYPE constant for the field in PCIR_HDRTYPE that holds
  the header type.
- Replace several magic numbers with appropriate constants for the header
  type register and a couple of PCI_FUNCMAX.
- Merge to amd64 the fix to the i386 bridge code to skip devices with
  unknown header types.

Requested by:	imp (1, 2)
2003-08-28 21:22:25 +00:00
John Baldwin
86889ca086 Add constants for capability IDs and header types.
Submitted by:	Samy Al Bahra <samy@kerneled.com>
2003-08-28 20:59:31 +00:00
Warner Losh
8d50cc0e3e Define PCI_MAXHDRTYPE to be 2. We know about header types 0, 1 and 2.
Update the MI device scanning code to use PCI_MAXHDRTYPE rather than
the hard coded 2.
2003-08-01 21:45:56 +00:00
Dag-Erling Smørgrav
bd9155712b Add constants for USB programming interfaces. These are already defined
(with other names) in the USB driver sources, but I felt that pcireg.h
should have a complete list - at least of classes and interfaces that we
know about and use.
2003-04-23 15:51:36 +00:00
Justin T. Gibbs
eda578ae9f Add some PCI-X register definitions.
PCIM_CMD_SERREN -> PCIM_CMD_SERRESPEN to be consistent with
the PERR definition.
2002-06-05 22:25:51 +00:00
Justin T. Gibbs
98f89aa0a9 Add PCIR_CAP_PTR as a define for the location of the capability
pointer of type 0 devices.  This is required by my last aic7xxx change.
2000-12-20 14:36:52 +00:00
Mike Smith
8983cfbf27 Next round of PCI subsystem updates:
- Break out the /dev/pci driver into a separate file.
 - Kill the COMPAT_OLDPCI support.
 - Make the EISA bridge attach a bit more like the old code; explicitly
   check for the existence of eisa0/isa0 and only attach if they don't
   already exist.  Only make one bus_generic_attach() pass over the
   bridge, once both busses are attached.  Note that the stupid Intel
   bridge's class is entirely unpredictable.
 - Add prototypes and re-layout the core PCI modules in line with
   current coding standards (not a major whitespace change, just moving
   the module data to the top of the file).
 - Remove redundant type-2 bridge support from the core PCI code; the
   PCI-CardBus code does this itself internally.  Remove the now
   entirely redundant header-class-specific support, as well as the
   secondary and subordinate bus number fields.  These are bridge
   attributes now.
 - Add support for PCI Extended Capabilities.
 - Add support for PCI Power Management.  The interface currently
   allows a driver to query and set the power state of a device.
 - Add helper functions to allow drivers to enable/disable busmastering
   and the decoding of I/O and memory ranges.
 - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some
   places.
 - Make the PCI-PCI bridge code a little more paranoid about valid
   I/O and memory decodes.
 - Add some more PCI register definitions for the command and status
   registers.  Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
Mike Smith
4fa59183f1 - We have access to our own device_t here, so use pci_read_config
rather than finding our parent pcib and using its PCI_READ_CONFIG
   method.

 - Fix the defines for the 32-bit I/O decode registers, and properly
   process the 16-bit versions.  Now we will correctly check that I/O
   resources behind the bridge are going to be decoded.

 - Bring the quirk for the Orion PCI:PCI bridge in here (since it
   seems to want to set the secondary/supplementary bus numbers).

 - Use PCI_SLOTMAX rather than a magic number.
2000-12-12 13:20:35 +00:00
Archie Cobbs
645d61ffeb Add definition for PCIS_SERIALBUS_SMBUS PCI device subclass.
Remove cut & paste leftovers.
2000-10-02 00:41:43 +00:00
Justin T. Gibbs
cb4d93cdbf Add PCIM_CMD_MWRICEN, the bit in the command register in PCI space
that enables memory write and invalidate cycles on a bus master.
2000-09-16 20:06:13 +00:00
Peter Wemm
30d1c11e3a Encapsulate the old PCI compatability support and APIs completely under
"options COMPAT_OLDPCI".  This option already existed, but now also tidies
up the declarations in #include <pci/pci*.h>.  It is amazing how much stuff
was using the old pre-FreeBSD 3.x names and going silently undetected.
2000-05-28 16:35:57 +00:00
Kazutaka YOKOTA
689e7081eb Added PCIR_BIOS (0x30). 2000-01-10 12:53:19 +00:00
Peter Wemm
649f6f6393 Add the 16550 programming interface code for PCIS_SIMPLECOMM_UART. 1999-10-09 16:00:56 +00:00