U-Boot will leave the ephy reset de-asserted and the MAC soft reset will
fail on these boards with internal PHY and no link established. Toggle reset
again before proceeding to attach/init.
MFC after: 1 week
This was intended to fix the soft reset timeout on boot for OrangePi One/R1
with internal PHY, but seems to cause other problems later on due to soft
resetting around some state changes that may or may not make the NIC
non-functional.
Reverting this for now while a better solution is sought out.
From NetBSD: Since the MAC can get stuck in reset state with no link, ignore
reset timeouts and continue with initializing the device.
Fixes "soft reset timeout" issue at boot with no network cable plugged in.
awg_init may be called multiple times throughout normal interface usage, so
the tx/rx descriptor base address registers must be written after each MAC
reset and are moved as such.
This problem has been observed on FreeBSD, H3/H2+ devices with an internal
PHY (includes OrangePi R1, OrangePi One at least).
Reviewed by: manu, ganbold
Obtained from: NetBSD
MFC after: 2 weeks
Differential Revision: https://reviews.freebsd.org/D18844
Rework aw_sid so it can work with the nvmem interface.
Each SoC expose a set of fuses (for now rootkey/boardid and, if available,
the thermal calibration data). A fuse can be private or public, reading private
fuse needs to be done via some registers instead of reading directly.
Each fuse is exposed as a sysctl.
For now leave the possibility for a driver to read any fuse without using
the nvmem interface as the awg and emac driver use this to generate a mac
address.
Split out delay parsing into a separate function; we'll support both
{tx,rx}-delay as well as the new versions.
While here, validate that they're within the expected range and fail to
attach if they are not. Assuming that we can clamp the delay is a bad idea
that might result in a non-working awg anyways, so we'll fail early to make
it easier to catch.
This version also unsets the tx and rx delay registers unconditionally and
then sets them if we read a non-zero delay. These delay properties should
default to 0 if not specified, as declared in the binding documentation.
Presumably the delays will be set via hardware configuration if they're not
explicitly set in FDT.
OF_getprop_alloc takes element size argument and returns number of
elements in the property. There are valid use cases for such behavior
but mostly API consumers pass 1 as element size to get string
properties. What API users would expect from OF_getprop_alloc is to be
a combination of malloc + OF_getprop with the same semantic of return
value. This patch modifies API signature to match these expectations.
For the valid use cases with element size != 1 and to reduce
modification scope new OF_getprop_alloc_multi function has been
introduced that behaves the same way OF_getprop_alloc behaved prior to
this patch.
Reviewed by: ian, manu
Differential Revision: https://reviews.freebsd.org/D14850
On the OrangePi One at least, emac reset when an ethernet cable is not
plugged in seems to break ethernet. Soft reset will fail, even with
increasing the delay and retries to wait for up to 20 seconds. This can be
reproduced across at least two different OrangePi One's by simply leaving
ethernet cable unplugged when awg attaches. Whether it's plugged in or not
through u-boot process makes no difference.
Skipping the reset in this configuration doesn't seem to cause any problems,
tried across many many reboots with and without ethernet cable plugged in.
Tested on: OrangePi One
Tested on: Other boards (manu)
Reviewed by: manu
Differential Revision: https://reviews.freebsd.org/D13974
Highlights of the new bindings:
- ahb clock is specified as 'stmmaceth'
- The PHY to be used is now specified as phy-handle
- We must now check the parent of the node phy-handle points to in order to
discover if we're using internal PHY.
- The ephy clk/reset will be specified on the PHY node, not the emac node.
Care has been taken to ensure that we remain compatible with the older
bindings that we were previously using.
Tested on: Pine64 (A64, old bindings)
Tested on: Pine64-LTS (A64, new bindings) [manu]
Tested on: OrangePi-One (H3, internal PHY) [manu]
Tested on: NanoPi M1 Plus (H3, external PHY) [manu]
Reviewed by: manu
Differential Revision: https://reviews.freebsd.org/D13777
The emac bindings that are landing in Linux 4.15 specify a syscon property
on the emac node that point to /soc/syscon. Use this property if it's
specified, but maintain backwards compatibility with the old method.
The older method is still used for boards that we get .dtb from u-boot, such
as pine64, that did not yet have stable emac bindings.
Tested on: Banana Pi-M3 (a83t)
Tested on: Pine64 (a64)
Reviewed by: manu
Differential Revision: https://reviews.freebsd.org/D13296
phy-mode can be one of: rgmii, rgmii-id, rgmii-txid, rgmii-rxid; as this was
written, any of these alternate -id configurations would break as we fail to
configure syscon for rgmii. Instead, simply check that phy-mode is
configured for rgmii and we'll let the PHY driver handle any internal delay
configuration.
The pine64 should eventually specify phy-mode = "rgmii-txid" to address
gigabit issues when rx delay is configured, motivating this change.
This reduces noise when kernel is compiled by newer GCC versions,
such as one used by external toolchain ports.
Reviewed by: kib, andrew(sys/arm and sys/arm64), emaste(partial), erj(partial)
Reviewed by: jhb (sys/dev/pci/* sys/kern/vfs_aio.c and sys/kern/kern_synch.c)
Differential Revision: https://reviews.freebsd.org/D10385
Stale packets should not be transmitted when the interface comes up after being down.
Count the successfully transmitted ones for statistics and drop the rest.
Submitted by: Guy Yur <guyyur@gmail.com>
Differential Revision: https://reviews.freebsd.org/D12539
Use a spare dma map when attempting to map a new mbuf on the rx path.
If the mbuf allocation fails or the dma map loading for the new mbuf fails just reuse the old mbuf
and increase the drop counter.
Submitted by: Guy Yur <guyyur@gmail.com>
Differential Revision: https://reviews.freebsd.org/D12538
- use awg_encap and awg_txeof names to match iflib and other network drivers.
- handle m_collapse failure similarly by freeing the mbuf rather than reenqueuing it where it will continue to fail.
Submitted by: Guy Yur <guyyur@gmail.com>
Differential Revision: https://reviews.freebsd.org/D13035
TX_BUF_UA_INT is set when there are no buffers to transmit and can
happen before hw.awg.tx_interval segments have been transmitted.
To reduce load, tx cleanup should be done in hw.awg.tx_interval intervals.
Submitted by: Guy Yur <guyyur@gmail.com>
Differential Revision: https://reviews.freebsd.org/D13034
A packet may be built from multiple segments, don't increase the count for each segment
Submitted by: Guy Yur <guyyur@gmail.com>
Differential Revision: https://reviews.freebsd.org/D13032
According to the datasheet, TX_DESC_CTL is cleared when whole frame is transmitted or all
data in the current descriptor's buffer are transmitted.
When the mbuf and mapping are stored in the first segment and in a scenario where a tx
completion interrupt arrives for a frame and only the start of the next frame was transmitted,
at the time of interrupt processing the mbuf and mapping will be freed when processing the
first segment of the next frame but the other untrasmitted segments still need to use them.
Submitted by: Guy Yur <guyyur@gmail.com>
Differential Revision: https://reviews.freebsd.org/D13031
In a multi segment frame, if the first tx descriptor is marked with TX_DESC_CTL
but not all tx descriptors for the other segments in the frame are set up,
the TX DMA may transmit an incomplete frame.
To prevent this, set TX_DESC_CTL for the first tx descriptor only when done
with all the other segments.
Also, don't bother cleaning transmitted tx descriptors since TX_DESC_CTL
is cleared for them by the hardware and they will be reprogrammed before
TX_DESC_CTL is reenabled for them.
Submitted by: Guy Yur <guyyur@gmail.com>
Differential Revision: https://reviews.freebsd.org/D13030
The hardware will not issue a completion interrupt for a descriptor
with TX_INT_CTL set if it doesn't also have TX_LAST_DESC set.
Submitted by: Guy Yur <guyyur_gmail.com>
Differential Revision: https://reviews.freebsd.org/D13029
Under certain traffic pattern awg driver does not recover from TX queue
full condition. The actual source of the problem is not identified yet
but jmcneill@ agreed that bumping TX_MAX_SEGS to 20 is OK as a workaround
for the problem (NetBSD has it set to 128).
Also add some diagnostic printfs to prevent silent failure of bus_dma
functions in the future
PR will be kept open until root cause of the issue is identified and fixed
PR: 219927
Submitted by: Tom Vijlbrief <tvijlbrief@gmail.com>
Approved by: jmcneill
MFC after: 2 weeks
H3 EMAC is the same as A83T/A64 except the SoC includes an (optional)
internal 10/100 PHY. Both internal and external PHYs are supported on H3
with this driver.
- Support DEVICE_POLLING
- Increase TX descriptors to 1024
- Add support for passing a chain of mbufs to if_input, reducing the
number of calls to mtx_unlock/mtx_lock under load.
- Remove duplicate byteswap when setting TX_INT_CTL in TX descriptor.
- Set undocumented "TX_NEXT_FRAME" bit in TX control 1 register.
According to the A83T BSP, setting this bit allows the DMA engine to
operate on a packet while receiving another.
Tested on A83T (1000Mbps PHY) and H3 (100Mbps PHY).
Reviewed by: manu
Differential Revision: https://reviews.freebsd.org/D7031
In some cases, the driver must handle given properties located in
specific OF subnode. Instead of creating duplicate set of function, add
'node' as argument to existing functions, defaulting it to device OF node.
MFC after: 3 weeks
The datasheets refer to this controller as EMAC, not to be confused with
the fast ethernet controller (also named EMAC) found in A10/A20 SoCs.
Tested on a BananaPi M3 (A83T), which uses an external RGMII PHY (RTL8211E).
Reviewed by: adrian
Differential Revision: https://reviews.freebsd.org/D6169
