Commit Graph

159 Commits

Author SHA1 Message Date
Andrew Turner
14df39ad40 Add support for a generic AHCI attachment. This allows us to attach to a
typically memory mapped bus, for example on the AMD Opteron A1100 the AHCI
device is mapped in the CPUs address space, and not through a PCI
controller.

Further work is needed for this to work with ACPI as this is expected to be
common on ARMv8 servers.

Reviewed by:	mav, mmel
Obtained from:	mmel, ABT Systems Ltd
Relnotes:	yes
Sponsored by:	SoftIron Inc
Differential Revision:	https://reviews.freebsd.org/D4269
2015-12-03 11:24:11 +00:00
Michal Meloun
d3214e8d6d AHCI: Fix AHCI driver for ARM.
On ARM, we must ensure proper interdevice write ordering.
The AHCI interrupt status register must be updated in HW before
registers in interrupt controller.
Unfortunately, only way how we can do it is readback.

Discussed with:	mav
Approved by:	kib (mentor)
Differential Revision: https://reviews.freebsd.org/D4240
2015-11-29 11:28:04 +00:00
Michal Meloun
b1d2c95e1c AHCI: Use bus_dmamap_sync(9) when accessing DMA buffers.
Reviewed by:	mav
Approved by:	kib (mentor)
Differential Revision: https://reviews.freebsd.org/D4240
2015-11-28 14:30:42 +00:00
Alexander Motin
98ef2a6198 Allow AHCI driver attach to all known chips reporting RAID class.
Reported by:	Michael BlackHeart <amdmiek@gmail.com>
MFC after:	1 week
2015-09-22 15:06:26 +00:00
Zbigniew Bodek
0af6011a92 Introduce support for MSI-X interrupts in AHCI
- Allocate resources for MSI-X table and PBA if necessary
- Add function ahci_free_mem() to free all resources

Reviewed by:   jhb, mav
Obtained from: Semihalf
Sponsored by:  The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D3009
2015-07-22 09:46:22 +00:00
Steven Hartland
64ce6b09a3 Correct bit offsets for ahci quirks
Fix bit offsets causing incorrect quirks being reported on boot for ahci
introduced by r280184.

MFC after:	3 days
Sponsored by:	Multiplay
2015-07-06 09:44:07 +00:00
Luiz Otavio O Souza
7ec8c789c3 Add AHCI attachment code for Allwinner A10/A20 SoCs.
The Allwinner SoC has an AHCI device on its internal main bus rather
than the PCI bus.  This SoC is somewhat underdocumented, and its SATA
controller is no exception.  The methods to support this chip were
harvested from the Linux Allwinner SDK, and then constants invented to
describe what's going on based on low-level constants contained in the
SATA standard and guess work.

This SoC requires a specific AHCI channel setup in order to start the
operations on the channel properly.

Clock setup and AHCI channel setup idea came from NetBSD.

Tested on Cubieboard 2 and Banana pi (and attachment on Cubieboard by
Pratik Singhal).

Differential Revision:	https://reviews.freebsd.org/D737
Submitted by:	imp
Reviewed by:	imp, ganbold, mav, andrew
2015-07-03 14:11:01 +00:00
Alexander Motin
556e4c9a83 Disable port multiplier support on Marvell 88SE61xx chips.
According to report, some recent unrelated changes in the driver triggered
timeouts when testing for absent port multiplier.  Cause of this behavior
channge is unclear, but since these chips are old, rare and buggy, it is
easier to just disable port multiplier support, same as done in Linux.

Reported by:	bar
MFC after:	3 days
2015-07-02 08:25:45 +00:00
Alexander Motin
e18af60507 Restore AHCI quirks printing as base16.
smh@ at r278034 made it base17, that is somewhat odd. :)

MFC after:	3 days
2015-06-02 23:11:12 +00:00
Alexander Motin
3036de3c48 Reduce priority of ATA/SATA drivers.
Legacy ata(4) -> BUS_PROBE_LOW_PRIORITY;  more functional ahci(4), siis(4),
mvs(4) -> BUS_PROBE_DEFAULT;  BUS_PROBE_VENDOR leave for vendor drivers.

MFC after:	2 weeks
2015-03-23 19:47:52 +00:00
Zbigniew Bodek
731a8268c5 Introduce Annapurna Labs AHCI support
Overview:
* implemented quirk for forcing SATA interface enable
* restore value to status register - this enables link autonegotiation

Modifications:
* devid:vendorid field
* quirk for forcing PI setting (BIOS is doing that on PC-like systems)
* write to capabilites field to enable phy link initialization

Submitted by:  Wojciech Macek <wma@semihalf.com>
Reviewed by:   imp, mav
Obtained from: Semihalf
2015-03-17 18:59:47 +00:00
Alexander Motin
c21b342b8e Fix SATA Gen3 speed constants.
MFC after:	1 week
2015-03-13 20:08:35 +00:00
Ed Maste
4e56f96440 Update ThunderX SATA quirk
Add quirk to ThunderX AHCI forcing only 1 MSI-X interrupt.
  Shorten Thunder quirk description to avoid printing 'SATA' twice.

Obtained from:	Semihalf
Sponsored by:	The FreeBSD Foundation
2015-03-04 02:17:36 +00:00
Alexander Motin
3e78ee6328 For some uniformity move ahci_ch_init() call under the lock.
Submitted by:	Dmitry Luhtionov <dmitryluhtionov@gmail.com>
MFC after:	2 weeks
2015-02-26 12:51:05 +00:00
Steven Hartland
b1877a0b39 Add a quirk to limit AHCI MSI vectors to one
In 10.1-RELEASE the default number of MSI vectors used was changed from one
to as many vectors as the HW supports.

This change resulted in an ahci timeouts regression when running on AMD
SB7x0/SB8x0/SB9x0 hardware, so its now limited to 1 MSI by default using
this new quirk.

MFC after:	2 weeks
Sponsored by:	Multiplay
2015-02-01 20:00:08 +00:00
Konstantin Belousov
43d5c9f65a Complete r277100: add AHCI_Q_ABAR0 tp AHCI_Q_BIT_STRING.
Noted and reviewed by:	smh
MFC after:	6 days
2015-01-13 09:50:15 +00:00
Konstantin Belousov
378c532c1f Add quirk to override default BAR(5) rid for AHCI.
Use it for Cavium AHCI.

Submitted by:	Michaе┌ Stanek
Reviewed by:	imp (previous version)
MFC after:	1 week
2015-01-13 00:11:56 +00:00
Marius Strobl
21190895ab - Const'ify the ahci_ids table.
- Use DEVMETHOD_END.
- Use NULL instead of 0 for pointers.

MFC after:	3 days
2014-12-28 20:42:28 +00:00
Steven Hartland
e4a8f2e2ec style (9) nits
Use return (val); instead of return val;

Differential Revision:	D838
MFC after:	2 weeks
Sponsored by:	Multiplay
2014-12-21 16:38:29 +00:00
Steven Hartland
5f59ea478e Return the error from ahci_setup_interrupt in ahci_attach
Previously ahci_attach returned a hard coded ENXIO instead of the value
from ahci_setup_interrupt. This is effectively a NOOP change as currently
ahci_setup_interrupt only ever returns 0 or ENXIO, so just there to protect
against any future changes to that.

Differential Revision:	D838
MFC after:	2 weeks
Sponsored by:	Multiplay
2014-12-21 16:32:57 +00:00
Steven Hartland
a12f5777df Clamp ahci max irq's to AHCI_MAX_IRQS
This prevents the possiblity of any overruns on the statically allocated
struct irqs field.

Differential Revision:	D838
MFC after:	2 weeks
X-MFC-With:	r276012
Sponsored by:	Multiplay
2014-12-21 16:15:29 +00:00
Steven Hartland
55972826f2 Add a constant AHCI_MAX_IRQS removing magic number
Sponsored by:	Multiplay
2014-12-21 16:07:46 +00:00
Alexander Motin
e67f3bec39 Add bunch of PCI IDs of Intel Wildcat Point (9 Series) chipsets.
MFC after:	1 week
2014-11-26 04:23:21 +00:00
Steven Hartland
85c9dd9d89 Prevent overflow issues in timeout processing
Previously, any timeout value for which (timeout * hz) will overflow the
signed integer, will give weird results, since callout(9) routines will
convert negative values of ticks to '1'. For unsigned integer overflow we
will get sufficiently smaller timeout values than expected.

Switch from callout_reset, which requires conversion to int based ticks
to callout_reset_sbt to avoid this.

Also correct isci to correctly resolve ccb timeout.

This was based on the original work done by Eygene Ryabinkin
<rea@freebsd.org> back in 5 Aug 2011 which used a macro to help avoid
the overlow.

Differential Revision:	https://reviews.freebsd.org/D1157
Reviewed by:	mav, davide
MFC after:	1 month
Sponsored by:	Multiplay
2014-11-21 21:01:24 +00:00
Ian Lepore
faab4473eb A dma tag alignment should be 1 (not 0) when a device can dma at any address. 2014-11-06 18:15:16 +00:00
Alexander Motin
88971a900d Use r271207 optimization only for MSI-enabled HBAs.
It was found that VirtualBox' AHCI does not allow nterrupt to be cleared
before the interrupt status register is read, causing interrupt storm.

AHCI specification allows to skip this register use when multi-vector MSI
is enabled and so interrupting port is known.  For single-vector MSI that
is not stated explicitly, but if the port is only one, it is obviously
known too.
2014-10-06 10:58:54 +00:00
Steven Hartland
6e9a599b27 Use a local STAILQ for unlocked done CCB processing in ahci direct mode
Previously it was possible for issues e.g. use after free, to result
from processing the done queue while not holding the channel lock.

While this should never happen in practice, unexpected code flows
which result in two threads processing from the same queue may
be possible.

We now use a local STAILQ to prevent this ever being an issue.

Sponsored by:	Multiplay
2014-09-27 19:14:22 +00:00
Alexander Motin
6e88c2c572 Initialize variables before resource_int_value().
Submitted by:	Dmitry Luhtionov <dmitryluhtionov@gmail.com>
2014-09-12 08:37:21 +00:00
Alexander Motin
03d89c944a Add PCI ID for Promise TX8660 8-port 3Gbps HBA.
This device reports RAID subclass, but appears to be AHCI compatible.

Submitted by:	Yuri Perejilin <yuri@rivera.ru>
MFC after:	1 week
2014-09-10 19:53:31 +00:00
Alexander Motin
fcd7f38fb0 Bunch of microoptimizations to reduce dereferences and cache collisions. 2014-09-08 12:11:49 +00:00
Alexander Motin
c45ff92177 Save one register read (AHCI_IS) for AHCI controllers with only one port.
For controllers with only one port (like PCIe or M.2 SSDs) interrupt can
come from only one source, and skipping read saves few percents of CPU time.

MFC after:	1 month
H/W donated by:	I/O Switch
2014-09-06 19:43:48 +00:00
Warner Losh
4acab041dd Restore order of interrupt setup. Minor problems can result by
setting up the interrupts too early:

Reviewed by: mav@
Sponsored by: Netflix
2014-09-06 18:20:50 +00:00
Alexander Motin
985da6db1c Fix typo in comments.
Submitted by:	Benedict Reuschling <bcr@FreeBSD.org>
MFC after:	6 days
2014-09-06 15:37:55 +00:00
Alexander Motin
c6efb4c41d Invert AHCI_Q_NOBSYRES quirk meaning, waiting for readiness by default.
I gave up to update list of Marvell chips that require this quirk.
The final nail was growing number of PCIe/M.2 SSDs where Marvell chips
have PCI IDs of different vendors.

MFC after:	1 week
H/W donated by:	I/O Switch
2014-09-05 13:45:14 +00:00
Warner Losh
802df3ace6 Separate out PCI attachment from the main AHCI driver. Move checks of
PCI IDs into quirks, which mostly fit (though you'd get no argument
from me that AHCI_Q_SATA1_UNIT0 is oddly specific). Set these quirks
in the PCI attachment. Make some shared functions public so that PCI
and possibly other bus attachments can use them.

The split isn't perfect yet, but it is functional. The split will be
perfected as other bus attachments for AHCI are written.

Sponsored by: Netflix
Reviewed by: kan, mav
Differential Revision: https://reviews.freebsd.org/D699
2014-09-04 22:22:53 +00:00
Warner Losh
0375d6f5f9 We were returning 20 bytes as the FIS size to send, but only
initializing 16. Initialize all 20 so we don't send garbage in the
Auxiliary register. The SATA standard mandates a 5 dword length for
the Host to Device FIS.

Sponsored by: Netflix
2014-08-30 02:13:09 +00:00
John Baldwin
a2677ff239 Don't bother clearing maps for static DMA allocations to NULL. Instead,
leave them as purely opaque values that are only set by bus_dmamem_alloc().
2014-06-17 18:10:06 +00:00
Alexander Motin
48ecfdc414 Correct AMD chipsets identification.
Submitted by:	Dmitry Luhtionov <dmitryluhtionov@gmail.com>
MFC after:	2 weeks
2014-04-17 14:16:02 +00:00
Alexander Motin
3fcad654e2 Add ID for one more ASMedia AHCI-compatible controller.
Reported by:	ignace.peeters@gmail.com
MFC after:	2 weeks
2014-01-17 17:16:49 +00:00
Zbigniew Bodek
b1c5afbb2f Revert r260165: Proper configuration of unmapped_buf_allowed should be used
To avoid failures in bus_dmamap_sync() on ARM unmapped_buf_allowed should
be set to 0. Hence, ARM-specific changes in AHCI should not be applied.
2014-01-02 11:24:04 +00:00
Zbigniew Bodek
49390e758d Use only mapped BIOs on ARM
Using unmapped BIOs causes failure inside bus_dmamap_sync, since
this function requires valid MVA address, which is not present
if mapping is not set up.

Submitted by:	Wojciech Macek <wma@semihalf.com>
Obtained from:	Semihalf
2014-01-01 20:26:08 +00:00
Zbigniew Bodek
df2ec2e4fb Do not attach to PCI bridges in AHCI driver
Some vendors use the same VID:PID combination in AHCI and PCI bridge cards

Submitted by:	Wojciech Macek <wma@semihalf.com>
Obtained from:	Semihalf
2014-01-01 20:18:03 +00:00
Alexander Motin
8adff99c8d Destroy mtx lock when failed to allocate memory during attach.
Submitted by:	Dmitry Luhtionov <dmitryluhtionov@gmail.com>
MFC after:	2 weeks
2013-12-11 17:40:35 +00:00
Eitan Adler
7a22215c53 Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this
shifts into the sign bit.  Instead use (1U << 31) which gets the
expected result.

This fix is not ideal as it assumes a 32 bit int, but does fix the issue
for most cases.

A similar change was made in OpenBSD.

Discussed with:	-arch, rdivacky
Reviewed by:	cperciva
2013-11-30 22:17:27 +00:00
Alexander Motin
9a6b4cb929 Add few more minor parts of DevSleep support from AHCI 1.3.1 proposal. 2013-11-15 15:14:07 +00:00
Alexander Motin
eda36fb4f5 Add some more IDs for Intel ATA, AHCI and USB controllers. 2013-11-15 10:28:59 +00:00
Alexander Motin
227d67aa54 Merge CAM locking changes from the projects/camlock branch to radically
reduce lock congestion and improve SMP scalability of the SCSI/ATA stack,
preparing the ground for the coming next GEOM direct dispatch support.

Replace big per-SIM locks with bunch of smaller ones:
 - per-LUN locks to protect device and peripheral drivers state;
 - per-target locks to protect list of LUNs on target;
 - per-bus locks to protect reference counting;
 - per-send queue locks to protect queue of CCBs to be sent;
 - per-done queue locks to protect queue of completed CCBs;
 - remaining per-SIM locks now protect only HBA driver internals.

While holding LUN lock it is allowed (while not recommended for performance
reasons) to take SIM lock.  The opposite acquisition order is forbidden.
All the other locks are leaf locks, that can be taken anywhere, but should
not be cascaded.  Many functions, such as: xpt_action(), xpt_done(),
xpt_async(), xpt_create_path(), etc. are no longer require (but allow) SIM
lock to be held.

To keep compatibility and solve cases where SIM lock can't be dropped, all
xpt_async() calls in addition to xpt_done() calls are queued to completion
threads for async processing in clean environment without SIM lock held.

Instead of single CAM SWI thread, used for commands completion processing
before, use multiple (depending on number of CPUs) threads.  Load balanced
between them using "hash" of the device B:T:L address.

HBA drivers that can drop SIM lock during completion processing and have
sufficient number of completion threads to efficiently scale to multiple
CPUs can use new function xpt_done_direct() to avoid extra context switch.
Make ahci(4) driver to use this mechanism depending on hardware setup.

Sponsored by:	iXsystems, Inc.
MFC after:	2 months
2013-10-21 12:00:26 +00:00
Gavin Atkinson
0d9bc65de7 Support the PCI-Express SSD in the new MacBook Air (model A1465)
Submitted by:	Johannes Lundberg <johannes brilliantservice.co.jp>
MFC after:	3 days
2013-08-28 14:29:33 +00:00
Alexander Motin
48f2741c29 Decode some bits defined in AHCI 1.3.1 Device Sleep Technical Proposal.
For now this is only conmetics to report HBA capabilities (Haswell?).

Submitted by:	Dmitry Luhtionov <dmitryluhtionov@gmail.com>
2013-07-25 10:29:40 +00:00
Jack F Vogel
428e286da3 Add new Coleto Creek device support: SATA, SMBus, and Watchdog devices.
MFC after: 1 week
2013-07-19 21:37:40 +00:00