Commit Graph

106 Commits

Author SHA1 Message Date
John Baldwin
82cb5c3b5b Native PCI-express HotPlug support.
PCI-express HotPlug support is implemented via bits in the slot
registers of the PCI-express capability of the downstream port along
with an interrupt that triggers when bits in the slot status register
change.

This is implemented for FreeBSD by adding HotPlug support to the
PCI-PCI bridge driver which attaches to the virtual PCI-PCI bridges
representing downstream ports on HotPlug slots. The PCI-PCI bridge
driver registers an interrupt handler to receive HotPlug events. It
also uses the slot registers to determine the current HotPlug state
and drive an internal HotPlug state machine. For simplicty of
implementation, the PCI-PCI bridge device detaches and deletes the
child PCI device when a card is removed from a slot and creates and
attaches a PCI child device when a card is inserted into the slot.

The PCI-PCI bridge driver provides a bus_child_present which claims
that child devices are present on HotPlug-capable slots only when a
card is inserted. Rather than requiring a timeout in the RC for
config accesses to not-present children, the pcib_read/write_config
methods fail all requests when a card is not present (or not yet
ready).

These changes include support for various optional HotPlug
capabilities such as a power controller, mechanical latch,
electro-mechanical interlock, indicators, and an attention button.
It also includes support for devices which require waiting for
command completion events before initiating a subsequent HotPlug
command. However, it has only been tested on ExpressCard systems
which support surprise removal and have none of these optional
capabilities.

PCI-express HotPlug support is conditional on the PCI_HP option
which is enabled by default on arm64, x86, and powerpc.

Reviewed by:	adrian, imp, vangyzen (older versions)
Relnotes:	yes
Differential Revision:	https://reviews.freebsd.org/D6136
2016-05-05 22:26:23 +00:00
Wojciech Macek
a2862b1169 Add support for Enhanced Allocation in pciconf
* Modified pciconf to print EA capability structure
 * Added register description to pcireg.h

Obtained from:         Semihalf
Sponsored by:          Cavium
Approved by:           cognet (mentor)
Reviewed by:           jhb
Differential revision: https://reviews.freebsd.org/D5440
2016-02-26 08:35:04 +00:00
Zbigniew Bodek
1e92574faa Fix invalid root link detection in mv_pci driver
mv_pci driver omitted slot 0, which can be valid device on Armada38x.
New mechanism detects if device is root link, basing on vendor's
and device's IDs.
It is restricted to Armada38x; on other machines, behaviour remains
the same.

Reviewed by:    andrew
Obtained from:  Semihalf
Sponsored by:   Stormshield
Submitted by:   Bartosz Szczepanek <bsz@semihalf.com>
Differential revision:  https://reviews.freebsd.org/D4377
2016-01-20 14:05:21 +00:00
John Baldwin
15d107308f Add a new -B flag for use with list mode (-l) that lists details about
bridges.  Currently this includes information about what resources a
bridge decodes on the upstream side for use by downstream devices including
bus numbers, I/O port resources, and memory resources.  Windows and bus
ranges are enumerated for both PCI-PCI bridges and PCI-CardBus bridges.

To simplify the implementation, all enumeration is done by reading the
appropriate config space registers directly rather than querying the
bridge driver in the kernel via new ioctls.  This does result in a few
limitations.

First, an unimplemented window in a PCI-PCI bridge cannot be accurately
detected as accurate detection requires writing to the window base
register.  That is not safe for pciconf(8).  Instead, this assumes that
any window where both the base and limit read as all zeroes is
unimplemented.

Second, the PCI-PCI bridge driver in a tree has a few quirks for
PCI-PCI bridges that use subtractive decoding but do not indicate that
via the progif config register.  The list of quirks is duplicated in
pciconf's source.

Reviewed by:	imp
MFC after:	2 weeks
Differential Revision:	https://reviews.freebsd.org/D4171
2015-11-23 23:48:07 +00:00
Zbigniew Bodek
1fe6a1a25a Add support for vendor specific function for PCI devid acquisition in ITS
It is possible that some HW will use different PCI devids,
hence allow to replace the default domain🚌slot:func schema
by implementing and registering custom function.

Obtained from: Semihalf
Sponsored by:  The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D3118
2015-07-21 14:47:23 +00:00
Ryan Stone
9bfb1e36d9 Implement interface to create SR-IOV Virtual Functions
Implement the interace to create SR-IOV Virtual Functions (VFs).
When a driver registers that they support SR-IOV by calling
pci_setup_iov(), the SR-IOV code creates a new node in /dev/iov
for that device.  An ioctl can be invoked on that device to
create VFs and have the driver initialize them.

At this point, allocating memory I/O windows (BARs) is not
supported.

Differential Revision:	https://reviews.freebsd.org/D76
Reviewed by:		jhb
MFC after: 		1 month
Sponsored by:		Sandvine Inc.
2015-03-01 00:40:09 +00:00
Ryan Stone
2397d2d817 Add some pcib methods to get ARI-related information
Differential Revision:	https://reviews.freebsd.org/D72
Reviewed by:		jhb
MFC after: 		1 month
Sponsored by:		Sandvine Inc.
2015-03-01 00:39:40 +00:00
Alexander Motin
e887c1dedf Add IOMMU PCI subclass, found on Tyan S8236 motherboard.
Submitted by:	Dmitry Luhtionov <dmitryluhtionov@gmail.com>
MFC after:	2 weeks
2014-05-20 14:39:22 +00:00
Ryan Stone
55d3ea1731 Add support for PCIe ARI
PCIe Alternate RID Interpretation (ARI) is an optional feature that
allows devices to have up to 256 different functions.  It is
implemented by always setting the PCI slot number to 0 and
re-purposing the 5 bits used to encode the slot number to instead
contain the function number.  Combined with the original 3 bits
allocated for the function number, this allows for 256 functions.

This is enabled by default, but it's expected to be a no-op on currently
supported hardware.  It's a prerequisite for supporting PCI SR-IOV, and
I want the ARI support to go in early to help shake out any bugs in it.
ARI can be disabled by setting the tunable hw.pci.enable_ari=0.

Reviewed by:	kib
MFC after:	2 months
Sponsored by:	Sandvine Inc.
2014-04-01 16:02:02 +00:00
Ryan Stone
5605a99e36 Add a method to get the PCI RID for a device.
Reviewed by:	kib
MFC after:	2 months
Sponsored by:	Sandvine Inc.
2014-04-01 15:47:24 +00:00
Ryan Stone
7036ae46bf Revert PCI RID changes.
My PCI RID changes somehow got intermixed with my PCI ARI patch when I
committed it.  I may have accidentally applied a patch to a non-clean
working tree.  Revert everything while I figure out what went wrong.

Pointy hat to: rstone
2014-04-01 15:06:03 +00:00
Ryan Stone
d773f48b1e Add a method to get the PCI Routing ID for a device
Reviewed by:	kib
Sponsored by:	Sandvine, Inc
2014-04-01 14:49:25 +00:00
Konstantin Belousov
83cc1cfaea Add some definitions for the bits in root control and status PCIe cap
registers.

Reviewed by:	jhb
Sponsored by:	The FreeBSD Foundation
MFC after:	1 week
2013-10-24 20:25:29 +00:00
Konstantin Belousov
f05f3c1764 Add new capability types encodings from HyperTransport I/O Link
Specification revisions 3.00 and 3.10.

Submitted by:	Dmitry Luhtionov <dmitryluhtionov@gmail.com>
MFC after:	1 week
2013-05-17 14:04:31 +00:00
Warner Losh
764f2139e6 Add missing Extended Capability ID Numbers from PCIe 3.0. 2012-10-19 23:10:55 +00:00
Jim Harris
6483d5a592 Add constants for programming interfaces for NVM/solid state storage
controller sub-class code.

Reference:  PCI Code and ID Assignment Specification Rev 1.2

Sponsored by:	Intel
Inspired by:	gavin
MFC after: 	1 week
X-MFC-With:	r240694
2012-09-19 15:43:30 +00:00
Gavin Atkinson
536f8fdecf Add PCI subclass for NVM Express devices.
Reference:
http://www.nvmexpress.org/index.php/download_file/view/42/1/NVM_Express_1_0b.pdf
section 2.1.5.

MFC after:	1 week
2012-09-19 12:54:25 +00:00
Gavin Atkinson
389c8bd51e Align the PCI Express #defines with the style used for the PCI-X
#defines.  This also has the advantage that it makes the names more
compact, iand also allows us to correct the non-uniform naming of
the PCIM_LINK_* defines, making them all consistent amongst themselves.

This is a mostly mechanical rename:
  s/PCIR_EXPRESS_/PCIER_/g
  s/PCIM_EXP_/PCIEM_/g
  s/PCIM_LINK_/PCIEM_LINK_/g

When this is MFC'd, #defines will be added for the old names to assist
out-of-tree drivers.

Discussed with:	jhb
MFC after:	1 week
2012-09-18 22:04:59 +00:00
Gavin Atkinson
058ede33bf - Add #defines for the bits within the iPCI Express PCIR_EXPRESS_LINK_CTL
register
- Add missing register PCIR_EXPRESS_ROOT_CAP
- Correct a spelling mistake (SLAT -> SLOT) [1]

Reviewed by:	jhb [1]
2012-09-17 12:51:48 +00:00
John Baldwin
2cfd0c4638 - Add some registers defined in PCI 3.0 including new AER bits.
- Add constants for the rest of the fields in the PCI-express device
  capability and control registers.
- Tweak some of the recently added PCI-e capability constants (always
  use hex for offsets in config space, and include a shortened
  version of the relevant register in the name of field constants).

MFC after:	1 week
2012-09-13 19:05:24 +00:00
Gavin Atkinson
77c0749cb2 Add #defines for the bits in the PCI Express SLOT registers. Names
have been chosen based on the bit names in the PCI Express Base
Specification 3.0, and to match the predominant style of the existing
bit definitions.

MFC after:	1 week
2012-09-05 19:01:39 +00:00
Alexander Kabaev
6e9dcee4ca Save more of config space for PCI Express and PCI-X devices.
Expand pci_save_state and pci_restore_state to save more of
the config state for PCI Express and PCI-X devices. Various
writable control registers are present in PCI Express that
can potentially be lost over suspend/resume cycle.

This change is modeled after similar functionality in Linux.

Reviewed by: wlosh,jhb
MFC after:  1 month
2012-03-08 21:09:34 +00:00
John Baldwin
d38d1fbc53 Fix a spelling mistake in the surprise link down error constant.
Submitted by:	glebius
2012-01-31 15:48:40 +00:00
John Baldwin
c7e6732dde Add a constant for the PCI-e surprise link down uncorrectable error. 2012-01-30 15:09:03 +00:00
John Baldwin
4889af2063 Add a constant for the Advisory Non-Fatal Error bit in AER corrected error
status and mask.
2011-11-30 18:33:23 +00:00
Ruslan Ermilov
934d7bccdb Renamed PCI_INTERFACE_XHCI to PCIP_SERIALBUS_USB_XHCI and moved it
to <dev/pci/pcireg.h>.

Reviewed by:	hselasky
MFC after:	3 days
2011-05-17 11:23:43 +00:00
John Baldwin
a90dd577e7 Explicitly track the state of all known BARs for each PCI device. The PCI
bus driver will now remember the size of a BAR obtained during the initial
bus scan and use that size when doing lazy resource allocation rather than
resizing the BAR.  The bus driver will now also report unallocated BARs to
userland for display by 'pciconf -lb'.  Psuedo-resources that are not BARs
(such as the implicit I/O port resources for master/slave ATA controllers)
will no longer be listed as BARs in 'pciconf -lb'.  During resume, BARs are
restored from their new saved state instead of having the raw registers
saved and restored across resume.  This also fixes restoring BARs at
unusual loactions if said BAR has been allocated by a driver.

Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and
properly handle ROM BIOS BARs in PCI-PCI bridges.  The PCI bus now also
properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge.

Tested by:	jkim
2011-03-31 13:22:12 +00:00
Jung-uk Kim
d815d0abb7 Update PCI power management registers per PCI Bus Power Management Interface
Specification Rev. 1.2.  Rename pp_pcmcsr field of PM capabilities to pp_bse
to avoid further confusions and adjust some comments accordingly.  The real
PMCSR (Power Management Control/Status Register) is PCIR_POWER_STATUS and
it is actually BSE (PCI-to-PCI Bridge Support Extensions) register.
2010-10-20 23:41:16 +00:00
John Baldwin
da6b22afaf - Rename the constant for the Master Data Parity Error flag in the
PCI status register to map its current name.
- Use PCIM_* rather than PCIR_* for constants for fields in various AER
  registers.  I got about half of them right in the previous commit.

MFC after:	1 week
2010-09-09 18:19:15 +00:00
John Baldwin
79c2de35b5 - Add register definitions related to extended capability IDs in
PCI-express.  I used PCIZ_* for ID constants (plain capability IDs use
  PCIY_*).
- Add register definitions for the Advanced Error Reporting, Virtual
  Channels, and Device Serial Number extended capabilities.
- Teach pciconf -c to list extended as well as plain capabilities.   Adds
  more detailed parsing for AER, VC, and device serial numbers.

MFC after:	2 weeks
2010-09-08 17:53:34 +00:00
Rafal Jaworowski
c5a514a756 Provide more defines for PCI-Express device ctrl. 2010-07-11 20:55:39 +00:00
Pyun YongHyeon
bde52fe26d Add more bit definitions to PCI express device control and device
status register.

Reviewed by:	jhb
2010-02-01 20:50:49 +00:00
Andriy Gapon
1e908511f8 number of cleanups in i386 and amd64 pci md code
o introduce PCIE_REGMAX and use it instead of ad-hoc constant
o where 'reg' parameter/variable is not already unsigned, cast it to
  unsigned before comparison with maximum value to cut off negative
  values
o use PCI_SLOTMAX in several places where 31 or 32 were explicitly used
o drop redundant check of 'bytes' in i386 pciereg_cfgread() - valid
  values are already checked in the subsequent switch

Reviewed by:	jhb
MFC after:	1 week
2009-09-24 07:11:23 +00:00
Andriy Gapon
f778af723b pci: remove definitions of duplicate constants
Suggested by:	jhb
Reviewed by:	jhb
MFC after:	1 week
2009-09-10 19:27:53 +00:00
John Baldwin
a28b3fc741 - Add a few more register defintions for the PCI express capability
registers.
- Cleanup PCI-X capability printf to not leave a dangling "supports" for
  some PCI-X bridges.
- Display additional PCI express details including the negotiated and max
  link width and the actual and maximum supported max payload.

MFC after:	1 month
2009-04-17 19:07:44 +00:00
John Baldwin
c4e8c9df9e Always read/write the full 64-bit value of 64-bit BARs. Specifically,
when determining the size of a BAR by writing all 1's to the BAR and
reading back the result, always operate on the full 64-bit size.

Reviewed by:	imp
MFC after:	1 month
2009-03-05 15:33:04 +00:00
Robert Noland
5884a846e7 Disable INTx when enabling MSI/MSIX
This addresses interrupt storms that were noticed after enabling MSI
in drm.  I think this is due to a loose interpretation of the PCI 2.3
spec, which states that a function using MSI is prohibitted from using
INTx.  It appears that some vendors interpretted that to mean that they
should handle it in hardware, while others felt it was the drivers
responsibility.

This fix will also likely resolve interrupt storm related issues with
devices other than drm.

Reviewed by:	jhb@
MFC after:	3 days
2009-03-02 19:00:41 +00:00
Alexander Motin
b8adaa5549 Add SATA and PCI Advanced Features capabilities constants. 2009-02-15 09:49:21 +00:00
John Baldwin
da1e0915c5 - Add a new ioctl to /dev/pci to fetch details on an individual BAR of a
device.  The details include the current value of the BAR (including all
  the flag bits and the current base address), its length, and whether or not
  it is enabled.  Since this operation is not invasive, non-root users are
  allowed to use it (unlike manual config register access which requires
  root).  The intention is that userland apps (such as Xorg) will use this
  interface rather than dangerously frobbing the BARs from userland to
  obtain this information.
- Add a new sub-mode to the 'list' mode of pciconf.  The -b flag when used
  with -l will now list all the active BARs for each device.

MFC after:	1 month
2009-02-02 19:54:16 +00:00
Warner Losh
8481e37b53 Nit: Add a few leading zeros to make this match other mask constants
in this file.  Also to make sure that I got other ASI constants right.
2008-11-03 15:38:45 +00:00
Alexander Motin
c5343d0981 Add HDA multimedia subclass. 2008-10-21 21:53:55 +00:00
John Baldwin
9c0e9e988e The config space registers holding the upper 32-bits of the prefetchable
memory area's base and limit are optional.  The low 4-bits of the "low"
prefetchable registers indicates whether or not a 32-bit or 64-bit
region is supported.  The PCI-PCI driver had been assuming that all bridges
supported a 64-bit region (and thus the two upper 32-bit registers).  Fix
the driver to only use those registers if the low 4-bits of the "low"
registers indicate that a 64-bit region is supported.  The PCI-PCI bridge
in the XBox happens to be a bridge that only supports a 32-bit region.

Reported by:	rink
MFC after:	1 week
2008-08-20 18:29:59 +00:00
Stephane E. Potvin
1a2952820d - Fix a small bit slip in PCIM_PCAP_D[0-2]PME defines.
- Add the definitions for D3PME_COLD and D3PME_HOT capabilities.

Reviewed by:	njl (mentor), imp
Approved by:	re (kensmith)
MFC after:	1 week
2007-09-19 13:05:58 +00:00
Warner Losh
4b3337405d Change PCIM_CIS_ASI_TUPLE to _CONFIG.
Add PCI_MAX_BAR_0
minor style nit.
Add PCIM_CIS_CONFIG_MASK
2007-05-16 18:42:38 +00:00
John Baldwin
d68b1825b7 - HT 2.00b added a new flag to the MSI mapping HT capability to indicate
that the MSI mapping window is fixed at 0xfee00000 and the capability
  does not include two more dwords used to program the address.  Supporting
  this mostly results in quieting spurious warnings during boot about
  non-default MSI mapping windows.
- HT 2.00b also added a new HT capability type, so support that in pciconf.

MFC after:	3 days
Tested by:	jmg
2007-04-25 14:45:46 +00:00
John Baldwin
4dc5078f81 Add constants for the fields in a BAR. Also, add two new macros
PCI_BAR_(IO|MEM)() that return true if the passed in value from a BAR
is for an IO or memory BAR, respectively.

Reviewed by:	imp
2007-03-31 21:39:02 +00:00
John Baldwin
657d9f9f55 - Add missing constants for subclasses.
- Add a few progif constants as well.
2007-03-31 20:41:00 +00:00
John Baldwin
976c400776 - Flesh out list of UART simple comms programming interfaces.
- Add list of PIC base peripheral programming interfaces.
- Add VPD capability register offsets.

MFC after:	3 days
2007-03-05 16:18:31 +00:00
John Baldwin
f50589d755 Add constants for the PCIY_VENDOR (vendor-specific), PCIY_DEBUG (EHCI
debug port), and PCIY_EXPRESS (PCI-express) capabilities.
2007-02-02 19:48:25 +00:00
John Baldwin
6eb7ebfe25 - Change the PCI-X registers constants to be relative to the PCI-X PCI
capability rather than hardcoded offsets for a particular card.  While
  I'm here, expand the constants some.
- Change the ahd(4) driver to use pci_find_extcap() to locate the PCI-X
  capability to keep up with the first change.

Reviewed by:	scottl, gibbs (earlier version)
2007-01-19 22:37:52 +00:00