Commit Graph

83 Commits

Author SHA1 Message Date
Alexander Motin
9364490242 Fix names of some Marvell SATA chips. It looks like chips with proprietary
interface supported by mvs(4) are 88SX, while AHCI-like chips are 88SE.

PR:		kern/165271
Submitted by:	Jia-Shiun Li <jiashiun@gmail.com>
MFC after:	1 week
2012-03-02 08:49:07 +00:00
Ulrich Spörlein
9a14aa017b Convert files to UTF-8 2012-01-15 13:23:18 +00:00
Jim Harris
9bea89c1b0 Add 0x2826 device ID for C600 (Patsburg) SATA controller in RAID mode.
Reviewed by: mav
Approved by: scottl
2012-01-06 00:22:55 +00:00
Alexander Motin
c8973d9e6c Add hw.ahci.force tunable to control whether AHCI drivers should attach
to known AHCI-capable chips (AMD/NVIDIA), configured for legacy emulation.

Enabled by default to get additional performance and functionality of AHCI
when it can't be enabled by BIOS. Can be disabled to honor BIOS settings if
needed for some reason.

MFC after:	1 month
2011-12-02 12:52:33 +00:00
Hans Petter Selasky
3b12bdb58f Rename device_delete_all_children() into device_delete_children().
Suggested by:	jhb @ and marius @
MFC after:	1 week
2011-11-22 21:56:55 +00:00
Hans Petter Selasky
11bcf702f4 Move the device_delete_all_children() function from usb_util.c
to kern/subr_bus.c. Simplify this function so that it no longer
depends on malloc() to execute. Identify a few other places where
it makes sense to use device_delete_all_children().

MFC after:	1 week
2011-11-19 10:11:50 +00:00
Alexander Motin
72a61203fc Change the way how "not implemented" AHCI channels handled. Instead of
completely skipping them, create ahcich devices for them to allocate unit
numbers, but mark them as disabled to prevent driver probe and attach.

Last time some BIOSes tend to report unused channels as "not implemented".
This change makes ahcichX devices numbering consistent, independently of
connected disks. It makes per-channel driver hints usable and CAM devices
wiring possible on such systems.
2011-11-17 20:46:51 +00:00
Ed Schouten
d745c852be Mark MALLOC_DEFINEs static that have no corresponding MALLOC_DECLAREs.
This means that their use is restricted to a single C file.
2011-11-07 06:44:47 +00:00
Alexander Motin
cf2446231a Add one more ID for the Marvell 88SE9128 6Gbps SATA controller.
MFC after:	3 days
2011-09-27 09:32:34 +00:00
Alexander Motin
376271fb4c Add ID for ASMedia ASM1061 2-port PCIe 2.0 x1 6Gb/s SATA controller.
Approved by:	re (blackend)
MFC after:	1 week
2011-08-24 09:08:07 +00:00
Alexander Motin
df6f430410 Do not force AHCI mode on NVIDIA MCP89 SATA controllers. Recent Apple
Mac with this chipset does not initialize AHCI mode unless it is started
from EFI loader.  However, legacy ATA mode works.

Submitted by:	jkim@ (original version)
Approved by:	re (kib)
MFC after:	1 week
2011-08-02 11:07:47 +00:00
Alexander Motin
2d33cc7688 In some cases, at least on Marvell 88SE912x controllers, Current Command
Slot field of the PxCMD register may point to an empty command slot.
That breaks command timeout detection logic, making impossible to find
what command actually caused timeout, and leading to infinite wait.
Workaround that by checking whether pointed command slot is really used
and can timeout in its time. And if not, fallback to the dumb algorithm
used with FBS -- let all commands to time out and then fail all of them.

Approved by:	re (kib)
MFC after:	1 week
2011-07-29 20:35:23 +00:00
Alexander Motin
35ded6a6a7 Add ID for Marvell 88SE9125 SATA controller.
PR:		kern/157843
MFC after:	1 week
2011-06-30 19:23:17 +00:00
Alexander Motin
1d4ce50afe Add Marvell 88SE9172 chip PCI ID. 2011-05-26 10:10:10 +00:00
Alexander Motin
232a9d55fb Marvell 88SE91xx controllers are known to report soft-reset completion
without waiting for device readiness (or at least not updating FIS receive
area in time). To workaround that, special quirk was added earlier to wait
for the FIS receive area update. But it was found that under same PCI ID
0x91231b4b and revision 0x11 there are two completely different chip
versions (firmware?): HBA and RAID. The problem is that RAID version in
some cases, such as hot-plug, does not update FIS receive area at all!

To workaround that, differentiate the chip versions by their capabilities,
and, if RAID version found, skip FIS receive area update waiting and read
device signature from the PxSIG register instead. This method doesn't work
for HBA version when PMP attached, so keep using previous workaround there.
2011-05-26 09:23:01 +00:00
Alexander Motin
08c8fde007 According to SATA specification, when Serial ATA Enclosure Management Bridge
(SEMB) is unable to communicate to Storage Enclosure Processor (SEP), in
response to hard and soft resets it should among other things return value
0x7F in Status register. The weird side is that it means DRQ bit set, which
tells that reset request is not completed. It would be fine if SEMB was the
only device on port. But if SEMB connected to PMP or built into it, it may
block access to other devices sharing same SATA port.

Make some tunings/fixes to soft-reset handling to workaround the issue:
 - ahci(4): request CLO on the port after soft reset to ignore DRQ bit;
 - siis(4): gracefully reinitialize port after soft reset timeout (hardware
doesn't detect reset request completion in this case);
 - mvs(4): if PMP is used, send dummy soft-reset to the PMP port to make it
clear DRQ bit for us.

For now this makes quirks in ata_pmp.c, hiding SEMB ports of SiI3726/SiI4726
PMPs, less important. Further, if hardware permit, I hope to implement real
SEMB support.
2011-05-25 13:55:49 +00:00
Alexander Motin
96b7988f12 Add support for "LED" enclosure management messages, defined by the AHCI.
When supported by hardware, this allows to control per-port activity, locate
and fault LEDs via the led(4) API for localization and status reporting
purposes. Supporting AHCI controllers may transmit that information to the
backplane controllers via SGPIO interface. Backplane controllers interpret
received statuses in some way (IBPI standard) to report them using present
indicators.
2011-05-17 22:07:45 +00:00
Jack F Vogel
73e3bb6563 Chipset support for the new Intel Panther Point PCH, thanks
to Seth Heasley for preparing the changes.
2011-05-11 20:31:27 +00:00
Alexander Motin
e2d6ccef4b Add PCI ID for Marvell 88SE9182 -- PCIe 2.x x2 relative of the 88SE912x.
Submitted by:	dchagin
MFC after:	1 week
2011-05-05 17:11:26 +00:00
Alexander Motin
7bcc595738 Fix some English grammar. 2011-04-19 10:57:40 +00:00
Alexander Motin
1f145eafea According to specification. device should respond to COMRESET with COMINIT
in no more then 10ms. If we detected no device presence within that time,
there is no reason to wait longer.
2011-04-19 10:51:19 +00:00
Alexander Motin
6ac0befde2 Properly handle memory allocation errors during error recovery. 2011-04-19 08:01:17 +00:00
Alexander Motin
18301f742e Handle ready timeout during polled operation same as done in mvs(4) before. 2011-04-18 16:00:46 +00:00
Alexander Motin
3a3d820b3d - Tune different wait loops to cut some more milliseconds from reset time.
- Do not call ahci_start() before device signature received. It is required
by the specification and caused non-fatal reset timeouts on AMD chipsets.
2011-04-18 13:34:31 +00:00
Alexander Motin
06ccfe1dd7 Some changes around hot-plug and interface power-management:
- use ATA_SE_EXCHANGED (SError.DIAG.X) bit to detect hot-plug events when
power-management enabled and ATA_SE_PHY_CHANGED (SError.DIAG.N) can't be
trusted;
 - on controllers supporting staggered spin-up (SS) put unused channels
into Listen state instead of Off. It should still save some power, but
allow plug-in events to be detected;
 - on controllers supporting cold presence detection (CPD), when power
management enabled, use CPD events to detect hot-plug in addition to PHY
events.
2011-04-15 16:40:31 +00:00
Alexander Motin
8d169381e4 Improve SATA Asynchronous Notification feature support in CAM:
- make SATA SIMs announce capabilities to handle SDB with Notification bit;
 - make PMP driver honor this SIMs capability;
 - make SATA XPT to negotiate and enable this feature for ATAPI devices.

This feature allows supporting SATA ATAPI devices to inform system about
some events happened, that may require attention. In my case this allows
LG GH22LS50 SATA DVR-RW drive to report tray open/close events. Events
reported to CAM in form of AC_SCSI_AEN async. Further they could be used
as a hints for checking device status and reporting media change to upper
layers, for example, via spoiling mechanism of GEOM.
2011-04-13 16:20:54 +00:00
Alexander Motin
df1439e31f Refactor hard-reset implementation in ahci(4).
Instead of spinning in a tight loop for up to 15 seconds, polling for device
readiness while it spins up, return reset completion just after PHY reports
"connect well" or 100ms connection timeout. If device was found, use callout
for checking device readiness with 100ms period up to full 31 second timeout.

This fixes system freeze for 5-10 seconds on drives hot plug-in.
2011-04-12 20:50:57 +00:00
Alexander Motin
6bbd332e5d Implement automatic SCSI sense fetching for ahci(4). 2011-04-12 11:24:59 +00:00
Alexander Motin
5b917bfc3f Add one more ID for Marvell 88SE912x chip found on Asus U3S6 card.
Submitted by:	Jonas Jonsson <fatbrain@gmail.com>
2011-04-07 08:28:53 +00:00
Alexander Motin
65c63cd22f Add some more IDs of HighPoint RocketRAID 64x. 2011-03-06 16:10:39 +00:00
Alexander Motin
fa84e0f903 Restore DH89xxCC/Patsburg chip IDs accentally dropped at r218596. 2011-02-12 13:28:50 +00:00
Alexander Motin
a7c797f063 Disable NCQ for multiport Marvell 88SX61XX SATA controllers. Simultaneous
active I/O to several disks (copying large file on ZFS) causes timeout after
just a few seconds of run. Single port 88SX6111 seems like not affected.

Skip reading transferred bytes count for these controllers. It works for
88SX6111, but 88SX6145 always returns zero there. Haven't tested others,
but better to be safe.
2011-02-12 07:06:40 +00:00
Jack F Vogel
bf0477b215 Support for the new Patsburg PCH chipset:
- SMBus Controller
     - SATA Controller
     - HD Audio Controller
     - Watchdog Controller

Thanks to Seth Heasley (seth.heasley@intel.com) for providing us code.

MFC after 3 days
2011-02-01 01:05:11 +00:00
Jack F Vogel
d5267ede37 Support for the new DH89xxCC PCH chipset including:
- SATA controller
      - Watchdog timer
      - SMBus controller
2011-01-31 18:41:52 +00:00
Alexander Motin
da839e639b Add IDs for HighPoint RocketRAID 64x controllers.
These controllers consist of two Marvell 88SE9128 6Gbps SATA chips and
PLX PCIe bridge. As result, they seem to be agree to work with ahci(4)
as usual HBAs. The only noticed issue is that RAID BIOS disables all
drive caches during boot, though `camcontrol cmd ...` is able to fix that.

Those who wants RAID functionality can still use closed proprietary driver
from HighPoint site.

MFC after:	1 week
2011-01-10 22:27:52 +00:00
Alexander Motin
ee65f30a14 Add IDs of HighPoint RocketRAID 62x cards (Marvell 88SE9128 chips).
PR:		kern/152926
Submitted by:	Mike Tancsa <mike@sentex.net>
MFC after:	1 week
2010-12-08 20:35:20 +00:00
Alexander Motin
96ecb95ed9 Fix small typo.
Submitted by:	Artem Belevich
2010-11-22 23:04:25 +00:00
Alexander Motin
ba3a999598 Teach ahci(4), siis(4) and ATA_CAM ata(4) wrapper report to CAM residual
I/O length on underruns, that often happens for some SCSI commands.
2010-11-08 15:36:15 +00:00
Alexander Motin
5b9392e840 Add missing mtx_destroy() on channel attach failure. 2010-10-25 07:41:21 +00:00
Alexander Motin
bf12976c76 Fix panic, when due to some kind of congestion on FIS-based switching
port multiplier some command triggers false positive timeout, but then
completes normally.

MFC after:	2 weeks
2010-09-16 12:39:50 +00:00
Alexander Motin
90400bed63 MFata(4):
Add Intel Cougar Point PCH SATA Controller DeviceIDs. Correct some existing
entries for Intel Ibex Peak (5 Series/3400 Series) PCH SATA controllers.
2010-08-28 07:24:45 +00:00
Alexander Motin
8edcf69406 Export PCI IDs of ATA/SATA controllers through CAM and ata(4) layers to
GEOM. This information needed for proper soft-RAID's on-disk metadata
reading and writing.
2010-07-25 15:43:52 +00:00
Alexander Motin
a47eae85b4 Disable NCQ and PMP support for VIA VT8251 AHCI. It was reported to be
unreliable under load. Linux does the same.
2010-06-08 10:03:08 +00:00
Alexander Motin
dc5a530b04 Plug memory leak to silent Coverity. Error is still not really handled.
Found with:   Coverity Prevent(tm)
CID:          4130
2010-06-05 08:07:54 +00:00
Alexander Motin
c4d8fe61a1 Fix attach errors handling.
Found with:   Coverity Prevent(tm)
CID:          3424
2010-06-05 08:02:19 +00:00
Alexander Motin
cc6b610bea Fill rman range start/end values. It makes devinfo output more readable. 2010-05-22 08:30:47 +00:00
Alexander Motin
445cc79ca9 Report ATA/SATA channel number to NewBus at location string. 2010-05-22 07:32:47 +00:00
Alexander Motin
6533cd198d Improve suspend/resume support. Make sure controller is idle on suspend
and reset it on resume.
2010-05-21 13:29:28 +00:00
Alexander Motin
205367f9bc Enable PCI busmastering explicitly to be sure. 2010-05-02 14:46:05 +00:00
Alexander Motin
da6808c111 Make SATA XPT negotiate and enable some additional SATA features, such as:
- device initiated power management (some devices support only this way);
 - Automatic Partial to Slumber Transition (more power saving);
 - DMA auto-activation (expected to slightly improve performance).
More features could be added later, when hardware supports.
2010-05-02 12:07:47 +00:00