Commit Graph

1411 Commits

Author SHA1 Message Date
Brooks Davis
063629a18d Don't include syscons in the config just yet. We haven't imported the
touchscreen driver yet.
2012-08-25 17:34:48 +00:00
Alan Cox
648b050d7d Retire PV_TABLE_MOD. When we destroy or write protect a dirty mapping,
we call vm_page_dirty().  Maintaining the PV_TABLE_MOD flag, in addition,
serves no useful purpose.
2012-08-25 16:55:38 +00:00
Robert Watson
190cc7cf25 Add reference kernel configurations for FreeBSD/beri in simulation, on the
Terasic DE-4, and Terasic tPad Altera-based boards.

Sponsored by:	DARPA, AFRL
2012-08-25 12:02:13 +00:00
Robert Watson
697a77c1c4 Add altera_jtag_uart(4), a device driver for Altera's JTAG UART soft core,
which presents a UART-like interface over the Avalon bus that can be
addressed over JTAG.  This IP core proves extremely useful, allowing us to
connect trivially to the FreeBSD console over JTAG for FPGA-embedded hard
and soft cores.  As interrupts are optionally configured for this soft
core, we support both interrupt-driven and polled modes of operation,
which must be selected using device.hints.  UART instances appear in /dev
as ttyu0, ttyu1, etc.

However, it also contains a number of quirks, which make it difficult to
tell when JTAG is connected, and some buffering issues.  We work around
these as best we can, using various heuristics.

While the majority of this device driver is not only not BERI-specific,
but also not MIPS-specific, for now add its defines in the BERI files
list, as the console-level parts are aware of where the first JTAG UART
is mapped on Avalon, and contain MIPS-specific address translation, to
use before Newbus and device.hints are available.

Sponsored by:	DARPA, AFRL
2012-08-25 11:30:36 +00:00
Robert Watson
c9790125b5 Add preliminary support for the SRI International / University of Cambridge
Bluespec Extensible RISC Implementation (BERI) processor.  BERI is a 64-bit
MIPS ISA soft CPU core that can be synthesised to Altera and Xilinx FPGAs,
and is being used for CPU and OS research at several institutions.

Sponsored by:   DARPA, AFRL
2012-08-25 08:31:21 +00:00
Robert Watson
8122a592ee Provide basic glue to allow syscons to be used on MIPS, modelled
on PowerPC support.  This was clearly not something syscons was
designed to do (very specific assumptions about the nature of VGA
consoles on PCs), but fortunately others have long since blazed
the way on making it work regardless of that.

Sponsored by:	DARPA, AFRL
2012-08-25 08:09:37 +00:00
Robert Watson
431735d0c3 On MIPS, when printing page fault information for an unexpected exception
type, explicitly print out "unknown" rather than the empty string, and
include the exception type number for ease of debugging.

Sponsored by:	DARPA, AFRL
2012-08-25 08:02:46 +00:00
Aleksandr Rybalko
40bcb1d1fd Remove duplicated GEOM_PART_* options.
PR:		170931
Approved by:	adrian
2012-08-23 22:23:56 +00:00
Jayachandran C.
8099aeffc3 Add correct range parameter in XLP DTS
r239274 added support for ranges. Update XLP DTS to provide the correct
range parameter for the XLP SoC bus.  Also fix bus_space_map method
for XLP bus space.

Submitted by:	Sreekanth M. <sreekanth.molagavalli@broadcom.com>
2012-08-21 09:37:23 +00:00
Jayachandran C.
718444dcc1 Define and exclude DRAM regions used by hardware/bootloder on XLP
Fix xlp_mem_init() - remove the ad-hoc code for excluding memory regions
and use an array of regions.
2012-08-20 11:51:49 +00:00
Alan Cox
09563c2244 Eliminate another vestige of page coloring. 2012-08-17 20:15:01 +00:00
Alan Cox
f274a47134 Fix two problems with pmap_clear_modify().
First, pmap_clear_modify() is write protecting all mappings to the specified
page, not just clearing the modified bit.  Specifically, it sets PTE_RO on
the PTE, which is wrong.  Moreover, it is calling vm_page_dirty(), which is
not the expected behavior for pmap_clear_modify().  Generally speaking, the
machine-independent VM layer masks these mistakes.  For example, setting
PTE_RO will result in additional soft faults, but not a catastrophe.

Second, pmap_clear_modify() may not clear the modified bits because it only
iterates over the PV list when the page has the PV_TABLE_MOD flag set and
elsewhere the pmap clears the PV_TABLE_MOD flag anytime a modified mapping
is write protected or destroyed.  However, the page may still have other
mappings with the modified bit set.

Eliminate a stale comment.
2012-08-17 05:02:29 +00:00
Rui Paulo
8c09f7b626 The GPIO drivers were initialising their mutexes with type of
MTX_NETWORK_LOCK. This is wrong since these mutexes have nothing to do
with networking.
2012-08-17 04:44:57 +00:00
Alan Cox
6f601842d2 Eliminate an unused parameter from init_pte_prot().
Eliminate stray whitespace within init_pte_prot().

Eliminate a gratuitous variable initialization from pmap_enter().
2012-08-16 04:41:15 +00:00
Alan Cox
397b37ed55 Replace all uses of the vm page queues lock by a r/w lock that is private
to this pmap.

Tidy up the #include's.

Remove the (now) unused #define PMAP_SHPGPERPROC.  (This should have
been removed in r239236.)

Tested by:	jchandra
2012-08-15 22:51:01 +00:00
Alan Cox
f167c4a762 Port the new PV entry allocator from amd64/i386. This allocator has two
advantages.  First, PV entries are roughly half the size.  Second, this
allocator doesn't access the paging queues, and thus it will allow for the
removal of the page queues lock from this pmap.

Fix a rather serious bug in pmap_remove_write().  After removing write
access from the specified page's first mapping, pmap_remove_write() then
used the wrong "next" pointer.  Consequently, the page's second, third,
etc. mappings were not write protected.

Tested by:	jchandra
2012-08-13 17:38:38 +00:00
Alan Cox
c0c5f0df71 Merge r134393 from amd64/i386:
The machine-independent parts of the virtual memory system always pass a
  valid pmap to the pmap functions that require one.  Remove the checks for
  NULL.  (These checks have their origins in the Mach pmap.c that was
  integrated into BSD.  None of the new code written specifically for
  FreeBSD included them.)
2012-08-10 05:00:50 +00:00
Alan Cox
b3ca34cfd2 Merge r132141 and r111272 from amd64/i386:
Reduce the size of a PV entry by eliminating pv_ptem.  There is no need
  to store a pointer to the page table page in the PV entry because it is
  easily computed during the walk down the page table.

  Eliminate the ptphint from the pmap.  Long, long ago, page table pages
  belonged to a vm object, and we would look up page table pages based
  upon their offset within this vm object.  In those days, this hint may
  have had tangible benefits.

Tested by:	jchandra
2012-08-09 16:38:17 +00:00
Warner Losh
b7e39c683a Fix obvious problem with emulate_fp sysctl.
Submitted by:	Paul Ambrose <ambrosehua@gmail.com>
2012-08-07 08:37:35 +00:00
Robert Watson
051d6b64cd Merge FreeBSD/beri Perforce change @211945 to head:
Modify MIPS page table entry (PTE) initialisation so that cachability
bits are set only once, using is_cacheable_mem() to determine what
caching properties are required, rather than also unconditionally
setting PTE_C_CACHE in init_pte_prot().  As PTE_C_CACHE |
PTE_C_UNCACHED == PTE_C_CACHE, this meant that all userspace memory
mappings of device memory (incorrectly) used caching TLB entries.

This is arguably not quite what we want, even though it is (more)
consistent with the MIPS pmap design: PTE caching properties should
be derived from machine-independent page table attributes, but this
is a substantially more complex change as the MIPS pmap doesn't yet
know about page attributes, causing it to ignore requests by device
drivers that want uncached userspace memory mappings as they
describe memory-mapped FIFOs or shared memory with a device not
participating in the cache coherence scheme.

This fixes cacheability issues (specifically, undesired and
unrequested caching) seen in userspace memory mappings of Avalon SoC
bus device memory on BERI MIPS.

Discussed with:	jmallett, alc
Sponsored by:	DARPA, AFRL
MFC after:	3 days
2012-07-28 11:09:03 +00:00
Alan Cox
85eeca35b9 Move what remains of vm/vm_contig.c into vm/vm_pageout.c, where similar
code resides.  Rename vm_contig_grow_cache() to vm_pageout_grow_cache().

Reviewed by:	kib
2012-07-18 05:21:34 +00:00
Jayachandran C.
92184b6098 Support Netlogic XLP 8xx B1 revisions in xlpge.
Updates to the MDIO access code for the new revision of the
XLP chip.
2012-07-09 10:39:57 +00:00
Jayachandran C.
fe60722c96 Identify Netlogic XLP 8xx B1 chip revisions
Add functions to check for 8xx B0 and 3xx Ax revisions which will
be used in network block initialization.
2012-07-09 10:24:45 +00:00
Jayachandran C.
21221d1f6b Fix PCIe hardware swap configuration for Netlogic XLP
The last 12 bits of the limit registers have to be set to 1. These
bits are not significant in bridge BARs and are 0 on read, but the
bits are valid in the swap limit register and needs to be set.
2012-07-09 10:17:06 +00:00
Warner Losh
f3140a8923 octeon_uart_class was removed some time ago everywhere but here. 2012-06-28 06:49:04 +00:00
Oleksandr Tymoshenko
8696e0cb5b Handle case when result of pmap_pte is NULL. This issue was uncovered
by r237367
2012-06-25 17:50:11 +00:00
Andrew Turner
74dc547e24 Make the wchar_t type machine dependent.
This is required for ARM EABI. Section 7.1.1 of the Procedure Call for the
ARM Architecture (AAPCS) defines wchar_t as either an unsigned int or an
unsigned short with the former preferred.

Because of this requirement we need to move the definition of __wchar_t to
a machine dependent header. It also cleans up the macros defining the limits
of wchar_t by defining __WCHAR_MIN and __WCHAR_MAX in the same machine
dependent header then using them to define WCHAR_MIN and WCHAR_MAX
respectively.

Discussed with:	bde
2012-06-24 04:15:58 +00:00
Konstantin Belousov
aea810386d Implement mechanism to export some kernel timekeeping data to
usermode, using shared page.  The structures and functions have vdso
prefix, to indicate the intended location of the code in some future.

The versioned per-algorithm data is exported in the format of struct
vdso_timehands, which mostly repeats the content of in-kernel struct
timehands. Usermode reading of the structure can be lockless.
Compatibility export for 32bit processes on 64bit host is also
provided. Kernel also provides usermode with indication about
currently used timecounter, so that libc can fall back to syscall if
configured timecounter is unknown to usermode code.

The shared data updates are initiated both from the tc_windup(), where
a fast task is queued to do the update, and from sysctl handlers which
change timecounter. A manual override switch
kern.timecounter.fast_gettime allows to turn off the mechanism.

Only x86 architectures export the real algorithm data, and there, only
for tsc timecounter. HPET counters page could be exported as well, but
I prefer to not further glue the kernel and libc ABI there until
proper vdso-based solution is developed.

Minimal stubs neccessary for non-x86 architectures to still compile
are provided.

Discussed with:	bde
Reviewed by:	jhb
Tested by:	flo
MFC after:	1 month
2012-06-22 07:06:40 +00:00
Konstantin Belousov
232aa31fb9 Reserve AT_TIMEKEEP auxv entry for providing usermode the pointer to
timekeeping information.

MFC after:  1 week
2012-06-22 06:38:31 +00:00
Alan Cox
6031c68de4 The page flag PGA_WRITEABLE is set and cleared exclusively by the pmap
layer, but it is read directly by the MI VM layer.  This change introduces
pmap_page_is_write_mapped() in order to completely encapsulate all direct
access to PGA_WRITEABLE in the pmap layer.

Aesthetics aside, I am making this change because amd64 will likely begin
using an alternative method to track write mappings, and having
pmap_page_is_write_mapped() in place allows me to make such a change
without further modification to the MI VM layer.

As an added bonus, tidy up some nearby comments concerning page flags.

Reviewed by:	kib
MFC after:	6 weeks
2012-06-16 18:56:19 +00:00
Dag-Erling Smørgrav
9189ae71fa auth.conf is dead. 2012-06-12 17:04:56 +00:00
Bjoern A. Zeeb
920b965865 MFp4 bz_ipv6_fast:
in_cksum.h required ip.h to be included for struct ip.  To be
  able to use some general checksum functions like in_addword()
  in a non-IPv4 context, limit the (also exported to user space)
  IPv4 specific functions to the times, when the ip.h header is
  present and IPVERSION is defined (to 4).

  We should consider more general checksum (updating) functions
  to also allow easier incremental checksum updates in the L3/4
  stack and firewalls, as well as ponder further requirements by
  certain NIC drivers needing slightly different pseudo values
  in offloading cases.  Thinking in terms of a better "library".

  Sponsored by:	The FreeBSD Foundation
  Sponsored by:	iXsystems

Reviewed by:	gnn (as part of the whole)
MFC After:	3 days
2012-05-24 22:00:48 +00:00
Alexander Motin
dc0aa406db MFprojects/zfsd:
Generalize and unify ses device description.
2012-05-24 11:20:51 +00:00
Adrian Chadd
2d269a1628 Enable the AR8316 switch on the routerstation pro board.
The configuration is:

* RGMII, both ports
* arge0 - connected to PHY4 as a dedicated port (CPU port)
* arge1 - connected to the switch ports

I've verified this on my routerstation pro board.
2012-05-19 20:11:18 +00:00
Adrian Chadd
c7551b8b46 Remove duplicate config bits.
Submitted by:	juli
2012-05-12 19:43:22 +00:00
Adrian Chadd
0d96099845 Revert this - I disabled it whilst hwpmc is/was broken. 2012-05-12 17:42:22 +00:00
Adrian Chadd
1111c8313a Flip on WN1043ND switch PHY support.
* Add the i2c bitbang bus;
* Add the etherswitch/rtl8366rb drivers;
* "fix" the USB GPIO configuration so USB actually works.

Submitted by:	Stefan Bethke <stb@lassitu.de>
2012-05-12 17:41:42 +00:00
Adrian Chadd
9d9690e93b Now that there's a hint for it, add a "I'm an AR7240 switch!" hint. 2012-05-12 05:27:14 +00:00
Adrian Chadd
f7c03fa47d Add in the AP93 configuration file.
The AP93 has:

* AR7240 - mips24k processor with integrated 10/100 switch and
  various other peripherals;
* AR9283 - 2x2 2.4GHz 802.11n (with calibration data in flash);
* 64MB RAM;
* 16MB SPI flash.

The switch code detects as an AR8216 at the present moment, which isn't
_entirely_ strictly true.  However, the MII/MDIO routing in AP93.hints
works - the arge0 MAC connects to PHY4 in the switch, but via the
switch internal MDIO bus.  The switch connects to arge0's MDIO bus,
but only to export the switch registers.

Thanks to stb and ray for the switch work, and ray for helping determine
what the correct switch hints should be for this thing.
2012-05-12 04:52:59 +00:00
Adrian Chadd
411477c533 Add switch support to AP96. 2012-05-11 21:13:43 +00:00
Juli Mallett
0c8da0be6e Add basic SMP support for GXemul. Ideally we would have some way to override
some of the IPI mechanisms used by the common MIPS SMP code so we could use
the multicast IPI facilities, on GXemul as well as on several real hardware
platforms, and the ability to have multiple hard IPI types.
2012-05-07 04:36:48 +00:00
Juli Mallett
bd6c6f4249 Add a trivial driver for the GXemul Ethernet device. Probably quite buggy and
certainly non-optimal, but enough for basic networking use.

Requested by:	rwatson
2012-05-07 04:15:46 +00:00
Juli Mallett
ffbec96825 Add a driver for the GXemul test machine's disk controller and disk devices.
Prefer it to using an md device in the GXEMUL kernel configuration.

Requested by:	rwatson, theraven
2012-05-06 08:28:08 +00:00
Juli Mallett
a0f00447fb Get the memory size from the gxemul mp device. Don't dump the environment if
it is not present.
2012-05-06 05:58:56 +00:00
Adrian Chadd
6632cb429f Disable setting the MII port speed.
This seems to break at least my test board here (AR71xx + AR8316 switch
PHY).  Since I do have a whole sleuth of "normal" PHY boards (with
an AR71xx on a normal PHY port), I'll do some further testing with those
to determine whether this is a general issue, or whether it's limited
to the behaviour of the "fake" dedicated PHY port mode on these atheros
switches.
2012-05-04 02:26:15 +00:00
Adrian Chadd
b846389100 In the new world order, multiphy is now when the phymask is 0x0.
This makes the TP-WN1043ND (ar913x based) work again.
2012-05-03 07:48:19 +00:00
Adrian Chadd
ce3c177ff8 Fix a totally bone-headed, last minute bounds check snafu that somehow
I must've missed when booting a test kernel.

This has been validated on the AR7161.
2012-05-03 05:52:39 +00:00
Bjoern A. Zeeb
4c95ae1b74 Catch-up with r232853 and remove platform APIs which are not used by any
code and which had only stub implementations or no implementation on all
platforms.  Makes gxemul compile.

Hinted by:	rwatson
MFC after:	3 weeks
X-MFC by:	rwatson:
2012-05-02 14:38:43 +00:00
Robert Watson
fe62958717 mips/mips64eb became mips/mips64 while I wasn't looking (whoops), so update
GXEMUL kernel config for the new world order.

Spotted by:	bz
MFC after:	3 weeks
2012-05-02 12:15:34 +00:00
Robert Watson
e36985c9aa Clean up various aspects of the MIPS generic busspace implementation:
1) Always implement missing bus space methods using a panic() stub rather
   than a NULL pointer.  This appeared not to trip up any existing device
   drivers, but due to the nature of the devices I'm supporting locally,
   I'm making use of some of the more obscure busspace methods, and
   panic() is a preferred failure mode.  For example, do this for the
   setregion methods.

2) Hook up several existing busspace method implementations that were
   provided in the file, but not actually present in the methods
   structure.  Especially, single-byte bus I/O routines.  This should
   allow bugs to be fixed in the Atheros 802.11 driver.

There are still some remaining unimplemented methods that would be
desirable to implement -- especially, 64-bit I/O calls that would
observably accelerate device performance on FPGA-based soft CPU cores
that are typically clocked an order of magnitude slower than
conventional hard core CPUs, but that remains for another day.

MFC after:	3 weeks
Discussed with:	jmallett, scottl
Sponsored by:	DARPA, AFRL
2012-05-02 08:23:53 +00:00
Robert Watson
79ee9286f2 Merge a rudimentary gxemul "oldtestmips" port. This consists almost
entirely of one machdep file lifted from the MALTA port, as well as
a low-level console and tty driver for the gxemul debugging console
device (the emulators stdio).  As with many low-level embedded and
hypervisor console devices, it is polled only, so we drive TTY I/O
from a callout; we are perhaps a bit too aware of the MIPS physical
maps in order to attach the console before newbus comes to life.

The sample kernel configuration depends on an MD-based root file
system, which is not provided.  However, any 64-bit, big-endian
userspace image (such as one generated for MALTA) should work.

This will hopefully be supplemented by additional device drivers for
gxemul-specific hardware simulations from Juli Mallett.  We have
found oldtestmips quite useful for testing and improving aspects of
the MIPS port, so it's worth supporting better in FreeBSD.

Requested by:	theraven, jmallett
Sponsored by:	DARPA, AFRL
MFC after:	3 weeks
2012-05-02 08:10:15 +00:00
Adrian Chadd
337ef3cad0 Implement PLL configuration override support, similar to what openwrt
implements.
2012-05-02 07:43:11 +00:00
Adrian Chadd
ceec92152b Disable the pll_1000 hint for now, the upcoming work enables it and it
breaks without the switch PHY code.
2012-05-02 07:41:26 +00:00
Adrian Chadd
7a1e9887de * Force the ethernet MII configuration to be RGMII
* Populate the "pll_1000" field, which will soon be used to override the
  PLL configuration from the default value.

Obtained from:	Linux OpenWRT
2012-05-02 06:19:26 +00:00
Adrian Chadd
f014aaebdf Allow the MII mode to be overridden via 'hint.arge.X.miimode'.
It takes a number at the moment, rather than a string.

Some of the Linux board configurations specify the MII mode explicitly.
2012-05-02 06:18:12 +00:00
Adrian Chadd
8b73bee2d3 Add a missing newline. 2012-05-02 06:17:16 +00:00
Adrian Chadd
23ec80a3da Further ar71xx MII support improvements.
* Flesh out the PLL configuration fetch function, which will return the PLL
  configuration based on the unit number and speed.
* Remove the PLL speed config logic from the AR71xx/AR91xx chip PLL config
  function - pass in a 'pll' value instead.
* Modify arge_set_pll() to:
  + fetch the PLL configuration
  + write the PLL configuration
  + update the MII speed configuration.

This will allow if_arge to override the PLL configuration as required.

Obtained from:	Linux/Atheros/OpenWRT
2012-05-02 04:51:43 +00:00
Adrian Chadd
da88453012 MII related infrastructure changes.
* Add a new method to set the MII mode - GMII, RGMII, RMII, MII.
  + arge0 supports all four (two for non-Gige interfaces.)
  + arge1 only supports two (one for non-gige interfaces.)
* Set the MII clock speed when changing the MAC PLL speed.
  + Needed for AR91xx and AR71xx; not needed for AR724x.

Tested:

* AR71xx only, I'll do AR913x testing tonight and fix whichever issues
  creep up.

TODO:

* Implement the missing AR7242 arge0 PLL configuration, but don't
  adjust the MII speed accordingly.
* .. the AR7240/AR7241 don't require this, so make sure it's not set
  accidentally.

Bugs (not fixed here):

* Statically configured arge speeds are still broken - investigate why
  that is on the AP96 board.  Autonegotiate is working fine, but there
  still seems to be an occasionally heavy packet loss issue.

Obtained from: Linux/Atheros/OpenWRT
2012-05-02 01:21:57 +00:00
Adrian Chadd
784bcea8a9 Introduce an enum which encapsulates the PHY interface types that can be
configured.
2012-05-02 01:14:15 +00:00
Adrian Chadd
a2ebf5ddb1 Add in the MII configuration parameters for the AR71xx.
Obtained from:	Linux/OpenWRT
2012-05-01 20:32:38 +00:00
Adrian Chadd
e4b7508aad Convert AP96 to use the mdioproxy and ARGE_MDIO option.
arge1 still works (it's the standalone PHY) but arge0 and the other switch
ports don't work.  They're enumerated though, demonstrating that the
mdiobus abstraction is correctly working.
2012-05-01 06:21:02 +00:00
Adrian Chadd
72b9c70e36 Break out the arge MDIO bus code into an optional argemdio device.
This is only done if the ARGE_MDIO option is included.

* Shuffle the arge MDIO bus into a separate device, that needs to be
  probed early (use hint.argemdio.X.order=0)
* hint.arge.X.mdio now specifies which miiproxy to rendezvous with.
* Call MAC/MDIO bus init during MDIO attach, not arge attach.

This is done regardless:

* Shift the arge MAC and MDIO bus reset code into separate functions
  and call it early during MDIO bus attach.  It's required for
  correct MDIO bus IO to occur on AR71xx/AR91xx devices.

* Remove the AR71xx/AR91xx centric assumption that there's only one
  MDIO bus.  The initial code mapped miibus0(arge0) and miibus1(arge1)
  MII register operations to the MII0 (arge0) register space.  The
  AR724x (and later, upcoming chipsets) have two MDIO busses and
  the second is very much in use.

TODO:

* since the multiphy behaviour has changed (where now a phymask of >1
  PHY will still be enumerated), multiphy setups may be quite wrong.
  I'll go and fix these so they still have a chance of working, at least.
  until the switch PHY support appears in -HEAD.

Submitted by:	Stefan Bethke <stb@lassitu.de>
2012-05-01 06:18:30 +00:00
Adrian Chadd
03cb2eedfd Migrate ARGE_DEBUG to opt_arge.h.
Submitted by:	Stefan Bethke <stb@lassitu.de>
2012-05-01 04:35:53 +00:00
Dimitry Andric
460378bf13 Add a convenience macro for the returns_twice attribute, and apply it to
the prototypes of the appropriate functions (getcontext, savectx,
setjmp, sigsetjmp and vfork).

MFC after:	2 weeks
2012-04-29 11:04:31 +00:00
Adrian Chadd
1d0e8a50a0 Allow for MIPS devices to have a specific probe/attach order.
The default priority is now '1000' rather than '0'.  This may cause some
unforseen regressions.

Submitted by:	Stefan Bethke <stb@lassitu.de>
Reviewed by:	imp
2012-04-21 04:17:30 +00:00
Adrian Chadd
15a353ce97 Allow for a default GPIO pin "high", which is required for some boards
which tie the USB device enable to a GPIO line.

Submitted by:	Stefan Bethke <stb@lassitu.de>
2012-04-20 22:44:00 +00:00
Adrian Chadd
b50d8083ab Introduce the matching PCI ath(4) fixup code from ar71xx_pci into
ar724x_pci.c.

* Move out the code which populates the firmware into ar71xx_fixup.c
* Shuffle around the ar724x fixup code to match what the ar71xx fixup
  code does.

I've validated this on an AR7240 with AR9285 on-board NIC. It doesn't
yet load, as the AR9285 EEPROM code needs to be made "flash aware."

TODO:

* Validate that I haven't broken AR71xx
* Test AR9285/AR9287 onboard NICs, complete with EEPROM code changes
* Port over the needed BAR hacks for AR7240, AR7241 and AR7242 from
  Linux OpenWRT.  The current WAR has only been tested on the AR7240
  and I'm not sure the way the BAR register is treated is "right".
  The "fixup" method here is right when setting the BAR for local access -
  ie, the BAR address is either 0xffff (AR7240) or 0x1000ffff (AR7241/AR7242),
  but the ath9k-fixup.c code (Linux OpenWRT) does this when setting the
  initial "fixup" BAR.  It then restores the original BAR.
  I'll have to read the ar724x PCI bus glue to see what other special cases
  await.
2012-04-20 08:26:05 +00:00
Adrian Chadd
93f5997b8c Style(9) and white space fixes. 2012-04-17 01:34:49 +00:00
Adrian Chadd
3f08db2e79 Protect the PCI space registers behind a mutex.
Obtained from:	Linux/OpenWRT, Atheros
2012-04-17 01:22:59 +00:00
Adrian Chadd
468d6f48b3 Add in the AP96 phy configuration from openwrt.
* arge0 doesn't (yet) work via the switch PHY ports; I'm not sure why.
* arge1 maps to the WAN port. That works.

TODO:

* The PLL register needs a different (non-default) value for Gigabit
  Ethernet.  The board setup code needs to be extended a bit to allow
  for non-default pll_1000 values - right now, those values come out
  of hard-coded values in the per-chip set_pll_ge() routines.

Obtained from:	Linux / OpenWRT
2012-04-15 22:59:56 +00:00
Adrian Chadd
5fdb2379cb The AR913x MII speed configuration matches the AR71xx MII configuration.
So share the code.

Don't do it for the AR724x - that has a completely different set of PLL
and MII configuration parameters.
2012-04-15 22:34:22 +00:00
Adrian Chadd
bf9abaa954 Fix the mask logic when reading PCI configuration space registers. 2012-04-15 02:38:01 +00:00
Adrian Chadd
c4b28bdc27 Flesh out the rest of the AP96 board/config. 2012-04-13 20:23:32 +00:00
Adrian Chadd
d591b27dbc * Enable ATH_EEPROM_FIRMWARE, now that it's a compile time option
* Tidy up things a bit.
2012-04-13 18:01:53 +00:00
Adrian Chadd
2c61ba4db2 These are uboot, so mark them as such or booting from flash will not work. 2012-04-13 08:56:23 +00:00
Adrian Chadd
3a8a3eebfd Introduce configuration files for AP94 and AP96.
This uses the new firmware(9) method for squirreling away the EEPROM
contents from SPI flash so ath(4) can get to them later.

It won't work out of the box just yet - you have to add this to
if_ath_pci.c:

#define ATH_EEPROM_FIRMWARE

.. until I've added it as a configuration option and updated things.
2012-04-13 08:52:25 +00:00
Adrian Chadd
8f7015e205 (ab)Use the firmware API to store away EEPROM calibration data for
future use by the ath(4) driver.

These embedded devices put the calibration/PCI bootstrap data on the
on board SPI flash rather than on an EEPROM connected to the NIC.
For some boards, there's two NICs and two sets of EEPROM data in the
main SPI flash.

The particulars:

* Introduce ath_fixup_size, which is the size of the EEPROM area in
  bytes.
* Create a firmware image with a name based on the PCI device identifier
  (bus/slot/device/function).
* Hide some verbose debugging behind 'bootverbose'.

ath(4) can then use this to load in the EEPROM data.

This requires AR71XX_ATH_EEPROM to be defined.
2012-04-13 08:45:50 +00:00
Adrian Chadd
8a138d80d0 Remove an unused variable. Grr. 2012-04-13 06:13:37 +00:00
Adrian Chadd
be94a28e2a Sync this code against what's in OpenWRT trunk.
* the openwrt code doesn't treat 0/0/0 any differently
  from other bus/slot/func combinations.
* A "local write" function writes to the LCONF area, and
  so I've added it.
* The PCI workaround at attach time uses this LCONF code,
  which it already did ..
* .. but it is a 4 byte write, not a 2 byte write.
  Even though it's PCIR_COMMAND which is a two byte PCI register.

Tested on:	AR7161
TODO:		The other two AR71xx derivatives
TODO:		More thoroughly stare at the datasheets I do have
		and if it indeed is incorrect, push fixes to both
		FreeBSD and Linux/OpenWRT.

Obtained from:	Linux OpenWRT
2012-04-13 06:11:24 +00:00
Jayachandran C.
2323b34a2d Reinstate the XTLB handler for CPU_NLM and CPU_RMI
These platforms set the KX bit even when booted in 32 bit mode. So
the XLTB handler is needed even when __mips_n64 is not defined.
2012-04-02 11:41:33 +00:00
John Baldwin
5e1a7cc71e Use VM_MEMATTR_UNCACHEABLE for the constant for UC memory rather than
VM_MEMATTR_UNCACHED.  VM_MEMATTR_UNCACHEABLE is the constant other
platforms use.

MFC after:	2 weeks
2012-03-29 16:48:36 +00:00
Jayachandran C.
7fb26c47df Remove unnecessary assembly code.
The compiler should generate lw/sw corresponding to register
operations.
2012-03-29 11:46:29 +00:00
Juli Mallett
84db023ec1 Assume a big-endian default on MIPS and drop the "eb" suffix from MACHINE_ARCH.
This makes our naming scheme more closely match other systems and the
expectations of much third-party software.  MIPS builds which are little-endian
should require and exhibit no changes.  Big-endian TARGET_ARCHes must be
changed:
	From:		To:
	mipseb		mips
	mipsn32eb	mipsn32
	mips64eb	mips64

An entry has been added to UPDATING and some foot-shooting protection (complete
with warnings which should become errors in the near future) to the top-level
base system Makefile.
2012-03-29 02:54:35 +00:00
Juli Mallett
df42d19401 Turn on messages from the Simple Executive codebase, what few there are. 2012-03-29 02:05:11 +00:00
Juli Mallett
5143d82211 Disable FP instruction emulation by default on !o32 because of ABI concerns.
Note that in practice this isn't needed because we get a coprocessor unusable
exception first, but that's actually something like a bug.
2012-03-29 02:04:15 +00:00
Juli Mallett
39dec33f2b Supply endianness implied by the -m flag when compiling ucore code. 2012-03-29 02:03:06 +00:00
Juli Mallett
5c3c01764b Fix little-endian built. 2012-03-29 02:02:23 +00:00
Fabien Thomas
f5f9340b98 Add software PMC support.
New kernel events can be added at various location for sampling or counting.
This will for example allow easy system profiling whatever the processor is
with known tools like pmcstat(8).

Simultaneous usage of software PMC and hardware PMC is possible, for example
looking at the lock acquire failure, page fault while sampling on
instructions.

Sponsored by: NETASQ
MFC after:	1 month
2012-03-28 20:58:30 +00:00
Jayachandran C.
eff39d0f38 Fix size of PCI softc. 2012-03-27 18:26:35 +00:00
Jayachandran C.
4b3aada9d4 Resource allocation for XLP SoC SDHCI slots
The on-chip SD slots do not have PCI BARs corresponding to them, so
this has to be handled in the custom SoC memory allocation.

Provide memory resource for rids corresponding to BAR 0 and 1 in
the custom allocation code.
2012-03-27 15:43:32 +00:00
Jayachandran C.
d5d4261f35 Update memory and resource allocation code for SoC devices
The XLP on-chip devices have PCI configuration headers, but some of the
devices need custom resource allocation code.
- devices with no MEM/IO BARs with registers in PCIe extended reg
  space have to be handled in memory resource allocation
- devices without INTPIN/INTLINE in PCI header can be supported
  by having these faked with a shadow register.
- Some devices does not allow 8/16 bit access to the register space,
  he default bus space cannot be used for these.

Subclass pci and override attach and resource allocation methods to
take care of this.

Remove earlier code which did this partially.
2012-03-27 15:39:55 +00:00
Jayachandran C.
2652f84c92 NOR flash driver for XLP.
The NOR interface on the SoC appears on the top level PCI bus. Add
a simple driver for this.
2012-03-27 15:16:38 +00:00
Jayachandran C.
250a191260 XLP UART code udpate.
Move XLP PCI UART device to sys/mips/nlm/dev/ directory.  Other
drivers for the XLP SoC devices will be added here as well.
Update uart_cpu_xlp.c and uart_pci_xlp.c use macros for uart port,
speed and IO frequency.
2012-03-27 14:48:40 +00:00
Jayachandran C.
35011d20cb xlpge : driver for XLP network accelerator
Features:
- network driver for the four 10G interfaces and two management ports
  on XLP 8xx.
- Support 4xx and 3xx variants of the processor.
- Source code and firmware building for the 16 mips32r2 micro-code engines
  in the Network Accelerator.
- Basic initialization code for Packet ordering Engine.

Submitted by:	Prabhath Raman (prabhath at netlogicmicro com)
		[refactored and fixed up for style by jchandra]
2012-03-27 14:05:12 +00:00
Jayachandran C.
ca950537bb Support for EEPROM and CPLD on XLP EVP boards.
On XLP evaluation platform, the board information is stored
in an I2C eeprom and the network block configuration is available
from a CPLD connected to the GBU (NOR flash bus). Add support
for both of these.
2012-03-27 12:25:47 +00:00
Jayachandran C.
9b4d140639 Opencrypto driver for XLP Security and RSA/ECC blocks
Support for the Security and RSA blocks on XLP SoC. Even though
the XLP supports many more algorithms, only the ones supported
in OCF have been added.

Submitted by:	Venkatesh J. V. (venkatesh at netlogicmicro com)
2012-03-27 11:43:46 +00:00
Jayachandran C.
8f57f9e0d7 I2C support for XLP, add hints for I2C devices and update PCI resource
allocation code.
2012-03-27 11:17:04 +00:00
Jayachandran C.
e12ed67f35 XLP PCIe code update.
- XLP supports hardware swap for PCIe IO/MEM accesses. Since we
  are in big-endian mode, enable hardware swap and use the normal
  bus space.
- move some printfs to bootverbose, and remove others.
- fix SoC device resource allocation code
- Do not use '|' while updating PCIE_BRIDGE_MSI_ADDRL
- some style fixes

In collaboration with: Venkatesh J. V. (venkatesh at netlogicmicro com)
2012-03-27 07:57:41 +00:00
Jayachandran C.
752a2fe776 Update the L1D cache flush sequence when enabling threads.
Added more comments to the code.
2012-03-27 07:51:42 +00:00
Jayachandran C.
68790561a5 Switch to interrupt based message handling for XLP 8xx B0.
Fixup some style issues in the file as well.
2012-03-27 07:47:13 +00:00
Jayachandran C.
91339fd498 Support for XLP4xx and XLP 8xx B0 revision
- Add 4xx processor IDs, add workaround in CPU detection code.
- Update frequency detection code for XLP 8xx.
- Add setting device frequency code.
- Update processor ID checking code.
2012-03-27 07:39:05 +00:00
Jayachandran C.
7aeda475e5 Fixes to the XLP startup code.
Changes are:
- Correct the order of calling init functions.
- Fix up checking excluding reset area.
2012-03-27 07:34:27 +00:00
Oleksandr Tymoshenko
5e608d0b09 Remap PMC interrupt for all cores 2012-03-24 06:28:15 +00:00
Oleksandr Tymoshenko
fa1e9b3a72 Add DTrace-related part to machine-dependent code:
- DTrace trap handler
- invop-related variables (unused on MIPS but still referenced from dtrace)
2012-03-24 05:17:38 +00:00
Oleksandr Tymoshenko
2a4f7a57fe Fix pmap_kextract prototype to align it with pmap.c change 2012-03-23 18:07:12 +00:00
Oleksandr Tymoshenko
f86a93b5be Add pseudo-device for handling PMC interrupts and link everything
PMC-related to build
2012-03-23 00:11:54 +00:00
Oleksandr Tymoshenko
ae849c7c42 Setup fake MODINFO variables for octeon kernel 2012-03-23 00:01:09 +00:00
Oleksandr Tymoshenko
1b930fb786 Rework MIPS PMC code:
- Replace MIPS24K-specific code with more generic framework that will
    make adding new CPU support easier
- Add MIPS24K support for new framework
- Limit backtrace depth to 1 for stability reasons and add option
    HWPMC_MIPS_BACKTRACE to override this limitation
2012-03-22 18:01:23 +00:00
Oleksandr Tymoshenko
a5fbfee1d0 Move PMC hook invocation to cpu_intr. The idea is the same as with ast()
call but there is no reason to implement it in assembler.
2012-03-22 17:47:52 +00:00
Jayachandran C.
0e37e252d2 Fix return type of mips pmap_kextract()
The return type should be vm_paddr_t, not vm_offset_t.
2012-03-22 15:14:10 +00:00
Juli Mallett
ce30db0b31 o) Don't keep drive parameters in a global, put them in the softc.
o) Don't report a bogus stripesize.
o) Eliminate a nearby gratuitous "proxy" indirection.
2012-03-21 10:27:12 +00:00
Ed Schouten
92396a3174 Remove pty(4) from our kernel configurations.
As of FreeBSD 8, this driver should not be used. Applications that use
posix_openpt(2) and openpty(3) use the pts(4) that is built into the
kernel unconditionally. If it turns out high profile depend on the
pty(4) module anyway, I'd rather get those fixed. So please report any
issues to me.

The pty(4) module is still available as a kernel module of course, so a
simple `kldload pty' can be used to run old-style pseudo-terminals.
2012-03-21 08:38:42 +00:00
Oleksandr Tymoshenko
fce0c7295d - Fix logic for detection if further processing of PMC should be performed.
pmc_intr returns one if one of the counters actually triggered the IRQ
- style(9) fixed
2012-03-18 01:43:41 +00:00
Adrian Chadd
0c7a79d76e style(9) changes. 2012-03-17 07:29:11 +00:00
Adrian Chadd
0e69f431d4 Begin fleshing out MII clock rate configuration changes.
These are needed for some particular port configurations where the default
speed isn't suitable for all link speed types. (Ie, changing 10/100/1000MBit
PLL rate requires a similar MII clock rate, rather than a fixed MII rate.)

This is:

* only currently implemented for the ar71xx;
* isn't used anywhere (yet), as the final interface for this hasn't yet
  been determined.
2012-03-17 07:25:23 +00:00
Oleksandr Tymoshenko
66134c7e59 Clean-up fake preload data generator:
- Use macros to push scalar values
- Fix type mismatch for module size
2012-03-15 23:53:24 +00:00
Oleksandr Tymoshenko
fba09d4c08 Fill out fake preload structure to let userland tools like pmc(3) know
about kernel module base address and actual size
2012-03-15 05:29:51 +00:00
Adrian Chadd
49def78fbb Remove a now unneeded ARGE_UNLOCK().
Whilst I'm here, remove a couple blank lines.
2012-03-13 06:50:56 +00:00
Adrian Chadd
8a5350984f Fix link status handling on if_arge upon system boot to allow bootp/NFS to
function.

From the submitter:

This patch fixes an issue I encountered using an NFS root with an
ar71xx-based MikroTik RouterBoard 450G on -current where the kernel fails
to contact a DHCP/BOOTP server via if_arge when it otherwise should be able
to.  This may be the same issue that Monthadar Al Jaberi reported against
an RSPRO on 6 March, as the signature is the same:

%%%

DHCP/BOOTP timeout for server 255.255.255.255
DHCP/BOOTP timeout for server 255.255.255.255
DHCP/BOOTP timeout for server 255.255.255.255
.
.
.
DHCP/BOOTP timeout for server 255.255.255.255
DHCP/BOOTP timeout for server 255.255.255.255
arge0: initialization failed: no memory for rx buffers
DHCP/BOOTP timeout for server 255.255.255.255
arge0: initialization failed: no memory for rx buffers

%%%

The primary issue that I found is that the DHCP/BOOTP message that
bootpc_call() is sending never makes it onto the wire, which I believe is
due to the following:

- Last December, a change was made to the ifioctl that bootpc_call() uses
to adjust the netmask around the sosend().

- The new ioctl (SIOCAIFADDR) performs an if_init when invoked, whereas the
old one (SIOCSIFNETMASK) did not.

- if_arge maintains its own sense of link state in sc->arge_link_status.

- On a single-phy interface, sc->arge_link_status is initialized to 0 in
arge_init_locked().

- sc->arge_link_status remains 0 until a phy state change notification
causes arge_link_task to run, notice the link is up, and set it to 1.

- The inits caused by the ifioctls in bootpc_call are reinitializing the
interface, but not the phy, so sc->arge_link_status goes to 0 and remains
there.

- arge_start_locked() always sees sc->arge_link_status == 0 and returns
without queuing anything.

The attached patch changes arge_init_locked() such that in the single-phy
case, instead of initializing sc->arge_link_status to 0, it runs
arge_link_task() to set it according to the current phy state.  This change
has allowed my setup to mount an NFS root successfully.

Submitted by:	Patrick Kelsey <kelsey@ieee.org>
Reviewed by:	juli
2012-03-13 06:28:52 +00:00
Juli Mallett
f8e47016ec Don't build kernel.tramp on Octeon. Probably building it should be opt-in
not opt-out, but I don't know enough about which ports need it to get the
defaults right.
2012-03-13 06:22:49 +00:00
Adrian Chadd
eeaef4bae5 Correctly (I hope) deallocate the if_arge RX buffer ring on arge_stop().
I had some interesting hangs until I realised I should try flushing the
DDR FIFO register and lo and behold, hangs stopped occuring.

I've put in a few DDR flushes here and there in case people decide to
reuse some of these functions.  It's very very likely they're almost
all superflous.

To test:

* Connect to a network with a _lot_ of broadcast traffic
* Do this:
  # while true; do ifconfig arge0 down; ifconfig arge0 up; done

This fixes the mbuf exhaustion that has been reported when the interface
state flaps up/down.
2012-03-13 06:15:20 +00:00
Juli Mallett
4ea65e2064 Remove TARGET_BIG_ENDIAN which should have been removed previously. 2012-03-12 21:26:09 +00:00
Juli Mallett
379663d70b o) Use ABI, not ISA_* options, to determine whether to compile bits if libkern
required for the ABI the kernel is being built for.
   XXX This is implemented in a kind-of nasty way that involves including source
       files, but it's still an improvement.
o) Retire ISA_* options since they're unused and were always wrong.
2012-03-12 21:25:32 +00:00
Adrian Chadd
6ff44ffc53 Configuration changes/updates!
* enable ALQ and net80211/ath ALQ logging by default, to make it possible
  to get debug register traces.
* Update some comments
* Enable HWPMC for testing.
2012-03-12 20:32:23 +00:00
Juli Mallett
fee74cf7e8 Use 64-bit bus space constants on 64-bit kernels. 2012-03-12 18:56:16 +00:00
Juli Mallett
11ca697ba5 Remove more unused stuff, primarily a set of (unused, thankfully) PIO
functions.

Adjust nearby style of one assembly function END().
2012-03-12 18:10:01 +00:00
Juli Mallett
c8b31c8f20 Remove more unused code and declarations, and add dire warnings to the 64-bit
atomic ops used by 32-bit kernels.
2012-03-12 08:13:04 +00:00
Juli Mallett
312af517e3 Remove platform APIs which are not used by any code and which had only stub
implementations or no implementation on all platforms.

Some of these functions might be good ideas, but their semantics were unclear
given the lack of implementation, and an unlucky porter could be fooled into
trying to implement them or, worse, being baffled when something like
platform_trap_enter() failed to be called.
2012-03-12 07:34:15 +00:00
Oleksandr Tymoshenko
2a0fa68aca - Rename apb_intr to apb_filter since it's a filter handler
- Pass interrupt trapframe for handlers dow the chain
- Add PMC interrupt handler
    PMC interrupt is a special case, so we want handle it as soon as possible
    with minimum overhead. So we handle it apb filter routine.
2012-03-12 01:23:09 +00:00
Adrian Chadd
f0dc1b857c Begin modifying the PB92 config file to actually generate a flashable,
bootable image.

The kernel has to fit inside an 896KiB area in a 4MB SPI flash.
So a bunch of stuff can't be included (and more is to come), including
(unfortunately) IPv6.

TODO:

* GPIO modules need to be created
* Shrink the image a bit more by removing some of the CAM layer debugging
  strings.
2012-03-12 01:15:58 +00:00
Juli Mallett
e889b2b09e We've supported 64-bit PTEs for some time. 2012-03-11 22:17:01 +00:00
Juli Mallett
b5acc0d618 Disable the Simple Executive's error decoding/reporting code. 2012-03-11 06:55:17 +00:00
Juli Mallett
dc4ee6ca91 Merge the Cavium Octeon SDK 2.3.0 Simple Executive code and update FreeBSD to
make use of it where possible.

This primarily brings in support for newer hardware, and FreeBSD is not yet
able to support the abundance of IRQs on new hardware and many features in the
Ethernet driver.

Because of the changes to IRQs in the Simple Executive, we have to maintain our
own list of Octeon IRQs now, which probably can be pared-down and be specific
to the CIU interrupt unit soon, and when other interrupt mechanisms are added
they can maintain their own definitions.

Remove unmasking of interrupts from within the UART device now that the
function used is no longer present in the Simple Executive.  The unmasking
seems to have been gratuitous as this is more properly handled by the buses
above the UART device, and seems to work on that basis.
2012-03-11 06:17:49 +00:00
Juli Mallett
ecdb6b0261 Fix promiscuous mode with if_octm:
o) The MAC set must occur before the multicast list is set up as the former
   will enable the CAM unconditionally, while promiscuous mode disables it,
   so if promiscuous mode is to be set this must occur after the MAC is
   programmed.
o) The multicast list must be set up unconditionally as even if flags have
   not changed, if the interface has gone through a reinitialization, the
   state of the CAM as changed by the MAC initialization could be incorrect.
o) Call octm_init when flags change, even if the interface is already running.
2012-03-11 00:34:14 +00:00
Juli Mallett
86ce6e9fda Remove some headers not used by kernel or world and which are not present in
other ports.
2012-03-10 23:27:03 +00:00
Juli Mallett
21535672bb Fix reversed logic in previous commit that broke build and earned me quite the
pointy hat.

Submitted by:	bz
2012-03-10 18:35:38 +00:00
Juli Mallett
fff491331e Use ABI to determine bus_addr_t for cnMIPS. 2012-03-10 07:54:41 +00:00
Juli Mallett
4f32220bf6 o) Remove some CPU_CNMIPS-related magical thinking about the status register's
contents for user programs.
o) Conditionalize the installation of an XTLB handler on ABI, not CPU family.
2012-03-10 06:54:37 +00:00
Juli Mallett
fd71d13eb6 Get rid of mainbus.c. The version in nexus.c is being used and is
perfectly-sufficient and equally-crufty.
2012-03-10 06:45:21 +00:00
Juli Mallett
4b6b28c350 Don't truncate physical addresses to 32-bits. 2012-03-10 06:43:41 +00:00
Juli Mallett
13a7423bf5 Reduce diffs with freebsd32_sysarch. 2012-03-10 06:31:28 +00:00
Juli Mallett
fb2a44f292 o) Bump INTRCOUNT_COUNT to 256, since Octeon already has >128.
XXX It would be good to use a better way to size intrcnt.
o) Fix literal 4s that are supposed to be sizeof (u_long).
   XXX Why the * 2 here?  Is this an artifact of a different system that this
       code came from?  We seem to allocate twice as much space for intrcnt
       as we admit to in sintrcnt.
2012-03-10 05:38:04 +00:00
Juli Mallett
9ea99cd3b5 "Did you still want the not yet? I think we just arrived at yet."
Submitted by:	thompsa
2012-03-09 09:32:20 +00:00
Juli Mallett
f6f8319094 Enable COMPAT_FREEBSD32 for the Octeon kernel config by default. 2012-03-09 07:53:44 +00:00
Juli Mallett
3812e6817b Get rid of duplicated versions of the KSU bits. 2012-03-06 23:08:02 +00:00
Aleksandr Rybalko
7283f2ff0f Break long lines.
Approved by:	adri (mentor)
2012-03-06 22:45:54 +00:00
Aleksandr Rybalko
b906a7a912 Remove EoL whitespaces.
Approved by:	adri (mentor)
2012-03-06 22:16:10 +00:00
Juli Mallett
e13dfc355c Remove unused file. 2012-03-06 20:23:29 +00:00
Attilio Rao
9c170fd168 Disable the option VFS_ALLOW_NONMPSAFE by default on all the supported
platforms.
This will make every attempt to mount a non-mpsafe filesystem to the
kernel forbidden, unless it is expressely compiled with
VFS_ALLOW_NONMPSAFE option.

This patch is part of the effort of killing non-MPSAFE filesystems
from the tree.

No MFC is expected for this patch.
2012-03-06 20:01:25 +00:00
Juli Mallett
723616952d At the risk of reducing source compatibility with old NetBSD and Sprite:
o) Get rid of some unused macros related to features we don't intend to
   provide.
o) Get rid of macro definitions for MIPS-I CPUs.  We are not likely to
   support anything that predartes MIPS-III.
o) Respell MIPS3_* macros as MIPS_*, which is how most of them were being
   used already.
o) Eliminate a duplicate and mostly-unused set of exception vector macros.

There's still considerable duplication and lots more obsolete in our headers,
but this reduces one of the larger files to a size where one could reckon
about the correctness of its contents with a mere few hours of contemplation.

There is, of course, a question of whether we need definitions for fields,
registers and configurations that we are unlikely to ever use or implement,
even if they're not obsolete since 1991.  FreeBSD is not a processor
reference manual, and things that aren't used may be wrong, or may be
duplicated because nobody could possibly actually know whether they're
already defined.
2012-03-06 19:01:32 +00:00