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freebsd-nq/sys/dev/sis/if_sis.c

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/* -> /*- for license, minor formatting changes
2005-01-07 02:29:27 +00:00
/*-
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
* Copyright (c) 2005 Poul-Henning Kamp <phk@FreeBSD.org>
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
* Copyright (c) 1997, 1998, 1999
* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Bill Paul.
* 4. Neither the name of the author nor the names of any co-contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*/
Remove duplicate FBSDID's, move others to their right place.
2003-11-14 17:16:58 +00:00
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
/*
* SiS 900/SiS 7016 fast ethernet PCI NIC driver. Datasheets are
* available from http://www.sis.com.tw.
*
Fix up the sis driver, largely to improve the NatSemi DP83815 support: - Modify the driver to poll the link state and positively set the MAC to full or half duplex as needed. Previously, it was possible for the MAC to remain in half duplex even though the PHY had negotiated full duplex with its link partner, which would result in bursty performance. - Program some of the NatSemi's registers as specified by the datasheet. The manual says these are necessary for "optimum perofrmance," though a couple of them are marked as reserved in the register map. *shrug* - Select the TX DMA burst size correctly for 10 and 100mbps modes. Previously I was using 64 bytes in both modes, which worked in 100mbps mode, but resulting in spotty performance in 10mbps. 32 bytes works much better; without this change, the natsemi chip yields piss poor performance at 10mbps. With these fixes, the NatSemi chip finally performs to my satisfaction. I should be merging the support for this controller into -stable shortly. Phew.
2000-08-22 23:26:51 +00:00
* This driver also supports the NatSemi DP83815. Datasheets are
* available from http://www.national.com.
*
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
* Written by Bill Paul <wpaul@ee.columbia.edu>
* Electrical Engineering Department
* Columbia University, New York City
*/
/*
* The SiS 900 is a fairly simple chip. It uses bus master DMA with
* simple TX and RX descriptors of 3 longwords in size. The receiver
* has a single perfect filter entry for the station address and a
* 128-bit multicast hash table. The SiS 900 has a built-in MII-based
* transceiver while the 7016 requires an external transceiver chip.
* Both chips offer the standard bit-bang MII interface as well as
* an enchanced PHY interface which simplifies accessing MII registers.
*
* The only downside to this chipset is that RX descriptors must be
* longword aligned.
*/
- Don't pollute opt_global.h with DEVICE_POLLING and introduce opt_device_polling.h - Include opt_device_polling.h into appropriate files. - Embrace with HAVE_KERNEL_OPTION_HEADERS the include in the files that can be compiled as loadable modules. Reviewed by: bde
2005-10-05 10:09:17 +00:00
#ifdef HAVE_KERNEL_OPTION_HEADERS
#include "opt_device_polling.h"
#endif
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
#include <sys/param.h>
#include <sys/systm.h>
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
#include <sys/bus.h>
#include <sys/endian.h>
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
#include <sys/kernel.h>
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
#include <sys/lock.h>
#include <sys/malloc.h>
#include <sys/mbuf.h>
Add some missing <sys/module.h> includes which are masked by the one on death-row in <sys/kernel.h>
2004-05-30 17:57:46 +00:00
#include <sys/module.h>
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
#include <sys/socket.h>
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
#include <sys/sockio.h>
Unlike most other controllers, NS DP83815/DP83816 controllers seem to pad with 0xFF when it encounter short frames. According to RFC 1042 the pad bytes should be 0x00. Because manual padding consumes extra CPU cycles, introduce a new tunable which controls the padding behavior. Turning this tunable on will have driver pad manually but it's disabled by default. Users can enable software padding by setting the following tunable to non-zero value. dev.sis.%d.manual_pad="1" PR: kern/35422 (patch not used)
2010-09-02 18:10:11 +00:00
#include <sys/sysctl.h>
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
#include <net/if.h>
The r48589 promised to remove implicit inclusion of if_var.h soon. Prepare to this event, adding if_var.h to files that do need it. Also, include all includes that now are included due to implicit pollution via if_var.h Sponsored by: Netflix Sponsored by: Nginx, Inc.
2013-10-26 17:58:36 +00:00
#include <net/if_var.h>
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
#include <net/if_arp.h>
#include <net/ethernet.h>
#include <net/if_dl.h>
#include <net/if_media.h>
Add VLAN support. MFC after: 7 days
2001-12-05 09:34:28 +00:00
#include <net/if_types.h>
#include <net/if_vlan_var.h>
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
#include <net/bpf.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/rman.h>
#include <dev/mii/mii.h>
- Import the common MII bitbang'ing code from NetBSD and convert drivers to take advantage of it instead of duplicating it. This reduces the size of the i386 GENERIC kernel by about 4k. The only potential in-tree user left unconverted is xe(4), which generally should be changed to use miibus(4) instead of implementing PHY handling on its own, as otherwise it makes not much sense to add a dependency on miibus(4)/mii_bitbang(4) to xe(4) just for the MII bitbang'ing code. The common MII bitbang'ing code also is useful in the embedded space for using GPIO pins to implement MII access. - Based on lessons learnt with dc(4) (see r185750), add bus barriers to the MII bitbang read and write functions of the other drivers converted in order to ensure the intended ordering. Given that register access via an index register as well as register bank/window switching is subject to the same problem, also add bus barriers to the respective functions of smc(4), tl(4) and xl(4). - Sprinkle some const. Thanks to the following testers: Andrew Bliznak (nge(4)), nwhitehorn@ (bm(4)), yongari@ (sis(4) and ste(4)) Thanks to Hans-Joerg Sirtl for supplying hardware to test stge(4). Reviewed by: yongari (subset of drivers) Obtained from: NetBSD (partially)
2011-11-01 16:13:59 +00:00
#include <dev/mii/mii_bitbang.h>
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
#include <dev/mii/miivar.h>
Prefer new location of pci include files (which have only been in the tree for two or more years now), except in a few places where there's code to be compatible with older versions of FreeBSD.
2003-08-22 07:20:27 +00:00
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
#define SIS_USEIOSPACE
Move sis to sys/dev/sis for consistency.
2008-08-10 10:00:14 +00:00
#include <dev/sis/if_sisreg.h>
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
- Express hard dependencies on bus (pci, isa, pccard) and network layer (ether). - Don't abuse module names to facilitate ifconfig module loading; such abuse isn't really needed. (And if we do need type information associated with a module then we should make it explicit and not use hacks.)
2003-04-15 06:37:30 +00:00
MODULE_DEPEND(sis, pci, 1, 1, 1);
MODULE_DEPEND(sis, ether, 1, 1, 1);
Depend on miibus. Note that if_aue doesn't strictly depend on usb because it uses the method interface for calls rather than using internal symbols, and because it's a child driver of usb and therefore will not try and do anything unless the parent usb code is loaded at some point. if_aue does strictly depend on miibus as it will fail to link if it is missing.
2000-04-29 13:41:57 +00:00
MODULE_DEPEND(sis, miibus, 1, 1, 1);
Replace FreeBSD 3.x syntax (controller miibus0) with 4.x syntax (device miibus) in time for 7.0 :-)
2005-10-22 05:06:55 +00:00
/* "device miibus" required. See GENERIC if you get errors here. */
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
#include "miibus_if.h"
Move code macros from if_sis*reg*.h to if_sis.*c*
2005-09-20 09:52:53 +00:00
#define SIS_LOCK(_sc) mtx_lock(&(_sc)->sis_mtx)
#define SIS_UNLOCK(_sc) mtx_unlock(&(_sc)->sis_mtx)
#define SIS_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sis_mtx, MA_OWNED)
/*
* register space access macros
*/
Use the new bus_space/resource convenience functions.
2005-09-24 20:46:02 +00:00
#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->sis_res[0], reg, val)
Move code macros from if_sis*reg*.h to if_sis.*c*
2005-09-20 09:52:53 +00:00
Use the new bus_space/resource convenience functions.
2005-09-24 20:46:02 +00:00
#define CSR_READ_4(sc, reg) bus_read_4(sc->sis_res[0], reg)
Move code macros from if_sis*reg*.h to if_sis.*c*
2005-09-20 09:52:53 +00:00
Use the new bus_space/resource convenience functions.
2005-09-24 20:46:02 +00:00
#define CSR_READ_2(sc, reg) bus_read_2(sc->sis_res[0], reg)
Move code macros from if_sis*reg*.h to if_sis.*c*
2005-09-20 09:52:53 +00:00
- Import the common MII bitbang'ing code from NetBSD and convert drivers to take advantage of it instead of duplicating it. This reduces the size of the i386 GENERIC kernel by about 4k. The only potential in-tree user left unconverted is xe(4), which generally should be changed to use miibus(4) instead of implementing PHY handling on its own, as otherwise it makes not much sense to add a dependency on miibus(4)/mii_bitbang(4) to xe(4) just for the MII bitbang'ing code. The common MII bitbang'ing code also is useful in the embedded space for using GPIO pins to implement MII access. - Based on lessons learnt with dc(4) (see r185750), add bus barriers to the MII bitbang read and write functions of the other drivers converted in order to ensure the intended ordering. Given that register access via an index register as well as register bank/window switching is subject to the same problem, also add bus barriers to the respective functions of smc(4), tl(4) and xl(4). - Sprinkle some const. Thanks to the following testers: Andrew Bliznak (nge(4)), nwhitehorn@ (bm(4)), yongari@ (sis(4) and ste(4)) Thanks to Hans-Joerg Sirtl for supplying hardware to test stge(4). Reviewed by: yongari (subset of drivers) Obtained from: NetBSD (partially)
2011-11-01 16:13:59 +00:00
#define CSR_BARRIER(sc, reg, length, flags) \
bus_barrier(sc->sis_res[0], reg, length, flags)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
/*
* Various supported device vendors/types and their names.
*/
Remove duplicate const specifiers in many drivers (I hope I got all of them, please let me know if not). Most of these are of the form: static const struct bzzt_type { [...list of members...] } const bzzt_devs[] = { [...list of initializers...] }; The second const is unnecessary, as arrays cannot be modified anyway, and if the elements are const, the whole thing is const automatically (e.g. it is placed in .rodata). I have verified this does not change the binary output of a full kernel build (except for build timestamps embedded in the object files). Reviewed by: yongari, marius MFC after: 1 week
2012-11-05 19:16:27 +00:00
static const struct sis_type sis_devs[] = {
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{ SIS_VENDORID, SIS_DEVICEID_900, "SiS 900 10/100BaseTX" },
{ SIS_VENDORID, SIS_DEVICEID_7016, "SiS 7016 10/100BaseTX" },
Examine and record the Silicon Revision Register on NS parts. We can't update the device description in attach (why not ?), so we device_print() what we find. Conditionalize the short cable fix on this being older than rev 16A. Call device_printf() when we apply short cable fix. Include interrupt hold-off setting for rev 16+ under "#ifdef notyet" The device_printf()'s will go under bootverbose once the various issues have settled a bit.
2003-09-03 07:40:04 +00:00
{ NS_VENDORID, NS_DEVICEID_DP83815, "NatSemi DP8381[56] 10/100BaseTX" },
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{ 0, 0, NULL }
};
Eliminate a bunch of unnecessary prototypes.
2005-01-06 23:26:13 +00:00
static int sis_detach(device_t);
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
static __inline void sis_discard_rxbuf(struct sis_rxdesc *);
static int sis_dma_alloc(struct sis_softc *);
static void sis_dma_free(struct sis_softc *);
static int sis_dma_ring_alloc(struct sis_softc *, bus_size_t, bus_size_t,
bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
static void sis_dmamap_cb(void *, bus_dma_segment_t *, int, int);
#ifndef __NO_STRICT_ALIGNMENT
static __inline void sis_fixup_rx(struct mbuf *);
#endif
Eliminate a bunch of unnecessary prototypes.
2005-01-06 23:26:13 +00:00
static void sis_ifmedia_sts(struct ifnet *, struct ifmediareq *);
static int sis_ifmedia_upd(struct ifnet *);
static void sis_init(void *);
static void sis_initl(struct sis_softc *);
static void sis_intr(void *);
static int sis_ioctl(struct ifnet *, u_long, caddr_t);
- Import the common MII bitbang'ing code from NetBSD and convert drivers to take advantage of it instead of duplicating it. This reduces the size of the i386 GENERIC kernel by about 4k. The only potential in-tree user left unconverted is xe(4), which generally should be changed to use miibus(4) instead of implementing PHY handling on its own, as otherwise it makes not much sense to add a dependency on miibus(4)/mii_bitbang(4) to xe(4) just for the MII bitbang'ing code. The common MII bitbang'ing code also is useful in the embedded space for using GPIO pins to implement MII access. - Based on lessons learnt with dc(4) (see r185750), add bus barriers to the MII bitbang read and write functions of the other drivers converted in order to ensure the intended ordering. Given that register access via an index register as well as register bank/window switching is subject to the same problem, also add bus barriers to the respective functions of smc(4), tl(4) and xl(4). - Sprinkle some const. Thanks to the following testers: Andrew Bliznak (nge(4)), nwhitehorn@ (bm(4)), yongari@ (sis(4) and ste(4)) Thanks to Hans-Joerg Sirtl for supplying hardware to test stge(4). Reviewed by: yongari (subset of drivers) Obtained from: NetBSD (partially)
2011-11-01 16:13:59 +00:00
static uint32_t sis_mii_bitbang_read(device_t);
static void sis_mii_bitbang_write(device_t, uint32_t);
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
static int sis_newbuf(struct sis_softc *, struct sis_rxdesc *);
Initial WOL support. NS DP8315 was tested but SiS900/SiS7016 was not tested. While I'm here, clean up SIOCSIFCAP handler.
2010-09-03 00:34:45 +00:00
static int sis_resume(device_t);
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
static int sis_rxeof(struct sis_softc *);
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
static void sis_rxfilter(struct sis_softc *);
static void sis_rxfilter_ns(struct sis_softc *);
static void sis_rxfilter_sis(struct sis_softc *);
Eliminate a bunch of unnecessary prototypes.
2005-01-06 23:26:13 +00:00
static void sis_start(struct ifnet *);
static void sis_startl(struct ifnet *);
static void sis_stop(struct sis_softc *);
Initial WOL support. NS DP8315 was tested but SiS900/SiS7016 was not tested. While I'm here, clean up SIOCSIFCAP handler.
2010-09-03 00:34:45 +00:00
static int sis_suspend(device_t);
Unlike most other controllers, NS DP83815/DP83816 controllers seem to pad with 0xFF when it encounter short frames. According to RFC 1042 the pad bytes should be 0x00. Because manual padding consumes extra CPU cycles, introduce a new tunable which controls the padding behavior. Turning this tunable on will have driver pad manually but it's disabled by default. Users can enable software padding by setting the following tunable to non-zero value. dev.sis.%d.manual_pad="1" PR: kern/35422 (patch not used)
2010-09-02 18:10:11 +00:00
static void sis_add_sysctls(struct sis_softc *);
Convert sis(4) to use its own watchdog procedure. Submitted by: Florian C. Smeets <flo kasimir com>
2007-02-24 14:27:36 +00:00
static void sis_watchdog(struct sis_softc *);
Initial WOL support. NS DP8315 was tested but SiS900/SiS7016 was not tested. While I'm here, clean up SIOCSIFCAP handler.
2010-09-03 00:34:45 +00:00
static void sis_wol(struct sis_softc *);
Apply patch to add support for the intergrated ethernet in the SiS630E chipset. The MAC address is stored in the APC CMOS RAM and we have to commit trememdous evil in order to read it. The code to do this is only activated on the i386 platform. Thanks to Cameron Grant for providing access to a test box for me to tinker with. This will fix the problem where the sis driver ends up with a station address of 00:00:00:00:00:00 on boards that use the 630E chipset.
2001-02-09 00:45:29 +00:00
- Import the common MII bitbang'ing code from NetBSD and convert drivers to take advantage of it instead of duplicating it. This reduces the size of the i386 GENERIC kernel by about 4k. The only potential in-tree user left unconverted is xe(4), which generally should be changed to use miibus(4) instead of implementing PHY handling on its own, as otherwise it makes not much sense to add a dependency on miibus(4)/mii_bitbang(4) to xe(4) just for the MII bitbang'ing code. The common MII bitbang'ing code also is useful in the embedded space for using GPIO pins to implement MII access. - Based on lessons learnt with dc(4) (see r185750), add bus barriers to the MII bitbang read and write functions of the other drivers converted in order to ensure the intended ordering. Given that register access via an index register as well as register bank/window switching is subject to the same problem, also add bus barriers to the respective functions of smc(4), tl(4) and xl(4). - Sprinkle some const. Thanks to the following testers: Andrew Bliznak (nge(4)), nwhitehorn@ (bm(4)), yongari@ (sis(4) and ste(4)) Thanks to Hans-Joerg Sirtl for supplying hardware to test stge(4). Reviewed by: yongari (subset of drivers) Obtained from: NetBSD (partially)
2011-11-01 16:13:59 +00:00
/*
* MII bit-bang glue
*/
static const struct mii_bitbang_ops sis_mii_bitbang_ops = {
sis_mii_bitbang_read,
sis_mii_bitbang_write,
{
SIS_MII_DATA, /* MII_BIT_MDO */
SIS_MII_DATA, /* MII_BIT_MDI */
SIS_MII_CLK, /* MII_BIT_MDC */
SIS_MII_DIR, /* MII_BIT_DIR_HOST_PHY */
0, /* MII_BIT_DIR_PHY_HOST */
}
};
Use the new bus_space/resource convenience functions.
2005-09-24 20:46:02 +00:00
static struct resource_spec sis_res_spec[] = {
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
#ifdef SIS_USEIOSPACE
Use the new bus_space/resource convenience functions.
2005-09-24 20:46:02 +00:00
{ SYS_RES_IOPORT, SIS_PCI_LOIO, RF_ACTIVE},
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
#else
Use the new bus_space/resource convenience functions.
2005-09-24 20:46:02 +00:00
{ SYS_RES_MEMORY, SIS_PCI_LOMEM, RF_ACTIVE},
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
#endif
Use the new bus_space/resource convenience functions.
2005-09-24 20:46:02 +00:00
{ SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE},
{ -1, 0 }
};
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
#define SIS_SETBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, \
CSR_READ_4(sc, reg) | (x))
#define SIS_CLRBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, \
CSR_READ_4(sc, reg) & ~(x))
#define SIO_SET(x) \
CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) | x)
#define SIO_CLR(x) \
CSR_WRITE_4(sc, SIS_EECTL, CSR_READ_4(sc, SIS_EECTL) & ~x)
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
/*
* Routine to reverse the bits in a word. Stolen almost
* verbatim from /usr/games/fortune.
*/
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
static uint16_t
sis_reverse(uint16_t n)
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
{
n = ((n >> 1) & 0x5555) | ((n << 1) & 0xaaaa);
n = ((n >> 2) & 0x3333) | ((n << 2) & 0xcccc);
n = ((n >> 4) & 0x0f0f) | ((n << 4) & 0xf0f0);
n = ((n >> 8) & 0x00ff) | ((n << 8) & 0xff00);
style(9) - space after keywords.
2010-09-01 18:39:35 +00:00
return (n);
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
}
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static void
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
sis_delay(struct sis_softc *sc)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
int idx;
for (idx = (300 / 33) + 1; idx > 0; idx--)
CSR_READ_4(sc, SIS_CSR);
}
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static void
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
sis_eeprom_idle(struct sis_softc *sc)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
Don't declare variables "register", the compiler ought to know what to do.
2005-01-05 09:02:05 +00:00
int i;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
SIO_SET(SIS_EECTL_CSEL);
sis_delay(sc);
SIO_SET(SIS_EECTL_CLK);
sis_delay(sc);
for (i = 0; i < 25; i++) {
SIO_CLR(SIS_EECTL_CLK);
sis_delay(sc);
SIO_SET(SIS_EECTL_CLK);
sis_delay(sc);
}
SIO_CLR(SIS_EECTL_CLK);
sis_delay(sc);
SIO_CLR(SIS_EECTL_CSEL);
sis_delay(sc);
CSR_WRITE_4(sc, SIS_EECTL, 0x00000000);
}
/*
* Send a read command and address to the EEPROM, check for ACK.
*/
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static void
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
sis_eeprom_putbyte(struct sis_softc *sc, int addr)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
Don't declare variables "register", the compiler ought to know what to do.
2005-01-05 09:02:05 +00:00
int d, i;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
d = addr | SIS_EECMD_READ;
/*
* Feed in each bit and stobe the clock.
*/
for (i = 0x400; i; i >>= 1) {
if (d & i) {
SIO_SET(SIS_EECTL_DIN);
} else {
SIO_CLR(SIS_EECTL_DIN);
}
sis_delay(sc);
SIO_SET(SIS_EECTL_CLK);
sis_delay(sc);
SIO_CLR(SIS_EECTL_CLK);
sis_delay(sc);
}
}
/*
* Read a word of data stored in the EEPROM at address 'addr.'
*/
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static void
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
sis_eeprom_getword(struct sis_softc *sc, int addr, uint16_t *dest)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
Don't declare variables "register", the compiler ought to know what to do.
2005-01-05 09:02:05 +00:00
int i;
s/u_intXX_t/uintXX_t/g
2010-09-01 19:53:15 +00:00
uint16_t word = 0;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
/* Force EEPROM to idle state. */
sis_eeprom_idle(sc);
/* Enter EEPROM access mode. */
sis_delay(sc);
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
SIO_CLR(SIS_EECTL_CLK);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
sis_delay(sc);
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
SIO_SET(SIS_EECTL_CSEL);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
sis_delay(sc);
/*
* Send address of word we want to read.
*/
sis_eeprom_putbyte(sc, addr);
/*
* Start reading bits from EEPROM.
*/
for (i = 0x8000; i; i >>= 1) {
SIO_SET(SIS_EECTL_CLK);
sis_delay(sc);
if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECTL_DOUT)
word |= i;
sis_delay(sc);
SIO_CLR(SIS_EECTL_CLK);
sis_delay(sc);
}
/* Turn off EEPROM access mode. */
sis_eeprom_idle(sc);
*dest = word;
}
/*
* Read a sequence of words from the EEPROM.
*/
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static void
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
sis_read_eeprom(struct sis_softc *sc, caddr_t dest, int off, int cnt, int swap)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
int i;
s/u_intXX_t/uintXX_t/g
2010-09-01 19:53:15 +00:00
uint16_t word = 0, *ptr;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
for (i = 0; i < cnt; i++) {
sis_eeprom_getword(sc, off + i, &word);
s/u_intXX_t/uintXX_t/g
2010-09-01 19:53:15 +00:00
ptr = (uint16_t *)(dest + (i * 2));
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
if (swap)
*ptr = ntohs(word);
else
*ptr = word;
}
}
Bring rev 1.31 to the AMD64 platform. This adds support for the SiS intergrated NIC on some Athlon64 motherboards. The MAC address is stored in the APC CMOS RAM and this fixes the sis driver ending up with a 00:00:00:00:00:00 MAC address. Submitted by: Stasys Smailys <ssmailys@komvista.lt>
2005-03-28 18:06:44 +00:00
#if defined(__i386__) || defined(__amd64__)
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static device_t
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
sis_find_bridge(device_t dev)
Apply patch to add support for the intergrated ethernet in the SiS630E chipset. The MAC address is stored in the APC CMOS RAM and we have to commit trememdous evil in order to read it. The code to do this is only activated on the i386 platform. Thanks to Cameron Grant for providing access to a test box for me to tinker with. This will fix the problem where the sis driver ends up with a station address of 00:00:00:00:00:00 on boards that use the 630E chipset.
2001-02-09 00:45:29 +00:00
{
devclass_t pci_devclass;
device_t *pci_devices;
int pci_count = 0;
device_t *pci_children;
int pci_childcount = 0;
device_t *busp, *childp;
Fix access-after-free bug added in revision 1.31. Detected by: INVARIANTS MFC after: 2 days
2001-12-15 19:59:28 +00:00
device_t child = NULL;
Apply patch to add support for the intergrated ethernet in the SiS630E chipset. The MAC address is stored in the APC CMOS RAM and we have to commit trememdous evil in order to read it. The code to do this is only activated on the i386 platform. Thanks to Cameron Grant for providing access to a test box for me to tinker with. This will fix the problem where the sis driver ends up with a station address of 00:00:00:00:00:00 on boards that use the 630E chipset.
2001-02-09 00:45:29 +00:00
int i, j;
if ((pci_devclass = devclass_find("pci")) == NULL)
style(9) - space after keywords.
2010-09-01 18:39:35 +00:00
return (NULL);
Apply patch to add support for the intergrated ethernet in the SiS630E chipset. The MAC address is stored in the APC CMOS RAM and we have to commit trememdous evil in order to read it. The code to do this is only activated on the i386 platform. Thanks to Cameron Grant for providing access to a test box for me to tinker with. This will fix the problem where the sis driver ends up with a station address of 00:00:00:00:00:00 on boards that use the 630E chipset.
2001-02-09 00:45:29 +00:00
devclass_get_devices(pci_devclass, &pci_devices, &pci_count);
for (i = 0, busp = pci_devices; i < pci_count; i++, busp++) {
There actually were bugs in the original handling that I missed last night. Free the children after each pci bus that is searched. Otherwise we leak them. With free in the new place, we also have to free children before going to done when we find the device we're looking for. Also, if we can't get the children of a device, just ignore that bus.
2008-08-23 15:34:31 +00:00
if (device_get_children(*busp, &pci_children, &pci_childcount))
continue;
Apply patch to add support for the intergrated ethernet in the SiS630E chipset. The MAC address is stored in the APC CMOS RAM and we have to commit trememdous evil in order to read it. The code to do this is only activated on the i386 platform. Thanks to Cameron Grant for providing access to a test box for me to tinker with. This will fix the problem where the sis driver ends up with a station address of 00:00:00:00:00:00 on boards that use the 630E chipset.
2001-02-09 00:45:29 +00:00
for (j = 0, childp = pci_children;
j < pci_childcount; j++, childp++) {
if (pci_get_vendor(*childp) == SIS_VENDORID &&
pci_get_device(*childp) == 0x0008) {
Fix access-after-free bug added in revision 1.31. Detected by: INVARIANTS MFC after: 2 days
2001-12-15 19:59:28 +00:00
child = *childp;
There actually were bugs in the original handling that I missed last night. Free the children after each pci bus that is searched. Otherwise we leak them. With free in the new place, we also have to free children before going to done when we find the device we're looking for. Also, if we can't get the children of a device, just ignore that bus.
2008-08-23 15:34:31 +00:00
free(pci_children, M_TEMP);
Fix access-after-free bug added in revision 1.31. Detected by: INVARIANTS MFC after: 2 days
2001-12-15 19:59:28 +00:00
goto done;
Apply patch to add support for the intergrated ethernet in the SiS630E chipset. The MAC address is stored in the APC CMOS RAM and we have to commit trememdous evil in order to read it. The code to do this is only activated on the i386 platform. Thanks to Cameron Grant for providing access to a test box for me to tinker with. This will fix the problem where the sis driver ends up with a station address of 00:00:00:00:00:00 on boards that use the 630E chipset.
2001-02-09 00:45:29 +00:00
}
}
There actually were bugs in the original handling that I missed last night. Free the children after each pci bus that is searched. Otherwise we leak them. With free in the new place, we also have to free children before going to done when we find the device we're looking for. Also, if we can't get the children of a device, just ignore that bus.
2008-08-23 15:34:31 +00:00
free(pci_children, M_TEMP);
Apply patch to add support for the intergrated ethernet in the SiS630E chipset. The MAC address is stored in the APC CMOS RAM and we have to commit trememdous evil in order to read it. The code to do this is only activated on the i386 platform. Thanks to Cameron Grant for providing access to a test box for me to tinker with. This will fix the problem where the sis driver ends up with a station address of 00:00:00:00:00:00 on boards that use the 630E chipset.
2001-02-09 00:45:29 +00:00
}
Fix access-after-free bug added in revision 1.31. Detected by: INVARIANTS MFC after: 2 days
2001-12-15 19:59:28 +00:00
done:
Apply patch to add support for the intergrated ethernet in the SiS630E chipset. The MAC address is stored in the APC CMOS RAM and we have to commit trememdous evil in order to read it. The code to do this is only activated on the i386 platform. Thanks to Cameron Grant for providing access to a test box for me to tinker with. This will fix the problem where the sis driver ends up with a station address of 00:00:00:00:00:00 on boards that use the 630E chipset.
2001-02-09 00:45:29 +00:00
free(pci_devices, M_TEMP);
style(9) - space after keywords.
2010-09-01 18:39:35 +00:00
return (child);
Apply patch to add support for the intergrated ethernet in the SiS630E chipset. The MAC address is stored in the APC CMOS RAM and we have to commit trememdous evil in order to read it. The code to do this is only activated on the i386 platform. Thanks to Cameron Grant for providing access to a test box for me to tinker with. This will fix the problem where the sis driver ends up with a station address of 00:00:00:00:00:00 on boards that use the 630E chipset.
2001-02-09 00:45:29 +00:00
}
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static void
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
sis_read_cmos(struct sis_softc *sc, device_t dev, caddr_t dest, int off, int cnt)
Apply patch to add support for the intergrated ethernet in the SiS630E chipset. The MAC address is stored in the APC CMOS RAM and we have to commit trememdous evil in order to read it. The code to do this is only activated on the i386 platform. Thanks to Cameron Grant for providing access to a test box for me to tinker with. This will fix the problem where the sis driver ends up with a station address of 00:00:00:00:00:00 on boards that use the 630E chipset.
2001-02-09 00:45:29 +00:00
{
device_t bridge;
s/u_intXX_t/uintXX_t/g
2010-09-01 19:53:15 +00:00
uint8_t reg;
Apply patch to add support for the intergrated ethernet in the SiS630E chipset. The MAC address is stored in the APC CMOS RAM and we have to commit trememdous evil in order to read it. The code to do this is only activated on the i386 platform. Thanks to Cameron Grant for providing access to a test box for me to tinker with. This will fix the problem where the sis driver ends up with a station address of 00:00:00:00:00:00 on boards that use the 630E chipset.
2001-02-09 00:45:29 +00:00
int i;
bus_space_tag_t btag;
bridge = sis_find_bridge(dev);
if (bridge == NULL)
return;
reg = pci_read_config(bridge, 0x48, 1);
pci_write_config(bridge, 0x48, reg|0x40, 1);
/* XXX */
Merge amd64 and i386 bus.h and move the resulting header to x86. Replace the original amd64 and i386 headers with stubs. Rename (AMD64|I386)_BUS_SPACE_* to X86_BUS_SPACE_* everywhere. Reviewed by: imp (previous version), jhb Approved by: kib (mentor)
2010-12-20 16:39:43 +00:00
#if defined(__amd64__) || defined(__i386__)
btag = X86_BUS_SPACE_IO;
Bring rev 1.31 to the AMD64 platform. This adds support for the SiS intergrated NIC on some Athlon64 motherboards. The MAC address is stored in the APC CMOS RAM and this fixes the sis driver ending up with a 00:00:00:00:00:00 MAC address. Submitted by: Stasys Smailys <ssmailys@komvista.lt>
2005-03-28 18:06:44 +00:00
#endif
Apply patch to add support for the intergrated ethernet in the SiS630E chipset. The MAC address is stored in the APC CMOS RAM and we have to commit trememdous evil in order to read it. The code to do this is only activated on the i386 platform. Thanks to Cameron Grant for providing access to a test box for me to tinker with. This will fix the problem where the sis driver ends up with a station address of 00:00:00:00:00:00 on boards that use the 630E chipset.
2001-02-09 00:45:29 +00:00
for (i = 0; i < cnt; i++) {
bus_space_write_1(btag, 0x0, 0x70, i + off);
*(dest + i) = bus_space_read_1(btag, 0x0, 0x71);
}
pci_write_config(bridge, 0x48, reg & ~0x40, 1);
}
Add support for newer integrated SiS 900 controllers on the 635 and 735 motherboard chipsets. We need to force the chip to reload its MAC address into the receive filter, and enable software access mode for the PHY. PR: kern/33294
2002-01-12 21:12:17 +00:00
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static void
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
sis_read_mac(struct sis_softc *sc, device_t dev, caddr_t dest)
Add support for newer integrated SiS 900 controllers on the 635 and 735 motherboard chipsets. We need to force the chip to reload its MAC address into the receive filter, and enable software access mode for the PHY. PR: kern/33294
2002-01-12 21:12:17 +00:00
{
s/u_intXX_t/uintXX_t/g
2010-09-01 19:53:15 +00:00
uint32_t filtsave, csrsave;
Add support for newer integrated SiS 900 controllers on the 635 and 735 motherboard chipsets. We need to force the chip to reload its MAC address into the receive filter, and enable software access mode for the PHY. PR: kern/33294
2002-01-12 21:12:17 +00:00
filtsave = CSR_READ_4(sc, SIS_RXFILT_CTL);
csrsave = CSR_READ_4(sc, SIS_CSR);
CSR_WRITE_4(sc, SIS_CSR, SIS_CSR_RELOAD | filtsave);
CSR_WRITE_4(sc, SIS_CSR, 0);
Remove leading and trailing white spaces. No functional changes.
2010-09-01 18:28:08 +00:00
Add support for newer integrated SiS 900 controllers on the 635 and 735 motherboard chipsets. We need to force the chip to reload its MAC address into the receive filter, and enable software access mode for the PHY. PR: kern/33294
2002-01-12 21:12:17 +00:00
CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave & ~SIS_RXFILTCTL_ENABLE);
CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
s/u_intXX_t/uintXX_t/g
2010-09-01 19:53:15 +00:00
((uint16_t *)dest)[0] = CSR_READ_2(sc, SIS_RXFILT_DATA);
Add support for newer integrated SiS 900 controllers on the 635 and 735 motherboard chipsets. We need to force the chip to reload its MAC address into the receive filter, and enable software access mode for the PHY. PR: kern/33294
2002-01-12 21:12:17 +00:00
CSR_WRITE_4(sc, SIS_RXFILT_CTL,SIS_FILTADDR_PAR1);
s/u_intXX_t/uintXX_t/g
2010-09-01 19:53:15 +00:00
((uint16_t *)dest)[1] = CSR_READ_2(sc, SIS_RXFILT_DATA);
Add support for newer integrated SiS 900 controllers on the 635 and 735 motherboard chipsets. We need to force the chip to reload its MAC address into the receive filter, and enable software access mode for the PHY. PR: kern/33294
2002-01-12 21:12:17 +00:00
CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
s/u_intXX_t/uintXX_t/g
2010-09-01 19:53:15 +00:00
((uint16_t *)dest)[2] = CSR_READ_2(sc, SIS_RXFILT_DATA);
Add support for newer integrated SiS 900 controllers on the 635 and 735 motherboard chipsets. We need to force the chip to reload its MAC address into the receive filter, and enable software access mode for the PHY. PR: kern/33294
2002-01-12 21:12:17 +00:00
CSR_WRITE_4(sc, SIS_RXFILT_CTL, filtsave);
CSR_WRITE_4(sc, SIS_CSR, csrsave);
}
Apply patch to add support for the intergrated ethernet in the SiS630E chipset. The MAC address is stored in the APC CMOS RAM and we have to commit trememdous evil in order to read it. The code to do this is only activated on the i386 platform. Thanks to Cameron Grant for providing access to a test box for me to tinker with. This will fix the problem where the sis driver ends up with a station address of 00:00:00:00:00:00 on boards that use the 630E chipset.
2001-02-09 00:45:29 +00:00
#endif
Sis no longer implements the enhanced phy control register, and phy has to be directly accessed via mdio. Patch converted to CURRENT from STABLE. Submitted by: luoqi Reviewed by: luoqi (again) MFC after: 2 weeks
2003-01-10 08:14:07 +00:00
/*
- Import the common MII bitbang'ing code from NetBSD and convert drivers to take advantage of it instead of duplicating it. This reduces the size of the i386 GENERIC kernel by about 4k. The only potential in-tree user left unconverted is xe(4), which generally should be changed to use miibus(4) instead of implementing PHY handling on its own, as otherwise it makes not much sense to add a dependency on miibus(4)/mii_bitbang(4) to xe(4) just for the MII bitbang'ing code. The common MII bitbang'ing code also is useful in the embedded space for using GPIO pins to implement MII access. - Based on lessons learnt with dc(4) (see r185750), add bus barriers to the MII bitbang read and write functions of the other drivers converted in order to ensure the intended ordering. Given that register access via an index register as well as register bank/window switching is subject to the same problem, also add bus barriers to the respective functions of smc(4), tl(4) and xl(4). - Sprinkle some const. Thanks to the following testers: Andrew Bliznak (nge(4)), nwhitehorn@ (bm(4)), yongari@ (sis(4) and ste(4)) Thanks to Hans-Joerg Sirtl for supplying hardware to test stge(4). Reviewed by: yongari (subset of drivers) Obtained from: NetBSD (partially)
2011-11-01 16:13:59 +00:00
* Read the MII serial port for the MII bit-bang module.
Sis no longer implements the enhanced phy control register, and phy has to be directly accessed via mdio. Patch converted to CURRENT from STABLE. Submitted by: luoqi Reviewed by: luoqi (again) MFC after: 2 weeks
2003-01-10 08:14:07 +00:00
*/
- Import the common MII bitbang'ing code from NetBSD and convert drivers to take advantage of it instead of duplicating it. This reduces the size of the i386 GENERIC kernel by about 4k. The only potential in-tree user left unconverted is xe(4), which generally should be changed to use miibus(4) instead of implementing PHY handling on its own, as otherwise it makes not much sense to add a dependency on miibus(4)/mii_bitbang(4) to xe(4) just for the MII bitbang'ing code. The common MII bitbang'ing code also is useful in the embedded space for using GPIO pins to implement MII access. - Based on lessons learnt with dc(4) (see r185750), add bus barriers to the MII bitbang read and write functions of the other drivers converted in order to ensure the intended ordering. Given that register access via an index register as well as register bank/window switching is subject to the same problem, also add bus barriers to the respective functions of smc(4), tl(4) and xl(4). - Sprinkle some const. Thanks to the following testers: Andrew Bliznak (nge(4)), nwhitehorn@ (bm(4)), yongari@ (sis(4) and ste(4)) Thanks to Hans-Joerg Sirtl for supplying hardware to test stge(4). Reviewed by: yongari (subset of drivers) Obtained from: NetBSD (partially)
2011-11-01 16:13:59 +00:00
static uint32_t
sis_mii_bitbang_read(device_t dev)
Sis no longer implements the enhanced phy control register, and phy has to be directly accessed via mdio. Patch converted to CURRENT from STABLE. Submitted by: luoqi Reviewed by: luoqi (again) MFC after: 2 weeks
2003-01-10 08:14:07 +00:00
{
- Import the common MII bitbang'ing code from NetBSD and convert drivers to take advantage of it instead of duplicating it. This reduces the size of the i386 GENERIC kernel by about 4k. The only potential in-tree user left unconverted is xe(4), which generally should be changed to use miibus(4) instead of implementing PHY handling on its own, as otherwise it makes not much sense to add a dependency on miibus(4)/mii_bitbang(4) to xe(4) just for the MII bitbang'ing code. The common MII bitbang'ing code also is useful in the embedded space for using GPIO pins to implement MII access. - Based on lessons learnt with dc(4) (see r185750), add bus barriers to the MII bitbang read and write functions of the other drivers converted in order to ensure the intended ordering. Given that register access via an index register as well as register bank/window switching is subject to the same problem, also add bus barriers to the respective functions of smc(4), tl(4) and xl(4). - Sprinkle some const. Thanks to the following testers: Andrew Bliznak (nge(4)), nwhitehorn@ (bm(4)), yongari@ (sis(4) and ste(4)) Thanks to Hans-Joerg Sirtl for supplying hardware to test stge(4). Reviewed by: yongari (subset of drivers) Obtained from: NetBSD (partially)
2011-11-01 16:13:59 +00:00
struct sis_softc *sc;
uint32_t val;
Remove leading and trailing white spaces. No functional changes.
2010-09-01 18:28:08 +00:00
- Import the common MII bitbang'ing code from NetBSD and convert drivers to take advantage of it instead of duplicating it. This reduces the size of the i386 GENERIC kernel by about 4k. The only potential in-tree user left unconverted is xe(4), which generally should be changed to use miibus(4) instead of implementing PHY handling on its own, as otherwise it makes not much sense to add a dependency on miibus(4)/mii_bitbang(4) to xe(4) just for the MII bitbang'ing code. The common MII bitbang'ing code also is useful in the embedded space for using GPIO pins to implement MII access. - Based on lessons learnt with dc(4) (see r185750), add bus barriers to the MII bitbang read and write functions of the other drivers converted in order to ensure the intended ordering. Given that register access via an index register as well as register bank/window switching is subject to the same problem, also add bus barriers to the respective functions of smc(4), tl(4) and xl(4). - Sprinkle some const. Thanks to the following testers: Andrew Bliznak (nge(4)), nwhitehorn@ (bm(4)), yongari@ (sis(4) and ste(4)) Thanks to Hans-Joerg Sirtl for supplying hardware to test stge(4). Reviewed by: yongari (subset of drivers) Obtained from: NetBSD (partially)
2011-11-01 16:13:59 +00:00
sc = device_get_softc(dev);
Remove leading and trailing white spaces. No functional changes.
2010-09-01 18:28:08 +00:00
- Import the common MII bitbang'ing code from NetBSD and convert drivers to take advantage of it instead of duplicating it. This reduces the size of the i386 GENERIC kernel by about 4k. The only potential in-tree user left unconverted is xe(4), which generally should be changed to use miibus(4) instead of implementing PHY handling on its own, as otherwise it makes not much sense to add a dependency on miibus(4)/mii_bitbang(4) to xe(4) just for the MII bitbang'ing code. The common MII bitbang'ing code also is useful in the embedded space for using GPIO pins to implement MII access. - Based on lessons learnt with dc(4) (see r185750), add bus barriers to the MII bitbang read and write functions of the other drivers converted in order to ensure the intended ordering. Given that register access via an index register as well as register bank/window switching is subject to the same problem, also add bus barriers to the respective functions of smc(4), tl(4) and xl(4). - Sprinkle some const. Thanks to the following testers: Andrew Bliznak (nge(4)), nwhitehorn@ (bm(4)), yongari@ (sis(4) and ste(4)) Thanks to Hans-Joerg Sirtl for supplying hardware to test stge(4). Reviewed by: yongari (subset of drivers) Obtained from: NetBSD (partially)
2011-11-01 16:13:59 +00:00
val = CSR_READ_4(sc, SIS_EECTL);
CSR_BARRIER(sc, SIS_EECTL, 4,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
return (val);
Sis no longer implements the enhanced phy control register, and phy has to be directly accessed via mdio. Patch converted to CURRENT from STABLE. Submitted by: luoqi Reviewed by: luoqi (again) MFC after: 2 weeks
2003-01-10 08:14:07 +00:00
}
Remove leading and trailing white spaces. No functional changes.
2010-09-01 18:28:08 +00:00
Sis no longer implements the enhanced phy control register, and phy has to be directly accessed via mdio. Patch converted to CURRENT from STABLE. Submitted by: luoqi Reviewed by: luoqi (again) MFC after: 2 weeks
2003-01-10 08:14:07 +00:00
/*
- Import the common MII bitbang'ing code from NetBSD and convert drivers to take advantage of it instead of duplicating it. This reduces the size of the i386 GENERIC kernel by about 4k. The only potential in-tree user left unconverted is xe(4), which generally should be changed to use miibus(4) instead of implementing PHY handling on its own, as otherwise it makes not much sense to add a dependency on miibus(4)/mii_bitbang(4) to xe(4) just for the MII bitbang'ing code. The common MII bitbang'ing code also is useful in the embedded space for using GPIO pins to implement MII access. - Based on lessons learnt with dc(4) (see r185750), add bus barriers to the MII bitbang read and write functions of the other drivers converted in order to ensure the intended ordering. Given that register access via an index register as well as register bank/window switching is subject to the same problem, also add bus barriers to the respective functions of smc(4), tl(4) and xl(4). - Sprinkle some const. Thanks to the following testers: Andrew Bliznak (nge(4)), nwhitehorn@ (bm(4)), yongari@ (sis(4) and ste(4)) Thanks to Hans-Joerg Sirtl for supplying hardware to test stge(4). Reviewed by: yongari (subset of drivers) Obtained from: NetBSD (partially)
2011-11-01 16:13:59 +00:00
* Write the MII serial port for the MII bit-bang module.
Sis no longer implements the enhanced phy control register, and phy has to be directly accessed via mdio. Patch converted to CURRENT from STABLE. Submitted by: luoqi Reviewed by: luoqi (again) MFC after: 2 weeks
2003-01-10 08:14:07 +00:00
*/
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
static void
- Import the common MII bitbang'ing code from NetBSD and convert drivers to take advantage of it instead of duplicating it. This reduces the size of the i386 GENERIC kernel by about 4k. The only potential in-tree user left unconverted is xe(4), which generally should be changed to use miibus(4) instead of implementing PHY handling on its own, as otherwise it makes not much sense to add a dependency on miibus(4)/mii_bitbang(4) to xe(4) just for the MII bitbang'ing code. The common MII bitbang'ing code also is useful in the embedded space for using GPIO pins to implement MII access. - Based on lessons learnt with dc(4) (see r185750), add bus barriers to the MII bitbang read and write functions of the other drivers converted in order to ensure the intended ordering. Given that register access via an index register as well as register bank/window switching is subject to the same problem, also add bus barriers to the respective functions of smc(4), tl(4) and xl(4). - Sprinkle some const. Thanks to the following testers: Andrew Bliznak (nge(4)), nwhitehorn@ (bm(4)), yongari@ (sis(4) and ste(4)) Thanks to Hans-Joerg Sirtl for supplying hardware to test stge(4). Reviewed by: yongari (subset of drivers) Obtained from: NetBSD (partially)
2011-11-01 16:13:59 +00:00
sis_mii_bitbang_write(device_t dev, uint32_t val)
Sis no longer implements the enhanced phy control register, and phy has to be directly accessed via mdio. Patch converted to CURRENT from STABLE. Submitted by: luoqi Reviewed by: luoqi (again) MFC after: 2 weeks
2003-01-10 08:14:07 +00:00
{
- Import the common MII bitbang'ing code from NetBSD and convert drivers to take advantage of it instead of duplicating it. This reduces the size of the i386 GENERIC kernel by about 4k. The only potential in-tree user left unconverted is xe(4), which generally should be changed to use miibus(4) instead of implementing PHY handling on its own, as otherwise it makes not much sense to add a dependency on miibus(4)/mii_bitbang(4) to xe(4) just for the MII bitbang'ing code. The common MII bitbang'ing code also is useful in the embedded space for using GPIO pins to implement MII access. - Based on lessons learnt with dc(4) (see r185750), add bus barriers to the MII bitbang read and write functions of the other drivers converted in order to ensure the intended ordering. Given that register access via an index register as well as register bank/window switching is subject to the same problem, also add bus barriers to the respective functions of smc(4), tl(4) and xl(4). - Sprinkle some const. Thanks to the following testers: Andrew Bliznak (nge(4)), nwhitehorn@ (bm(4)), yongari@ (sis(4) and ste(4)) Thanks to Hans-Joerg Sirtl for supplying hardware to test stge(4). Reviewed by: yongari (subset of drivers) Obtained from: NetBSD (partially)
2011-11-01 16:13:59 +00:00
struct sis_softc *sc;
Remove leading and trailing white spaces. No functional changes.
2010-09-01 18:28:08 +00:00
- Import the common MII bitbang'ing code from NetBSD and convert drivers to take advantage of it instead of duplicating it. This reduces the size of the i386 GENERIC kernel by about 4k. The only potential in-tree user left unconverted is xe(4), which generally should be changed to use miibus(4) instead of implementing PHY handling on its own, as otherwise it makes not much sense to add a dependency on miibus(4)/mii_bitbang(4) to xe(4) just for the MII bitbang'ing code. The common MII bitbang'ing code also is useful in the embedded space for using GPIO pins to implement MII access. - Based on lessons learnt with dc(4) (see r185750), add bus barriers to the MII bitbang read and write functions of the other drivers converted in order to ensure the intended ordering. Given that register access via an index register as well as register bank/window switching is subject to the same problem, also add bus barriers to the respective functions of smc(4), tl(4) and xl(4). - Sprinkle some const. Thanks to the following testers: Andrew Bliznak (nge(4)), nwhitehorn@ (bm(4)), yongari@ (sis(4) and ste(4)) Thanks to Hans-Joerg Sirtl for supplying hardware to test stge(4). Reviewed by: yongari (subset of drivers) Obtained from: NetBSD (partially)
2011-11-01 16:13:59 +00:00
sc = device_get_softc(dev);
Remove leading and trailing white spaces. No functional changes.
2010-09-01 18:28:08 +00:00
- Import the common MII bitbang'ing code from NetBSD and convert drivers to take advantage of it instead of duplicating it. This reduces the size of the i386 GENERIC kernel by about 4k. The only potential in-tree user left unconverted is xe(4), which generally should be changed to use miibus(4) instead of implementing PHY handling on its own, as otherwise it makes not much sense to add a dependency on miibus(4)/mii_bitbang(4) to xe(4) just for the MII bitbang'ing code. The common MII bitbang'ing code also is useful in the embedded space for using GPIO pins to implement MII access. - Based on lessons learnt with dc(4) (see r185750), add bus barriers to the MII bitbang read and write functions of the other drivers converted in order to ensure the intended ordering. Given that register access via an index register as well as register bank/window switching is subject to the same problem, also add bus barriers to the respective functions of smc(4), tl(4) and xl(4). - Sprinkle some const. Thanks to the following testers: Andrew Bliznak (nge(4)), nwhitehorn@ (bm(4)), yongari@ (sis(4) and ste(4)) Thanks to Hans-Joerg Sirtl for supplying hardware to test stge(4). Reviewed by: yongari (subset of drivers) Obtained from: NetBSD (partially)
2011-11-01 16:13:59 +00:00
CSR_WRITE_4(sc, SIS_EECTL, val);
CSR_BARRIER(sc, SIS_EECTL, 4,
BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
Sis no longer implements the enhanced phy control register, and phy has to be directly accessed via mdio. Patch converted to CURRENT from STABLE. Submitted by: luoqi Reviewed by: luoqi (again) MFC after: 2 weeks
2003-01-10 08:14:07 +00:00
}
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static int
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
sis_miibus_readreg(device_t dev, int phy, int reg)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
struct sis_softc *sc;
sc = device_get_softc(dev);
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
if (sc->sis_type == SIS_TYPE_83815) {
if (phy != 0)
style(9) - space after keywords.
2010-09-01 18:39:35 +00:00
return (0);
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
/*
* The NatSemi chip can take a while after
* a reset to come ready, during which the BMSR
* returns a value of 0. This is *never* supposed
* to happen: some of the BMSR bits are meant to
* be hardwired in the on position, and this can
* confuse the miibus code a bit during the probe
* and attach phase. So we make an effort to check
* for this condition and wait for it to clear.
*/
if (!CSR_READ_4(sc, NS_BMSR))
DELAY(1000);
Sis no longer implements the enhanced phy control register, and phy has to be directly accessed via mdio. Patch converted to CURRENT from STABLE. Submitted by: luoqi Reviewed by: luoqi (again) MFC after: 2 weeks
2003-01-10 08:14:07 +00:00
return CSR_READ_4(sc, NS_BMCR + (reg * 4));
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
}
Add PCI revision number for 630A and 900B. Enable parity error detection on 900B and 635(A). Re-add the enhanced PHY access register method again for older chipsets, they do not seem to work with all old chips. Reviewed by: phk MFC after: 7 days
2003-01-28 10:55:38 +00:00
/*
* Chipsets < SIS_635 seem not to be able to read/write
* through mdio. Use the enhanced PHY access register
* again for them.
*/
Add support for newer integrated SiS 900 controllers on the 635 and 735 motherboard chipsets. We need to force the chip to reload its MAC address into the receive filter, and enable software access mode for the PHY. PR: kern/33294
2002-01-12 21:12:17 +00:00
if (sc->sis_type == SIS_TYPE_900 &&
Add PCI revision number for 630A and 900B. Enable parity error detection on 900B and 635(A). Re-add the enhanced PHY access register method again for older chipsets, they do not seem to work with all old chips. Reviewed by: phk MFC after: 7 days
2003-01-28 10:55:38 +00:00
sc->sis_rev < SIS_REV_635) {
int i, val = 0;
if (phy != 0)
style(9) - space after keywords.
2010-09-01 18:39:35 +00:00
return (0);
Add PCI revision number for 630A and 900B. Enable parity error detection on 900B and 635(A). Re-add the enhanced PHY access register method again for older chipsets, they do not seem to work with all old chips. Reviewed by: phk MFC after: 7 days
2003-01-28 10:55:38 +00:00
CSR_WRITE_4(sc, SIS_PHYCTL,
(phy << 11) | (reg << 6) | SIS_PHYOP_READ);
SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
for (i = 0; i < SIS_TIMEOUT; i++) {
if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
break;
}
if (i == SIS_TIMEOUT) {
- Import the common MII bitbang'ing code from NetBSD and convert drivers to take advantage of it instead of duplicating it. This reduces the size of the i386 GENERIC kernel by about 4k. The only potential in-tree user left unconverted is xe(4), which generally should be changed to use miibus(4) instead of implementing PHY handling on its own, as otherwise it makes not much sense to add a dependency on miibus(4)/mii_bitbang(4) to xe(4) just for the MII bitbang'ing code. The common MII bitbang'ing code also is useful in the embedded space for using GPIO pins to implement MII access. - Based on lessons learnt with dc(4) (see r185750), add bus barriers to the MII bitbang read and write functions of the other drivers converted in order to ensure the intended ordering. Given that register access via an index register as well as register bank/window switching is subject to the same problem, also add bus barriers to the respective functions of smc(4), tl(4) and xl(4). - Sprinkle some const. Thanks to the following testers: Andrew Bliznak (nge(4)), nwhitehorn@ (bm(4)), yongari@ (sis(4) and ste(4)) Thanks to Hans-Joerg Sirtl for supplying hardware to test stge(4). Reviewed by: yongari (subset of drivers) Obtained from: NetBSD (partially)
2011-11-01 16:13:59 +00:00
device_printf(sc->sis_dev,
"PHY failed to come ready\n");
style(9) - space after keywords.
2010-09-01 18:39:35 +00:00
return (0);
Add PCI revision number for 630A and 900B. Enable parity error detection on 900B and 635(A). Re-add the enhanced PHY access register method again for older chipsets, they do not seem to work with all old chips. Reviewed by: phk MFC after: 7 days
2003-01-28 10:55:38 +00:00
}
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Add PCI revision number for 630A and 900B. Enable parity error detection on 900B and 635(A). Re-add the enhanced PHY access register method again for older chipsets, they do not seem to work with all old chips. Reviewed by: phk MFC after: 7 days
2003-01-28 10:55:38 +00:00
val = (CSR_READ_4(sc, SIS_PHYCTL) >> 16) & 0xFFFF;
if (val == 0xFFFF)
style(9) - space after keywords.
2010-09-01 18:39:35 +00:00
return (0);
Add PCI revision number for 630A and 900B. Enable parity error detection on 900B and 635(A). Re-add the enhanced PHY access register method again for older chipsets, they do not seem to work with all old chips. Reviewed by: phk MFC after: 7 days
2003-01-28 10:55:38 +00:00
style(9) - space after keywords.
2010-09-01 18:39:35 +00:00
return (val);
- Import the common MII bitbang'ing code from NetBSD and convert drivers to take advantage of it instead of duplicating it. This reduces the size of the i386 GENERIC kernel by about 4k. The only potential in-tree user left unconverted is xe(4), which generally should be changed to use miibus(4) instead of implementing PHY handling on its own, as otherwise it makes not much sense to add a dependency on miibus(4)/mii_bitbang(4) to xe(4) just for the MII bitbang'ing code. The common MII bitbang'ing code also is useful in the embedded space for using GPIO pins to implement MII access. - Based on lessons learnt with dc(4) (see r185750), add bus barriers to the MII bitbang read and write functions of the other drivers converted in order to ensure the intended ordering. Given that register access via an index register as well as register bank/window switching is subject to the same problem, also add bus barriers to the respective functions of smc(4), tl(4) and xl(4). - Sprinkle some const. Thanks to the following testers: Andrew Bliznak (nge(4)), nwhitehorn@ (bm(4)), yongari@ (sis(4) and ste(4)) Thanks to Hans-Joerg Sirtl for supplying hardware to test stge(4). Reviewed by: yongari (subset of drivers) Obtained from: NetBSD (partially)
2011-11-01 16:13:59 +00:00
} else
return (mii_bitbang_readreg(dev, &sis_mii_bitbang_ops, phy,
reg));
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static int
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
sis_miibus_writereg(device_t dev, int phy, int reg, int data)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
struct sis_softc *sc;
sc = device_get_softc(dev);
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
if (sc->sis_type == SIS_TYPE_83815) {
if (phy != 0)
style(9) - space after keywords.
2010-09-01 18:39:35 +00:00
return (0);
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
CSR_WRITE_4(sc, NS_BMCR + (reg * 4), data);
style(9) - space after keywords.
2010-09-01 18:39:35 +00:00
return (0);
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
}
Add PCI revision number for 630A and 900B. Enable parity error detection on 900B and 635(A). Re-add the enhanced PHY access register method again for older chipsets, they do not seem to work with all old chips. Reviewed by: phk MFC after: 7 days
2003-01-28 10:55:38 +00:00
/*
* Chipsets < SIS_635 seem not to be able to read/write
* through mdio. Use the enhanced PHY access register
* again for them.
*/
if (sc->sis_type == SIS_TYPE_900 &&
sc->sis_rev < SIS_REV_635) {
int i;
if (phy != 0)
style(9) - space after keywords.
2010-09-01 18:39:35 +00:00
return (0);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Add PCI revision number for 630A and 900B. Enable parity error detection on 900B and 635(A). Re-add the enhanced PHY access register method again for older chipsets, they do not seem to work with all old chips. Reviewed by: phk MFC after: 7 days
2003-01-28 10:55:38 +00:00
CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
(reg << 6) | SIS_PHYOP_WRITE);
SIS_SETBIT(sc, SIS_PHYCTL, SIS_PHYCTL_ACCESS);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Add PCI revision number for 630A and 900B. Enable parity error detection on 900B and 635(A). Re-add the enhanced PHY access register method again for older chipsets, they do not seem to work with all old chips. Reviewed by: phk MFC after: 7 days
2003-01-28 10:55:38 +00:00
for (i = 0; i < SIS_TIMEOUT; i++) {
if (!(CSR_READ_4(sc, SIS_PHYCTL) & SIS_PHYCTL_ACCESS))
break;
}
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Add PCI revision number for 630A and 900B. Enable parity error detection on 900B and 635(A). Re-add the enhanced PHY access register method again for older chipsets, they do not seem to work with all old chips. Reviewed by: phk MFC after: 7 days
2003-01-28 10:55:38 +00:00
if (i == SIS_TIMEOUT)
- Import the common MII bitbang'ing code from NetBSD and convert drivers to take advantage of it instead of duplicating it. This reduces the size of the i386 GENERIC kernel by about 4k. The only potential in-tree user left unconverted is xe(4), which generally should be changed to use miibus(4) instead of implementing PHY handling on its own, as otherwise it makes not much sense to add a dependency on miibus(4)/mii_bitbang(4) to xe(4) just for the MII bitbang'ing code. The common MII bitbang'ing code also is useful in the embedded space for using GPIO pins to implement MII access. - Based on lessons learnt with dc(4) (see r185750), add bus barriers to the MII bitbang read and write functions of the other drivers converted in order to ensure the intended ordering. Given that register access via an index register as well as register bank/window switching is subject to the same problem, also add bus barriers to the respective functions of smc(4), tl(4) and xl(4). - Sprinkle some const. Thanks to the following testers: Andrew Bliznak (nge(4)), nwhitehorn@ (bm(4)), yongari@ (sis(4) and ste(4)) Thanks to Hans-Joerg Sirtl for supplying hardware to test stge(4). Reviewed by: yongari (subset of drivers) Obtained from: NetBSD (partially)
2011-11-01 16:13:59 +00:00
device_printf(sc->sis_dev,
"PHY failed to come ready\n");
} else
mii_bitbang_writereg(dev, &sis_mii_bitbang_ops, phy, reg,
data);
style(9) - space after keywords.
2010-09-01 18:39:35 +00:00
return (0);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static void
Make sis_initl() take a typed argument. Expect caller to lock before calling sis_stop() Various style stuff.
2005-01-05 10:26:12 +00:00
sis_miibus_statchg(device_t dev)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
struct sis_softc *sc;
Overhaul link state change handling. Previously sis(4) blindly configured TX/RX MACs before getting a valid link. After that, when link state change callback is called, it called device initialization again to reconfigure TX/RX MACs depending on resolved link state. This hack created several bad side effects and it required more hacks to not collide with sis_tick callback as well as disabling switching to currently selected media in device initialization. Also it seems sis(4) was used to be a template driver for long time so other drivers which was modeled after sis(4) also should be changed. TX/RX MACs are now reconfigured after getting a valid link. Fix for short cable error is also applied after getting a link because it's only valid when the resolved speed is 100Mbps. While I'm here slightly reorganize interrupt handler such that sis(4) always read SIS_ISR register to see whether the interrupt is ours or not. This change removes another hack and make it possible to nuke sis_stopped variable in softc.
2010-09-01 21:42:19 +00:00
struct mii_data *mii;
struct ifnet *ifp;
uint32_t reg;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
sc = device_get_softc(dev);
Make sis_initl() take a typed argument. Expect caller to lock before calling sis_stop() Various style stuff.
2005-01-05 10:26:12 +00:00
SIS_LOCK_ASSERT(sc);
Overhaul link state change handling. Previously sis(4) blindly configured TX/RX MACs before getting a valid link. After that, when link state change callback is called, it called device initialization again to reconfigure TX/RX MACs depending on resolved link state. This hack created several bad side effects and it required more hacks to not collide with sis_tick callback as well as disabling switching to currently selected media in device initialization. Also it seems sis(4) was used to be a template driver for long time so other drivers which was modeled after sis(4) also should be changed. TX/RX MACs are now reconfigured after getting a valid link. Fix for short cable error is also applied after getting a link because it's only valid when the resolved speed is 100Mbps. While I'm here slightly reorganize interrupt handler such that sis(4) always read SIS_ISR register to see whether the interrupt is ours or not. This change removes another hack and make it possible to nuke sis_stopped variable in softc.
2010-09-01 21:42:19 +00:00
mii = device_get_softc(sc->sis_miibus);
ifp = sc->sis_ifp;
if (mii == NULL || ifp == NULL ||
(ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
return;
Unlike most other controllers, NS DP83815/DP83816 controllers seem to pad with 0xFF when it encounter short frames. According to RFC 1042 the pad bytes should be 0x00. Because manual padding consumes extra CPU cycles, introduce a new tunable which controls the padding behavior. Turning this tunable on will have driver pad manually but it's disabled by default. Users can enable software padding by setting the following tunable to non-zero value. dev.sis.%d.manual_pad="1" PR: kern/35422 (patch not used)
2010-09-02 18:10:11 +00:00
sc->sis_flags &= ~SIS_FLAG_LINK;
Overhaul link state change handling. Previously sis(4) blindly configured TX/RX MACs before getting a valid link. After that, when link state change callback is called, it called device initialization again to reconfigure TX/RX MACs depending on resolved link state. This hack created several bad side effects and it required more hacks to not collide with sis_tick callback as well as disabling switching to currently selected media in device initialization. Also it seems sis(4) was used to be a template driver for long time so other drivers which was modeled after sis(4) also should be changed. TX/RX MACs are now reconfigured after getting a valid link. Fix for short cable error is also applied after getting a link because it's only valid when the resolved speed is 100Mbps. While I'm here slightly reorganize interrupt handler such that sis(4) always read SIS_ISR register to see whether the interrupt is ours or not. This change removes another hack and make it possible to nuke sis_stopped variable in softc.
2010-09-01 21:42:19 +00:00
if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
(IFM_ACTIVE | IFM_AVALID)) {
switch (IFM_SUBTYPE(mii->mii_media_active)) {
case IFM_10_T:
CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_10);
Unlike most other controllers, NS DP83815/DP83816 controllers seem to pad with 0xFF when it encounter short frames. According to RFC 1042 the pad bytes should be 0x00. Because manual padding consumes extra CPU cycles, introduce a new tunable which controls the padding behavior. Turning this tunable on will have driver pad manually but it's disabled by default. Users can enable software padding by setting the following tunable to non-zero value. dev.sis.%d.manual_pad="1" PR: kern/35422 (patch not used)
2010-09-02 18:10:11 +00:00
sc->sis_flags |= SIS_FLAG_LINK;
Overhaul link state change handling. Previously sis(4) blindly configured TX/RX MACs before getting a valid link. After that, when link state change callback is called, it called device initialization again to reconfigure TX/RX MACs depending on resolved link state. This hack created several bad side effects and it required more hacks to not collide with sis_tick callback as well as disabling switching to currently selected media in device initialization. Also it seems sis(4) was used to be a template driver for long time so other drivers which was modeled after sis(4) also should be changed. TX/RX MACs are now reconfigured after getting a valid link. Fix for short cable error is also applied after getting a link because it's only valid when the resolved speed is 100Mbps. While I'm here slightly reorganize interrupt handler such that sis(4) always read SIS_ISR register to see whether the interrupt is ours or not. This change removes another hack and make it possible to nuke sis_stopped variable in softc.
2010-09-01 21:42:19 +00:00
break;
case IFM_100_TX:
CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
Unlike most other controllers, NS DP83815/DP83816 controllers seem to pad with 0xFF when it encounter short frames. According to RFC 1042 the pad bytes should be 0x00. Because manual padding consumes extra CPU cycles, introduce a new tunable which controls the padding behavior. Turning this tunable on will have driver pad manually but it's disabled by default. Users can enable software padding by setting the following tunable to non-zero value. dev.sis.%d.manual_pad="1" PR: kern/35422 (patch not used)
2010-09-02 18:10:11 +00:00
sc->sis_flags |= SIS_FLAG_LINK;
Overhaul link state change handling. Previously sis(4) blindly configured TX/RX MACs before getting a valid link. After that, when link state change callback is called, it called device initialization again to reconfigure TX/RX MACs depending on resolved link state. This hack created several bad side effects and it required more hacks to not collide with sis_tick callback as well as disabling switching to currently selected media in device initialization. Also it seems sis(4) was used to be a template driver for long time so other drivers which was modeled after sis(4) also should be changed. TX/RX MACs are now reconfigured after getting a valid link. Fix for short cable error is also applied after getting a link because it's only valid when the resolved speed is 100Mbps. While I'm here slightly reorganize interrupt handler such that sis(4) always read SIS_ISR register to see whether the interrupt is ours or not. This change removes another hack and make it possible to nuke sis_stopped variable in softc.
2010-09-01 21:42:19 +00:00
break;
default:
break;
}
}
Unlike most other controllers, NS DP83815/DP83816 controllers seem to pad with 0xFF when it encounter short frames. According to RFC 1042 the pad bytes should be 0x00. Because manual padding consumes extra CPU cycles, introduce a new tunable which controls the padding behavior. Turning this tunable on will have driver pad manually but it's disabled by default. Users can enable software padding by setting the following tunable to non-zero value. dev.sis.%d.manual_pad="1" PR: kern/35422 (patch not used)
2010-09-02 18:10:11 +00:00
if ((sc->sis_flags & SIS_FLAG_LINK) == 0) {
Overhaul link state change handling. Previously sis(4) blindly configured TX/RX MACs before getting a valid link. After that, when link state change callback is called, it called device initialization again to reconfigure TX/RX MACs depending on resolved link state. This hack created several bad side effects and it required more hacks to not collide with sis_tick callback as well as disabling switching to currently selected media in device initialization. Also it seems sis(4) was used to be a template driver for long time so other drivers which was modeled after sis(4) also should be changed. TX/RX MACs are now reconfigured after getting a valid link. Fix for short cable error is also applied after getting a link because it's only valid when the resolved speed is 100Mbps. While I'm here slightly reorganize interrupt handler such that sis(4) always read SIS_ISR register to see whether the interrupt is ours or not. This change removes another hack and make it possible to nuke sis_stopped variable in softc.
2010-09-01 21:42:19 +00:00
/*
* Stopping MACs seem to reset SIS_TX_LISTPTR and
* SIS_RX_LISTPTR which in turn requires resetting
* TX/RX buffers. So just don't do anything for
* lost link.
*/
return;
}
/* Set full/half duplex mode. */
if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
SIS_SETBIT(sc, SIS_TX_CFG,
(SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR));
SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
} else {
SIS_CLRBIT(sc, SIS_TX_CFG,
(SIS_TXCFG_IGN_HBEAT | SIS_TXCFG_IGN_CARR));
SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
}
r119712 introduced SIS_TYPE_83816 but it was not actually set in driver such that checking against the type was always false. To detect NS DP83816, driver should have checked silicon revision register for NS controllers. While here, remove SIS_TYPE_83816 to not make the similar mistake again. Reported by: Brad Smith ( brad@openbsd )
2013-03-18 04:46:17 +00:00
if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) {
Overhaul link state change handling. Previously sis(4) blindly configured TX/RX MACs before getting a valid link. After that, when link state change callback is called, it called device initialization again to reconfigure TX/RX MACs depending on resolved link state. This hack created several bad side effects and it required more hacks to not collide with sis_tick callback as well as disabling switching to currently selected media in device initialization. Also it seems sis(4) was used to be a template driver for long time so other drivers which was modeled after sis(4) also should be changed. TX/RX MACs are now reconfigured after getting a valid link. Fix for short cable error is also applied after getting a link because it's only valid when the resolved speed is 100Mbps. While I'm here slightly reorganize interrupt handler such that sis(4) always read SIS_ISR register to see whether the interrupt is ours or not. This change removes another hack and make it possible to nuke sis_stopped variable in softc.
2010-09-01 21:42:19 +00:00
/*
* MPII03.D: Half Duplex Excessive Collisions.
* Also page 49 in 83816 manual
*/
SIS_SETBIT(sc, SIS_TX_CFG, SIS_TXCFG_MPII03D);
}
if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A &&
IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
/*
* Short Cable Receive Errors (MP21.E)
*/
CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff;
CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000);
DELAY(100);
reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff;
if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) {
device_printf(sc->sis_dev,
"Applying short cable fix (reg=%x)\n", reg);
CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8);
SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20);
}
CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
}
/* Enable TX/RX MACs. */
SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE);
SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE | SIS_CSR_RX_ENABLE);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
static uint32_t
sis_mchash(struct sis_softc *sc, const uint8_t *addr)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
Replace handrolled CRC calculation with ether_crc32_[lb]e().
2004-06-09 14:34:04 +00:00
uint32_t crc;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
/* Compute CRC for the address value. */
Replace handrolled CRC calculation with ether_crc32_[lb]e().
2004-06-09 14:34:04 +00:00
crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
/*
* return the filter bit position
*
* The NatSemi chip has a 512-bit filter, which is
* different than the SiS, so we special-case it.
*/
if (sc->sis_type == SIS_TYPE_83815)
Sis no longer implements the enhanced phy control register, and phy has to be directly accessed via mdio. Patch converted to CURRENT from STABLE. Submitted by: luoqi Reviewed by: luoqi (again) MFC after: 2 weeks
2003-01-10 08:14:07 +00:00
return (crc >> 23);
Add PCI revision number for 630A and 900B. Enable parity error detection on 900B and 635(A). Re-add the enhanced PHY access register method again for older chipsets, they do not seem to work with all old chips. Reviewed by: phk MFC after: 7 days
2003-01-28 10:55:38 +00:00
else if (sc->sis_rev >= SIS_REV_635 ||
sc->sis_rev == SIS_REV_900B)
Sis no longer implements the enhanced phy control register, and phy has to be directly accessed via mdio. Patch converted to CURRENT from STABLE. Submitted by: luoqi Reviewed by: luoqi (again) MFC after: 2 weeks
2003-01-10 08:14:07 +00:00
return (crc >> 24);
Add PCI revision number for 630A and 900B. Enable parity error detection on 900B and 635(A). Re-add the enhanced PHY access register method again for older chipsets, they do not seem to work with all old chips. Reviewed by: phk MFC after: 7 days
2003-01-28 10:55:38 +00:00
else
return (crc >> 25);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static void
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
sis_rxfilter(struct sis_softc *sc)
{
SIS_LOCK_ASSERT(sc);
if (sc->sis_type == SIS_TYPE_83815)
sis_rxfilter_ns(sc);
else
sis_rxfilter_sis(sc);
}
static void
sis_rxfilter_ns(struct sis_softc *sc)
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
{
struct ifnet *ifp;
struct ifmultiaddr *ifma;
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
uint32_t h, i, filter;
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
int bit, index;
Stop embedding struct ifnet at the top of driver softcs. Instead the struct ifnet or the layer 2 common structure it was embedded in have been replaced with a struct ifnet pointer to be filled by a call to the new function, if_alloc(). The layer 2 common structure is also allocated via if_alloc() based on the interface type. It is hung off the new struct ifnet member, if_l2com. This change removes the size of these structures from the kernel ABI and will allow us to better manage them as interfaces come and go. Other changes of note: - Struct arpcom is no longer referenced in normal interface code. Instead the Ethernet address is accessed via the IFP2ENADDR() macro. To enforce this ac_enaddr has been renamed to _ac_enaddr. - The second argument to ether_ifattach is now always the mac address from driver private storage rather than sometimes being ac_enaddr. Reviewed by: sobomax, sam
2005-06-10 16:49:24 +00:00
ifp = sc->sis_ifp;
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
filter = CSR_READ_4(sc, SIS_RXFILT_CTL);
if (filter & SIS_RXFILTCTL_ENABLE) {
/*
* Filter should be disabled to program other bits.
*/
CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE);
CSR_READ_4(sc, SIS_RXFILT_CTL);
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
}
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
filter &= ~(NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT |
NS_RXFILTCTL_MCHASH | SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD |
SIS_RXFILTCTL_ALLMULTI);
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
if (ifp->if_flags & IFF_BROADCAST)
filter |= SIS_RXFILTCTL_BROAD;
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
/*
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
* For the NatSemi chip, we have to explicitly enable the
* reception of ARP frames, as well as turn on the 'perfect
* match' filter where we store the station address, otherwise
* we won't receive unicasts meant for this host.
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
*/
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
filter |= NS_RXFILTCTL_ARP | NS_RXFILTCTL_PERFECT;
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
filter |= SIS_RXFILTCTL_ALLMULTI;
if (ifp->if_flags & IFF_PROMISC)
filter |= SIS_RXFILTCTL_ALLPHYS;
} else {
/*
* We have to explicitly enable the multicast hash table
* on the NatSemi chip if we want to use it, which we do.
*/
filter |= NS_RXFILTCTL_MCHASH;
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
/* first, zot all the existing hash bits */
for (i = 0; i < 32; i++) {
CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO +
(i * 2));
CSR_WRITE_4(sc, SIS_RXFILT_DATA, 0);
}
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
if_maddr_rlock(ifp);
TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
if (ifma->ifma_addr->sa_family != AF_LINK)
continue;
h = sis_mchash(sc,
LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
index = h >> 3;
bit = h & 0x1F;
CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_FMEM_LO +
index);
if (bit > 0xF)
bit -= 0x10;
SIS_SETBIT(sc, SIS_RXFILT_DATA, (1 << bit));
}
if_maddr_runlock(ifp);
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
}
Enable receive filter in sis_rxfilter(). While I'm here add a check for driver running state for multicast filter handling. Suggested by: brad@OpenBSD.org
2015-01-12 07:37:06 +00:00
/* Turn the receive filter on */
CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter | SIS_RXFILTCTL_ENABLE);
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
CSR_READ_4(sc, SIS_RXFILT_CTL);
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
}
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static void
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
sis_rxfilter_sis(struct sis_softc *sc)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
struct ifnet *ifp;
struct ifmultiaddr *ifma;
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
uint32_t filter, h, i, n;
s/u_intXX_t/uintXX_t/g
2010-09-01 19:53:15 +00:00
uint16_t hashes[16];
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Stop embedding struct ifnet at the top of driver softcs. Instead the struct ifnet or the layer 2 common structure it was embedded in have been replaced with a struct ifnet pointer to be filled by a call to the new function, if_alloc(). The layer 2 common structure is also allocated via if_alloc() based on the interface type. It is hung off the new struct ifnet member, if_l2com. This change removes the size of these structures from the kernel ABI and will allow us to better manage them as interfaces come and go. Other changes of note: - Struct arpcom is no longer referenced in normal interface code. Instead the Ethernet address is accessed via the IFP2ENADDR() macro. To enforce this ac_enaddr has been renamed to _ac_enaddr. - The second argument to ether_ifattach is now always the mac address from driver private storage rather than sometimes being ac_enaddr. Reviewed by: sobomax, sam
2005-06-10 16:49:24 +00:00
ifp = sc->sis_ifp;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Sis no longer implements the enhanced phy control register, and phy has to be directly accessed via mdio. Patch converted to CURRENT from STABLE. Submitted by: luoqi Reviewed by: luoqi (again) MFC after: 2 weeks
2003-01-10 08:14:07 +00:00
/* hash table size */
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
if (sc->sis_rev >= SIS_REV_635 || sc->sis_rev == SIS_REV_900B)
Add PCI revision number for 630A and 900B. Enable parity error detection on 900B and 635(A). Re-add the enhanced PHY access register method again for older chipsets, they do not seem to work with all old chips. Reviewed by: phk MFC after: 7 days
2003-01-28 10:55:38 +00:00
n = 16;
else
n = 8;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
filter = CSR_READ_4(sc, SIS_RXFILT_CTL);
if (filter & SIS_RXFILTCTL_ENABLE) {
Fix a bug introdiced in r217548. According to NS DP83815 data sheet, RX filter should be disabled before programming. Previously it was clearing wrong bits so RX filter was not disabled in RX filter configuration. Reported by: brad@OpenBSD.org
2014-12-16 06:13:30 +00:00
CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter & ~SIS_RXFILTCTL_ENABLE);
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
CSR_READ_4(sc, SIS_RXFILT_CTL);
}
filter &= ~(SIS_RXFILTCTL_ALLPHYS | SIS_RXFILTCTL_BROAD |
SIS_RXFILTCTL_ALLMULTI);
Sis no longer implements the enhanced phy control register, and phy has to be directly accessed via mdio. Patch converted to CURRENT from STABLE. Submitted by: luoqi Reviewed by: luoqi (again) MFC after: 2 weeks
2003-01-10 08:14:07 +00:00
if (ifp->if_flags & IFF_BROADCAST)
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
filter |= SIS_RXFILTCTL_BROAD;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
filter |= SIS_RXFILTCTL_ALLMULTI;
Sis no longer implements the enhanced phy control register, and phy has to be directly accessed via mdio. Patch converted to CURRENT from STABLE. Submitted by: luoqi Reviewed by: luoqi (again) MFC after: 2 weeks
2003-01-10 08:14:07 +00:00
if (ifp->if_flags & IFF_PROMISC)
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
filter |= SIS_RXFILTCTL_ALLPHYS;
Sis no longer implements the enhanced phy control register, and phy has to be directly accessed via mdio. Patch converted to CURRENT from STABLE. Submitted by: luoqi Reviewed by: luoqi (again) MFC after: 2 weeks
2003-01-10 08:14:07 +00:00
for (i = 0; i < n; i++)
hashes[i] = ~0;
} else {
for (i = 0; i < n; i++)
hashes[i] = 0;
i = 0;
Use if_maddr_rlock()/if_maddr_runlock() rather than IF_ADDR_LOCK()/ IF_ADDR_UNLOCK() across network device drivers when accessing the per-interface multicast address list, if_multiaddrs. This will allow us to change the locking strategy without affecting our driver programming interface or binary interface. For two wireless drivers, remove unnecessary locking, since they don't actually access the multicast address list. Approved by: re (kib) MFC after: 6 weeks
2009-06-26 11:45:06 +00:00
if_maddr_rlock(ifp);
Sis no longer implements the enhanced phy control register, and phy has to be directly accessed via mdio. Patch converted to CURRENT from STABLE. Submitted by: luoqi Reviewed by: luoqi (again) MFC after: 2 weeks
2003-01-10 08:14:07 +00:00
TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
if (ifma->ifma_addr->sa_family != AF_LINK)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
continue;
Try to create some sort of consistency in how the routings to find the multicast hash are written. There are still two distinct algorithms used, and there actually isn't any reason each driver should have its own copy of this function as they could all share one copy of it (if it grew an additional argument).
2003-11-13 20:55:53 +00:00
h = sis_mchash(sc,
Sis no longer implements the enhanced phy control register, and phy has to be directly accessed via mdio. Patch converted to CURRENT from STABLE. Submitted by: luoqi Reviewed by: luoqi (again) MFC after: 2 weeks
2003-01-10 08:14:07 +00:00
LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
hashes[h >> 4] |= 1 << (h & 0xf);
i++;
}
Use if_maddr_rlock()/if_maddr_runlock() rather than IF_ADDR_LOCK()/ IF_ADDR_UNLOCK() across network device drivers when accessing the per-interface multicast address list, if_multiaddrs. This will allow us to change the locking strategy without affecting our driver programming interface or binary interface. For two wireless drivers, remove unnecessary locking, since they don't actually access the multicast address list. Approved by: re (kib) MFC after: 6 weeks
2009-06-26 11:45:06 +00:00
if_maddr_runlock(ifp);
Sis no longer implements the enhanced phy control register, and phy has to be directly accessed via mdio. Patch converted to CURRENT from STABLE. Submitted by: luoqi Reviewed by: luoqi (again) MFC after: 2 weeks
2003-01-10 08:14:07 +00:00
if (i > n) {
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
filter |= SIS_RXFILTCTL_ALLMULTI;
Sis no longer implements the enhanced phy control register, and phy has to be directly accessed via mdio. Patch converted to CURRENT from STABLE. Submitted by: luoqi Reviewed by: luoqi (again) MFC after: 2 weeks
2003-01-10 08:14:07 +00:00
for (i = 0; i < n; i++)
hashes[i] = ~0;
}
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
Sis no longer implements the enhanced phy control register, and phy has to be directly accessed via mdio. Patch converted to CURRENT from STABLE. Submitted by: luoqi Reviewed by: luoqi (again) MFC after: 2 weeks
2003-01-10 08:14:07 +00:00
for (i = 0; i < n; i++) {
CSR_WRITE_4(sc, SIS_RXFILT_CTL, (4 + i) << 16);
CSR_WRITE_4(sc, SIS_RXFILT_DATA, hashes[i]);
}
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Enable receive filter in sis_rxfilter(). While I'm here add a check for driver running state for multicast filter handling. Suggested by: brad@OpenBSD.org
2015-01-12 07:37:06 +00:00
/* Turn the receive filter on */
CSR_WRITE_4(sc, SIS_RXFILT_CTL, filter | SIS_RXFILTCTL_ENABLE);
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
CSR_READ_4(sc, SIS_RXFILT_CTL);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static void
Make sis_initl() take a typed argument. Expect caller to lock before calling sis_stop() Various style stuff.
2005-01-05 10:26:12 +00:00
sis_reset(struct sis_softc *sc)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
Don't declare variables "register", the compiler ought to know what to do.
2005-01-05 09:02:05 +00:00
int i;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RESET);
for (i = 0; i < SIS_TIMEOUT; i++) {
if (!(CSR_READ_4(sc, SIS_CSR) & SIS_CSR_RESET))
break;
}
if (i == SIS_TIMEOUT)
Consistently use if_printf() only in interface methods: if_start, if_ioctl, if_watchdog, etc, or in functions that are used by these methods only. In all other cases use device_printf(). This also fixes several panics, when if_printf() is called before softc->ifp was initialized. Submitted by: Alex Lyashkov <umka sevcity.net>
2006-09-15 10:40:54 +00:00
device_printf(sc->sis_dev, "reset never completed\n");
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
/* Wait a little while for the chip to get its brains in order. */
DELAY(1000);
Big round of minor updates: - Use pci_get_powerstate()/pci_set_powerstate() in all the other drivers that need them so we don't have to fiddle with the PCI power management registers directly. - Use pci_enable_busmaster()/pci_enable_io() to turn on busmastering and PIO/memory mapped accesses. - Add support to the RealTek driver for the D-Link DFE-530TX+ which has a RealTek 8139 with its own PCI ID. (Submitted by Jason Wright) - Have the SiS 900/National DP83815 driver be sure to disable PME mode in sis_reset(). This apparently fixes a problem on some motherboards where the DP83815 chip fails to receive packets. (Submitted by Chuck McCrobie <mccrobie@cablespeed.com>)
2001-02-21 20:54:22 +00:00
/*
* If this is a NetSemi chip, make sure to clear
* PME mode.
*/
if (sc->sis_type == SIS_TYPE_83815) {
CSR_WRITE_4(sc, NS_CLKRUN, NS_CLKRUN_PMESTS);
CSR_WRITE_4(sc, NS_CLKRUN, 0);
Initial WOL support. NS DP8315 was tested but SiS900/SiS7016 was not tested. While I'm here, clean up SIOCSIFCAP handler.
2010-09-03 00:34:45 +00:00
} else {
/* Disable WOL functions. */
CSR_WRITE_4(sc, SIS_PWRMAN_CTL, 0);
Big round of minor updates: - Use pci_get_powerstate()/pci_set_powerstate() in all the other drivers that need them so we don't have to fiddle with the PCI power management registers directly. - Use pci_enable_busmaster()/pci_enable_io() to turn on busmastering and PIO/memory mapped accesses. - Add support to the RealTek driver for the D-Link DFE-530TX+ which has a RealTek 8139 with its own PCI ID. (Submitted by Jason Wright) - Have the SiS 900/National DP83815 driver be sure to disable PME mode in sis_reset(). This apparently fixes a problem on some motherboards where the DP83815 chip fails to receive packets. (Submitted by Chuck McCrobie <mccrobie@cablespeed.com>)
2001-02-21 20:54:22 +00:00
}
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
/*
* Probe for an SiS chip. Check the PCI vendor and device
* IDs against our list and return a device name if we find a match.
*/
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static int
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
sis_probe(device_t dev)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
- Import the common MII bitbang'ing code from NetBSD and convert drivers to take advantage of it instead of duplicating it. This reduces the size of the i386 GENERIC kernel by about 4k. The only potential in-tree user left unconverted is xe(4), which generally should be changed to use miibus(4) instead of implementing PHY handling on its own, as otherwise it makes not much sense to add a dependency on miibus(4)/mii_bitbang(4) to xe(4) just for the MII bitbang'ing code. The common MII bitbang'ing code also is useful in the embedded space for using GPIO pins to implement MII access. - Based on lessons learnt with dc(4) (see r185750), add bus barriers to the MII bitbang read and write functions of the other drivers converted in order to ensure the intended ordering. Given that register access via an index register as well as register bank/window switching is subject to the same problem, also add bus barriers to the respective functions of smc(4), tl(4) and xl(4). - Sprinkle some const. Thanks to the following testers: Andrew Bliznak (nge(4)), nwhitehorn@ (bm(4)), yongari@ (sis(4) and ste(4)) Thanks to Hans-Joerg Sirtl for supplying hardware to test stge(4). Reviewed by: yongari (subset of drivers) Obtained from: NetBSD (partially)
2011-11-01 16:13:59 +00:00
const struct sis_type *t;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
t = sis_devs;
style(9) - space after keywords.
2010-09-01 18:39:35 +00:00
while (t->sis_name != NULL) {
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
if ((pci_get_vendor(dev) == t->sis_vid) &&
(pci_get_device(dev) == t->sis_did)) {
device_set_desc(dev, t->sis_name);
Return BUS_PROBE_DEFAULT instead of 0.
2005-02-24 21:32:56 +00:00
return (BUS_PROBE_DEFAULT);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
t++;
}
style(9) - space after keywords.
2010-09-01 18:39:35 +00:00
return (ENXIO);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
/*
* Attach the interface. Allocate softc structures, do ifmedia
* setup and ethernet/BPF attach.
*/
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static int
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
sis_attach(device_t dev)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
u_char eaddr[ETHER_ADDR_LEN];
struct sis_softc *sc;
struct ifnet *ifp;
Initial WOL support. NS DP8315 was tested but SiS900/SiS7016 was not tested. While I'm here, clean up SIOCSIFCAP handler.
2010-09-03 00:34:45 +00:00
int error = 0, pmc, waittime = 0;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Make newer integrated SiS900 cards working. Allow to read EEPROM from LAN. It is shared between a 1394 controller and the NIC and each time we access it, we need to set SIS_EECMD_REQ. Idea from: linux driver source Reviewed by: luoqi Obtained from: linux driver source (idea)
2003-01-10 08:16:03 +00:00
waittime = 0;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
sc = device_get_softc(dev);
Consistently use if_printf() only in interface methods: if_start, if_ioctl, if_watchdog, etc, or in functions that are used by these methods only. In all other cases use device_printf(). This also fixes several panics, when if_printf() is called before softc->ifp was initialized. Submitted by: Alex Lyashkov <umka sevcity.net>
2006-09-15 10:40:54 +00:00
sc->sis_dev = dev;
Examine and record the Silicon Revision Register on NS parts. We can't update the device description in attach (why not ?), so we device_print() what we find. Conditionalize the short cable fix on this being older than rev 16A. Call device_printf() when we apply short cable fix. Include interrupt hold-off setting for rev 16+ under "#ifdef notyet" The device_printf()'s will go under bootverbose once the various issues have settled a bit.
2003-09-03 07:40:04 +00:00
Change callers of mtx_init() to pass in an appropriate lock type name. In most cases NULL is passed, but in some cases such as network driver locks (which use the MTX_NETWORK_LOCK macro) and UMA zone locks, a name is used. Tested on: i386, alpha, sparc64
2002-04-04 21:03:38 +00:00
mtx_init(&sc->sis_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
We no longer recurse the mutex.
2005-01-07 00:02:11 +00:00
MTX_DEF);
Small fixes to sis(4): - Remove sis_unit and use device_printf() and if_printf() instead. - Use callout_init_mtx() for the callout. - Remove spls. - Fix locking for ifmedia to happen in the ifmedia handlers rather than in sis_ioctl(). - Log an error message if we fail to allocate any resources. Perform cleanup if we fail to allocate any resources so that we don't leave a mutex hanging around. Tested by: Jason Tsai jason dot tsai at newcyberian dot com (1-4) MFC after: 3 days
2005-09-26 18:42:27 +00:00
callout_init_mtx(&sc->sis_stat_ch, &sc->sis_mtx, 0);
Initialize/grab the mutex earlier in the attach phase, so that bailing out to the fail: label where we release/destroy the mutex will work without exploding.
2000-12-04 22:46:50 +00:00
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
if (pci_get_device(dev) == SIS_DEVICEID_900)
sc->sis_type = SIS_TYPE_900;
if (pci_get_device(dev) == SIS_DEVICEID_7016)
sc->sis_type = SIS_TYPE_7016;
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
if (pci_get_vendor(dev) == NS_VENDORID)
sc->sis_type = SIS_TYPE_83815;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Add support for newer integrated SiS 900 controllers on the 635 and 735 motherboard chipsets. We need to force the chip to reload its MAC address into the receive filter, and enable software access mode for the PHY. PR: kern/33294
2002-01-12 21:12:17 +00:00
sc->sis_rev = pci_read_config(dev, PCIR_REVID, 1);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
/*
* Map control/status registers.
*/
Big round of minor updates: - Use pci_get_powerstate()/pci_set_powerstate() in all the other drivers that need them so we don't have to fiddle with the PCI power management registers directly. - Use pci_enable_busmaster()/pci_enable_io() to turn on busmastering and PIO/memory mapped accesses. - Add support to the RealTek driver for the D-Link DFE-530TX+ which has a RealTek 8139 with its own PCI ID. (Submitted by Jason Wright) - Have the SiS 900/National DP83815 driver be sure to disable PME mode in sis_reset(). This apparently fixes a problem on some motherboards where the DP83815 chip fails to receive packets. (Submitted by Chuck McCrobie <mccrobie@cablespeed.com>)
2001-02-21 20:54:22 +00:00
pci_enable_busmaster(dev);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Use the new bus_space/resource convenience functions.
2005-09-24 20:46:02 +00:00
error = bus_alloc_resources(dev, sis_res_spec, sc->sis_res);
Small fixes to sis(4): - Remove sis_unit and use device_printf() and if_printf() instead. - Use callout_init_mtx() for the callout. - Remove spls. - Fix locking for ifmedia to happen in the ifmedia handlers rather than in sis_ioctl(). - Log an error message if we fail to allocate any resources. Perform cleanup if we fail to allocate any resources so that we don't leave a mutex hanging around. Tested by: Jason Tsai jason dot tsai at newcyberian dot com (1-4) MFC after: 3 days
2005-09-26 18:42:27 +00:00
if (error) {
device_printf(dev, "couldn't allocate resources\n");
goto fail;
}
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
/* Reset the adapter. */
sis_reset(sc);
Add PCI revision number for 630A and 900B. Enable parity error detection on 900B and 635(A). Re-add the enhanced PHY access register method again for older chipsets, they do not seem to work with all old chips. Reviewed by: phk MFC after: 7 days
2003-01-28 10:55:38 +00:00
if (sc->sis_type == SIS_TYPE_900 &&
Remove leading and trailing white spaces. No functional changes.
2010-09-01 18:28:08 +00:00
(sc->sis_rev == SIS_REV_635 ||
sc->sis_rev == SIS_REV_900B)) {
Add PCI revision number for 630A and 900B. Enable parity error detection on 900B and 635(A). Re-add the enhanced PHY access register method again for older chipsets, they do not seem to work with all old chips. Reviewed by: phk MFC after: 7 days
2003-01-28 10:55:38 +00:00
SIO_SET(SIS_CFG_RND_CNT);
SIO_SET(SIS_CFG_PERR_DETECT);
}
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
/*
* Get station address from the EEPROM.
*/
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
switch (pci_get_vendor(dev)) {
case NS_VENDORID:
Examine and record the Silicon Revision Register on NS parts. We can't update the device description in attach (why not ?), so we device_print() what we find. Conditionalize the short cable fix on this being older than rev 16A. Call device_printf() when we apply short cable fix. Include interrupt hold-off setting for rev 16+ under "#ifdef notyet" The device_printf()'s will go under bootverbose once the various issues have settled a bit.
2003-09-03 07:40:04 +00:00
sc->sis_srr = CSR_READ_4(sc, NS_SRR);
/* We can't update the device description, so spew */
if (sc->sis_srr == NS_SRR_15C)
device_printf(dev, "Silicon Revision: DP83815C\n");
else if (sc->sis_srr == NS_SRR_15D)
device_printf(dev, "Silicon Revision: DP83815D\n");
else if (sc->sis_srr == NS_SRR_16A)
device_printf(dev, "Silicon Revision: DP83816A\n");
else
device_printf(dev, "Silicon Revision %x\n", sc->sis_srr);
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
/*
* Reading the MAC address out of the EEPROM on
* the NatSemi chip takes a bit more work than
* you'd expect. The address spans 4 16-bit words,
* with the first word containing only a single bit.
* You have to shift everything over one bit to
* get it aligned properly. Also, the bits are
* stored backwards (the LSB is really the MSB,
* and so on) so you have to reverse them in order
* to get the MAC address into the form we want.
* Why? Who the hell knows.
*/
{
s/u_intXX_t/uintXX_t/g
2010-09-01 19:53:15 +00:00
uint16_t tmp[4];
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
sis_read_eeprom(sc, (caddr_t)&tmp,
NS_EE_NODEADDR, 4, 0);
/* Shift everything over one bit. */
tmp[3] = tmp[3] >> 1;
Fix a minor bug in the MAC address unscrambling code. (Some shift rights should have been shift lefts.)
2000-07-06 19:21:07 +00:00
tmp[3] |= tmp[2] << 15;
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
tmp[2] = tmp[2] >> 1;
Fix a minor bug in the MAC address unscrambling code. (Some shift rights should have been shift lefts.)
2000-07-06 19:21:07 +00:00
tmp[2] |= tmp[1] << 15;
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
tmp[1] = tmp[1] >> 1;
Fix a minor bug in the MAC address unscrambling code. (Some shift rights should have been shift lefts.)
2000-07-06 19:21:07 +00:00
tmp[1] |= tmp[0] << 15;
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
/* Now reverse all the bits. */
tmp[3] = sis_reverse(tmp[3]);
tmp[2] = sis_reverse(tmp[2]);
tmp[1] = sis_reverse(tmp[1]);
Fix the last endianness issue on handling station address which prevented driver from working on big-endian machines. Also rewrite station address programming to make it work on strict-alignment architectures. With this change, sis(4) now works on sparc64 and performance number looks good even though sis(4) have to apply fixup code to align received frames on 2 bytes boundary on sparc64.
2010-09-02 17:51:41 +00:00
eaddr[0] = (tmp[1] >> 0) & 0xFF;
eaddr[1] = (tmp[1] >> 8) & 0xFF;
eaddr[2] = (tmp[2] >> 0) & 0xFF;
eaddr[3] = (tmp[2] >> 8) & 0xFF;
eaddr[4] = (tmp[3] >> 0) & 0xFF;
eaddr[5] = (tmp[3] >> 8) & 0xFF;
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
}
break;
case SIS_VENDORID:
default:
Bring rev 1.31 to the AMD64 platform. This adds support for the SiS intergrated NIC on some Athlon64 motherboards. The MAC address is stored in the APC CMOS RAM and this fixes the sis driver ending up with a 00:00:00:00:00:00 MAC address. Submitted by: Stasys Smailys <ssmailys@komvista.lt>
2005-03-28 18:06:44 +00:00
#if defined(__i386__) || defined(__amd64__)
Apply patch to add support for the intergrated ethernet in the SiS630E chipset. The MAC address is stored in the APC CMOS RAM and we have to commit trememdous evil in order to read it. The code to do this is only activated on the i386 platform. Thanks to Cameron Grant for providing access to a test box for me to tinker with. This will fix the problem where the sis driver ends up with a station address of 00:00:00:00:00:00 on boards that use the 630E chipset.
2001-02-09 00:45:29 +00:00
/*
* If this is a SiS 630E chipset with an embedded
* SiS 900 controller, we have to read the MAC address
* from the APC CMOS RAM. Our method for doing this
* is very ugly since we have to reach out and grab
* ahold of hardware for which we cannot properly
* allocate resources. This code is only compiled on
* the i386 architecture since the SiS 630E chipset
* is for x86 motherboards only. Note that there are
* a lot of magic numbers in this hack. These are
* taken from SiS's Linux driver. I'd like to replace
* them with proper symbolic definitions, but that
* requires some datasheets that I don't have access
* to at the moment.
*/
Add support for newer integrated SiS 900 controllers on the 635 and 735 motherboard chipsets. We need to force the chip to reload its MAC address into the receive filter, and enable software access mode for the PHY. PR: kern/33294
2002-01-12 21:12:17 +00:00
if (sc->sis_rev == SIS_REV_630S ||
sc->sis_rev == SIS_REV_630E ||
Fix support for 630ET support. We don't need the Linux part to set the mii access mode. Fix the device ID and make it read the mac via sis_read_mac. Reviewed by: imp MFC after: 1 week
2002-02-06 22:06:47 +00:00
sc->sis_rev == SIS_REV_630EA1)
Apply patch to add support for the intergrated ethernet in the SiS630E chipset. The MAC address is stored in the APC CMOS RAM and we have to commit trememdous evil in order to read it. The code to do this is only activated on the i386 platform. Thanks to Cameron Grant for providing access to a test box for me to tinker with. This will fix the problem where the sis driver ends up with a station address of 00:00:00:00:00:00 on boards that use the 630E chipset.
2001-02-09 00:45:29 +00:00
sis_read_cmos(sc, dev, (caddr_t)&eaddr, 0x9, 6);
Add support for newer integrated SiS 900 controllers on the 635 and 735 motherboard chipsets. We need to force the chip to reload its MAC address into the receive filter, and enable software access mode for the PHY. PR: kern/33294
2002-01-12 21:12:17 +00:00
Fix support for 630ET support. We don't need the Linux part to set the mii access mode. Fix the device ID and make it read the mac via sis_read_mac. Reviewed by: imp MFC after: 1 week
2002-02-06 22:06:47 +00:00
else if (sc->sis_rev == SIS_REV_635 ||
sc->sis_rev == SIS_REV_630ET)
Add support for newer integrated SiS 900 controllers on the 635 and 735 motherboard chipsets. We need to force the chip to reload its MAC address into the receive filter, and enable software access mode for the PHY. PR: kern/33294
2002-01-12 21:12:17 +00:00
sis_read_mac(sc, dev, (caddr_t)&eaddr);
Make newer integrated SiS900 cards working. Allow to read EEPROM from LAN. It is shared between a 1394 controller and the NIC and each time we access it, we need to set SIS_EECMD_REQ. Idea from: linux driver source Reviewed by: luoqi Obtained from: linux driver source (idea)
2003-01-10 08:16:03 +00:00
else if (sc->sis_rev == SIS_REV_96x) {
/* Allow to read EEPROM from LAN. It is shared
* between a 1394 controller and the NIC and each
* time we access it, we need to set SIS_EECMD_REQ.
*/
SIO_SET(SIS_EECMD_REQ);
for (waittime = 0; waittime < SIS_TIMEOUT;
waittime++) {
/* Force EEPROM to idle state. */
sis_eeprom_idle(sc);
if (CSR_READ_4(sc, SIS_EECTL) & SIS_EECMD_GNT) {
sis_read_eeprom(sc, (caddr_t)&eaddr,
SIS_EE_NODEADDR, 3, 0);
break;
}
DELAY(1);
}
/*
* Set SIS_EECTL_CLK to high, so a other master
* can operate on the i2c bus.
*/
SIO_SET(SIS_EECTL_CLK);
/* Refuse EEPROM access by LAN */
SIO_SET(SIS_EECMD_DONE);
} else
Apply patch to add support for the intergrated ethernet in the SiS630E chipset. The MAC address is stored in the APC CMOS RAM and we have to commit trememdous evil in order to read it. The code to do this is only activated on the i386 platform. Thanks to Cameron Grant for providing access to a test box for me to tinker with. This will fix the problem where the sis driver ends up with a station address of 00:00:00:00:00:00 on boards that use the 630E chipset.
2001-02-09 00:45:29 +00:00
#endif
sis_read_eeprom(sc, (caddr_t)&eaddr,
SIS_EE_NODEADDR, 3, 0);
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
break;
}
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Unlike most other controllers, NS DP83815/DP83816 controllers seem to pad with 0xFF when it encounter short frames. According to RFC 1042 the pad bytes should be 0x00. Because manual padding consumes extra CPU cycles, introduce a new tunable which controls the padding behavior. Turning this tunable on will have driver pad manually but it's disabled by default. Users can enable software padding by setting the following tunable to non-zero value. dev.sis.%d.manual_pad="1" PR: kern/35422 (patch not used)
2010-09-02 18:10:11 +00:00
sis_add_sysctls(sc);
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
/* Allocate DMA'able memory. */
if ((error = sis_dma_alloc(sc)) != 0)
Clean up locking and resource management for pci/if_* - Remove locking of the softc in the attach method, instead depending on bus_setup_intr being at the end of attach (delaying interrupt enable until after ether_ifattach is called) - Call *_detach directly in the error case of attach, depending on checking in detach to only free resources that were allocated. This puts all resource freeing in one place, avoiding thinkos that lead to memory leaks. - Add bus_child_present check to calls to *_stop in the detach method to be sure hw is present before touching its registers. - Remove bzero softc calls since device_t should do this for us. - dc: move interrupt allocation back where it was before. It was unnecessary to move it. This reverts part of 1.88 - rl: move irq allocation before ether_ifattach. Problems might have been caused by allocating the irq after enabling interrupts on the card. - rl: call rl_stop before ether_ifdetach - sf: call sf_stop before ether_ifdetach - sis: add missed free of sis_tag - sis: check errors from tag creation - sis: move dmamem_alloc and dmamap_load to happen at same time as tag creation - sk: remove duplicate initialization of sk_dev - ste: add missed bus_generic_detach - ti: call ti_stop before ether_ifdetach - ti: add missed error setting in ti_rdata alloc failure - vr: add missed error setting in I/O, memory mapping cases - xl: add missed error setting in I/O, memory mapping cases - xl: remove multi-level goto on attach failure - xl: move dmamem_alloc and dmamap_load to happen at same time as tag creation - Calls to free(9) are unconditional because it is valid to call free with a null pointer. Reviewed by: imp, mdodd
2003-03-31 17:29:43 +00:00
goto fail;
Convert the if_sis and if_rl drivers to use the bus_dma API instead of calling vtophys() and contigmalloc()/contigfree() directly. Hopefully, I have shaken out all of the problems with busdma on the alpha now. (Everything seems to work as expected.) Also, change the max RX DMA limit to 1024 bytes instead of "unlimited," as the latter seems not to work correctly on the alpha that I tested. (At 100Mbps, all attempts to receive frames yield RX errors.)
2001-08-15 17:38:43 +00:00
Stop embedding struct ifnet at the top of driver softcs. Instead the struct ifnet or the layer 2 common structure it was embedded in have been replaced with a struct ifnet pointer to be filled by a call to the new function, if_alloc(). The layer 2 common structure is also allocated via if_alloc() based on the interface type. It is hung off the new struct ifnet member, if_l2com. This change removes the size of these structures from the kernel ABI and will allow us to better manage them as interfaces come and go. Other changes of note: - Struct arpcom is no longer referenced in normal interface code. Instead the Ethernet address is accessed via the IFP2ENADDR() macro. To enforce this ac_enaddr has been renamed to _ac_enaddr. - The second argument to ether_ifattach is now always the mac address from driver private storage rather than sometimes being ac_enaddr. Reviewed by: sobomax, sam
2005-06-10 16:49:24 +00:00
ifp = sc->sis_ifp = if_alloc(IFT_ETHER);
if (ifp == NULL) {
Small fixes to sis(4): - Remove sis_unit and use device_printf() and if_printf() instead. - Use callout_init_mtx() for the callout. - Remove spls. - Fix locking for ifmedia to happen in the ifmedia handlers rather than in sis_ioctl(). - Log an error message if we fail to allocate any resources. Perform cleanup if we fail to allocate any resources so that we don't leave a mutex hanging around. Tested by: Jason Tsai jason dot tsai at newcyberian dot com (1-4) MFC after: 3 days
2005-09-26 18:42:27 +00:00
device_printf(dev, "can not if_alloc()\n");
Stop embedding struct ifnet at the top of driver softcs. Instead the struct ifnet or the layer 2 common structure it was embedded in have been replaced with a struct ifnet pointer to be filled by a call to the new function, if_alloc(). The layer 2 common structure is also allocated via if_alloc() based on the interface type. It is hung off the new struct ifnet member, if_l2com. This change removes the size of these structures from the kernel ABI and will allow us to better manage them as interfaces come and go. Other changes of note: - Struct arpcom is no longer referenced in normal interface code. Instead the Ethernet address is accessed via the IFP2ENADDR() macro. To enforce this ac_enaddr has been renamed to _ac_enaddr. - The second argument to ether_ifattach is now always the mac address from driver private storage rather than sometimes being ac_enaddr. Reviewed by: sobomax, sam
2005-06-10 16:49:24 +00:00
error = ENOSPC;
goto fail;
}
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
ifp->if_softc = sc;
Replace the if_name and if_unit members of struct ifnet with new members if_xname, if_dname, and if_dunit. if_xname is the name of the interface and if_dname/unit are the driver name and instance. This change paves the way for interface renaming and enhanced pseudo device creation and configuration symantics. Approved By: re (in principle) Reviewed By: njl, imp Tested On: i386, amd64, sparc64 Obtained From: NetBSD (if_xname)
2003-10-31 18:32:15 +00:00
if_initname(ifp, device_get_name(dev), device_get_unit(dev));
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = sis_ioctl;
ifp->if_start = sis_start;
ifp->if_init = sis_init;
Bring in the first chunk of altq driver modifications. This covers the following drivers: bfe(4), em(4), fxp(4), lnc(4), tun(4), de(4) rl(4), sis(4) and xl(4) More patches are pending on: http://peoples.freebsd.org/~mlaier/ Please take a look and tell me if "your" driver is missing, so I can fix this. Tested-by: many No-objection: -current, -net
2004-07-02 12:16:02 +00:00
IFQ_SET_MAXLEN(&ifp->if_snd, SIS_TX_LIST_CNT - 1);
ifp->if_snd.ifq_drv_maxlen = SIS_TX_LIST_CNT - 1;
IFQ_SET_READY(&ifp->if_snd);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Do a sweep of the tree replacing calls to pci_find_extcap() with calls to pci_find_cap() instead.
2011-03-23 13:10:15 +00:00
if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) == 0) {
Initial WOL support. NS DP8315 was tested but SiS900/SiS7016 was not tested. While I'm here, clean up SIOCSIFCAP handler.
2010-09-03 00:34:45 +00:00
if (sc->sis_type == SIS_TYPE_83815)
ifp->if_capabilities |= IFCAP_WOL;
else
ifp->if_capabilities |= IFCAP_WOL_MAGIC;
ifp->if_capenable = ifp->if_capabilities;
}
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
/*
* Do MII setup.
*/
Converted the remainder of the NIC drivers to use the mii_attach() introduced in r213878 instead of mii_phy_probe(). Unlike r213893 these are only straight forward conversions though. Reviewed by: yongari
2010-10-15 15:00:30 +00:00
error = mii_attach(dev, &sc->sis_miibus, ifp, sis_ifmedia_upd,
sis_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
if (error != 0) {
device_printf(dev, "attaching PHYs failed\n");
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
goto fail;
}
/*
Make all Ethernet drivers attach using ether_ifattach() and detach using ether_ifdetach(). The former consolidates the operations of if_attach(), ng_ether_attach(), and bpfattach(). The latter consolidates the corresponding detach operations. Reviewed by: julian, freebsd-net
2000-07-13 22:54:34 +00:00
* Call MI attach routine.
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
*/
o track either_ifattach/ether_ifdetach API changes o use if_input for input packet processing o don't strip the Ethernet header for input packets o use BPF_* macros bpf tapping o call ether_ioctl to handle default ioctl case o track vlan changes Reviewed by: many Approved by: re
2002-11-14 23:49:09 +00:00
ether_ifattach(ifp, eaddr);
Remove leading and trailing white spaces. No functional changes.
2010-09-01 18:28:08 +00:00
Add VLAN support. MFC after: 7 days
2001-12-05 09:34:28 +00:00
/*
* Tell the upper layer(s) we support long frames.
*/
Use define from if_var.h to access a field inside struct if_data, that resides in struct ifnet. Sponsored by: Nginx, Inc.
2014-08-30 19:55:54 +00:00
ifp->if_hdrlen = sizeof(struct ether_vlan_header);
o track either_ifattach/ether_ifdetach API changes o use if_input for input packet processing o don't strip the Ethernet header for input packets o use BPF_* macros bpf tapping o call ether_ioctl to handle default ioctl case o track vlan changes Reviewed by: many Approved by: re
2002-11-14 23:49:09 +00:00
ifp->if_capabilities |= IFCAP_VLAN_MTU;
Big polling(4) cleanup. o Axe poll in trap. o Axe IFF_POLLING flag from if_flags. o Rework revision 1.21 (Giant removal), in such a way that poll_mtx is not dropped during call to polling handler. This fixes problem with idle polling. o Make registration and deregistration from polling in a functional way, insted of next tick/interrupt. o Obsolete kern.polling.enable. Polling is turned on/off with ifconfig. Detailed kern_poll.c changes: - Remove polling handler flags, introduced in 1.21. The are not needed now. - Forget and do not check if_flags, if_capenable and if_drv_flags. - Call all registered polling handlers unconditionally. - Do not drop poll_mtx, when entering polling handlers. - In ether_poll() NET_LOCK_GIANT prior to locking poll_mtx. - In netisr_poll() axe the block, where polling code asks drivers to unregister. - In netisr_poll() and ether_poll() do polling always, if any handlers are present. - In ether_poll_[de]register() remove a lot of error hiding code. Assert that arguments are correct, instead. - In ether_poll_[de]register() use standard return values in case of error or success. - Introduce poll_switch() that is a sysctl handler for kern.polling.enable. poll_switch() goes through interface list and enabled/disables polling. A message that kern.polling.enable is deprecated is printed. Detailed driver changes: - On attach driver announces IFCAP_POLLING in if_capabilities, but not in if_capenable. - On detach driver calls ether_poll_deregister() if polling is enabled. - In polling handler driver obtains its lock and checks IFF_DRV_RUNNING flag. If there is no, then unlocks and returns. - In ioctl handler driver checks for IFCAP_POLLING flag requested to be set or cleared. Driver first calls ether_poll_[de]register(), then obtains driver lock and [dis/en]ables interrupts. - In interrupt handler driver checks IFCAP_POLLING flag in if_capenable. If present, then returns.This is important to protect from spurious interrupts. Reviewed by: ru, sam, jhb
2005-10-01 18:56:19 +00:00
ifp->if_capenable = ifp->if_capabilities;
Implemented per-interface polling(4) control.
2004-04-11 20:34:08 +00:00
#ifdef DEVICE_POLLING
ifp->if_capabilities |= IFCAP_POLLING;
#endif
Revise attach/detach resource cleanup - Unconditionally call *_stop() if device is in the tree. This is to prevent callouts from happening after the device is gone. Checks for bus_child_present() should be added in the future to keep from touching potentially non-existent hardware in *_detach(). Found by iedowse@. - Always check for and free miibus children, even if the device is not in the tree since some failure cases could have gotten here. - Call ether_ifdetach() in the irq setup failure case - ti(4), xl(4): move ifmedia_init() calls to the beginning of attach so that ifmedia_removeall() can be unconditionally called on detach. There is no way to detect whether ifmedia has been initialized without using a separate variable (as tl(4) does). - Add comments to indicate assumptions of code path
2003-04-17 20:32:06 +00:00
/* Hook interrupt last to avoid having to lock softc */
Use the new bus_space/resource convenience functions.
2005-09-24 20:46:02 +00:00
error = bus_setup_intr(dev, sc->sis_res[1], INTR_TYPE_NET | INTR_MPSAFE,
o break newbus api: add a new argument of type driver_filter_t to bus_setup_intr() o add an int return code to all fast handlers o retire INTR_FAST/IH_FAST For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current Reviewed by: many Approved by: re@
2007-02-23 12:19:07 +00:00
NULL, sis_intr, sc, &sc->sis_intrhand);
Clean up locking and resource management for pci/if_* - Remove locking of the softc in the attach method, instead depending on bus_setup_intr being at the end of attach (delaying interrupt enable until after ether_ifattach is called) - Call *_detach directly in the error case of attach, depending on checking in detach to only free resources that were allocated. This puts all resource freeing in one place, avoiding thinkos that lead to memory leaks. - Add bus_child_present check to calls to *_stop in the detach method to be sure hw is present before touching its registers. - Remove bzero softc calls since device_t should do this for us. - dc: move interrupt allocation back where it was before. It was unnecessary to move it. This reverts part of 1.88 - rl: move irq allocation before ether_ifattach. Problems might have been caused by allocating the irq after enabling interrupts on the card. - rl: call rl_stop before ether_ifdetach - sf: call sf_stop before ether_ifdetach - sis: add missed free of sis_tag - sis: check errors from tag creation - sis: move dmamem_alloc and dmamap_load to happen at same time as tag creation - sk: remove duplicate initialization of sk_dev - ste: add missed bus_generic_detach - ti: call ti_stop before ether_ifdetach - ti: add missed error setting in ti_rdata alloc failure - vr: add missed error setting in I/O, memory mapping cases - xl: add missed error setting in I/O, memory mapping cases - xl: remove multi-level goto on attach failure - xl: move dmamem_alloc and dmamap_load to happen at same time as tag creation - Calls to free(9) are unconditional because it is valid to call free with a null pointer. Reviewed by: imp, mdodd
2003-03-31 17:29:43 +00:00
if (error) {
Small fixes to sis(4): - Remove sis_unit and use device_printf() and if_printf() instead. - Use callout_init_mtx() for the callout. - Remove spls. - Fix locking for ifmedia to happen in the ifmedia handlers rather than in sis_ioctl(). - Log an error message if we fail to allocate any resources. Perform cleanup if we fail to allocate any resources so that we don't leave a mutex hanging around. Tested by: Jason Tsai jason dot tsai at newcyberian dot com (1-4) MFC after: 3 days
2005-09-26 18:42:27 +00:00
device_printf(dev, "couldn't set up irq\n");
Revise attach/detach resource cleanup - Unconditionally call *_stop() if device is in the tree. This is to prevent callouts from happening after the device is gone. Checks for bus_child_present() should be added in the future to keep from touching potentially non-existent hardware in *_detach(). Found by iedowse@. - Always check for and free miibus children, even if the device is not in the tree since some failure cases could have gotten here. - Call ether_ifdetach() in the irq setup failure case - ti(4), xl(4): move ifmedia_init() calls to the beginning of attach so that ifmedia_removeall() can be unconditionally called on detach. There is no way to detect whether ifmedia has been initialized without using a separate variable (as tl(4) does). - Add comments to indicate assumptions of code path
2003-04-17 20:32:06 +00:00
ether_ifdetach(ifp);
Clean up locking and resource management for pci/if_* - Remove locking of the softc in the attach method, instead depending on bus_setup_intr being at the end of attach (delaying interrupt enable until after ether_ifattach is called) - Call *_detach directly in the error case of attach, depending on checking in detach to only free resources that were allocated. This puts all resource freeing in one place, avoiding thinkos that lead to memory leaks. - Add bus_child_present check to calls to *_stop in the detach method to be sure hw is present before touching its registers. - Remove bzero softc calls since device_t should do this for us. - dc: move interrupt allocation back where it was before. It was unnecessary to move it. This reverts part of 1.88 - rl: move irq allocation before ether_ifattach. Problems might have been caused by allocating the irq after enabling interrupts on the card. - rl: call rl_stop before ether_ifdetach - sf: call sf_stop before ether_ifdetach - sis: add missed free of sis_tag - sis: check errors from tag creation - sis: move dmamem_alloc and dmamap_load to happen at same time as tag creation - sk: remove duplicate initialization of sk_dev - ste: add missed bus_generic_detach - ti: call ti_stop before ether_ifdetach - ti: add missed error setting in ti_rdata alloc failure - vr: add missed error setting in I/O, memory mapping cases - xl: add missed error setting in I/O, memory mapping cases - xl: remove multi-level goto on attach failure - xl: move dmamem_alloc and dmamap_load to happen at same time as tag creation - Calls to free(9) are unconditional because it is valid to call free with a null pointer. Reviewed by: imp, mdodd
2003-03-31 17:29:43 +00:00
goto fail;
}
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
fail:
Clean up locking and resource management for pci/if_* - Remove locking of the softc in the attach method, instead depending on bus_setup_intr being at the end of attach (delaying interrupt enable until after ether_ifattach is called) - Call *_detach directly in the error case of attach, depending on checking in detach to only free resources that were allocated. This puts all resource freeing in one place, avoiding thinkos that lead to memory leaks. - Add bus_child_present check to calls to *_stop in the detach method to be sure hw is present before touching its registers. - Remove bzero softc calls since device_t should do this for us. - dc: move interrupt allocation back where it was before. It was unnecessary to move it. This reverts part of 1.88 - rl: move irq allocation before ether_ifattach. Problems might have been caused by allocating the irq after enabling interrupts on the card. - rl: call rl_stop before ether_ifdetach - sf: call sf_stop before ether_ifdetach - sis: add missed free of sis_tag - sis: check errors from tag creation - sis: move dmamem_alloc and dmamap_load to happen at same time as tag creation - sk: remove duplicate initialization of sk_dev - ste: add missed bus_generic_detach - ti: call ti_stop before ether_ifdetach - ti: add missed error setting in ti_rdata alloc failure - vr: add missed error setting in I/O, memory mapping cases - xl: add missed error setting in I/O, memory mapping cases - xl: remove multi-level goto on attach failure - xl: move dmamem_alloc and dmamap_load to happen at same time as tag creation - Calls to free(9) are unconditional because it is valid to call free with a null pointer. Reviewed by: imp, mdodd
2003-03-31 17:29:43 +00:00
if (error)
sis_detach(dev);
style(9) - space after keywords.
2010-09-01 18:39:35 +00:00
return (error);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
Revise attach/detach resource cleanup - Unconditionally call *_stop() if device is in the tree. This is to prevent callouts from happening after the device is gone. Checks for bus_child_present() should be added in the future to keep from touching potentially non-existent hardware in *_detach(). Found by iedowse@. - Always check for and free miibus children, even if the device is not in the tree since some failure cases could have gotten here. - Call ether_ifdetach() in the irq setup failure case - ti(4), xl(4): move ifmedia_init() calls to the beginning of attach so that ifmedia_removeall() can be unconditionally called on detach. There is no way to detect whether ifmedia has been initialized without using a separate variable (as tl(4) does). - Add comments to indicate assumptions of code path
2003-04-17 20:32:06 +00:00
/*
* Shutdown hardware and free up resources. This can be called any
* time after the mutex has been initialized. It is called in both
* the error case in attach and the normal detach case so it needs
* to be careful about only freeing resources that have actually been
* allocated.
*/
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static int
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
sis_detach(device_t dev)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
struct sis_softc *sc;
struct ifnet *ifp;
sc = device_get_softc(dev);
Add missing ()'s so that these drivers all compile again. Noticed by: jake Tested on: i386 (compile)
2003-03-31 20:22:00 +00:00
KASSERT(mtx_initialized(&sc->sis_mtx), ("sis mutex not initialized"));
Stop embedding struct ifnet at the top of driver softcs. Instead the struct ifnet or the layer 2 common structure it was embedded in have been replaced with a struct ifnet pointer to be filled by a call to the new function, if_alloc(). The layer 2 common structure is also allocated via if_alloc() based on the interface type. It is hung off the new struct ifnet member, if_l2com. This change removes the size of these structures from the kernel ABI and will allow us to better manage them as interfaces come and go. Other changes of note: - Struct arpcom is no longer referenced in normal interface code. Instead the Ethernet address is accessed via the IFP2ENADDR() macro. To enforce this ac_enaddr has been renamed to _ac_enaddr. - The second argument to ether_ifattach is now always the mac address from driver private storage rather than sometimes being ac_enaddr. Reviewed by: sobomax, sam
2005-06-10 16:49:24 +00:00
ifp = sc->sis_ifp;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Big polling(4) cleanup. o Axe poll in trap. o Axe IFF_POLLING flag from if_flags. o Rework revision 1.21 (Giant removal), in such a way that poll_mtx is not dropped during call to polling handler. This fixes problem with idle polling. o Make registration and deregistration from polling in a functional way, insted of next tick/interrupt. o Obsolete kern.polling.enable. Polling is turned on/off with ifconfig. Detailed kern_poll.c changes: - Remove polling handler flags, introduced in 1.21. The are not needed now. - Forget and do not check if_flags, if_capenable and if_drv_flags. - Call all registered polling handlers unconditionally. - Do not drop poll_mtx, when entering polling handlers. - In ether_poll() NET_LOCK_GIANT prior to locking poll_mtx. - In netisr_poll() axe the block, where polling code asks drivers to unregister. - In netisr_poll() and ether_poll() do polling always, if any handlers are present. - In ether_poll_[de]register() remove a lot of error hiding code. Assert that arguments are correct, instead. - In ether_poll_[de]register() use standard return values in case of error or success. - Introduce poll_switch() that is a sysctl handler for kern.polling.enable. poll_switch() goes through interface list and enabled/disables polling. A message that kern.polling.enable is deprecated is printed. Detailed driver changes: - On attach driver announces IFCAP_POLLING in if_capabilities, but not in if_capenable. - On detach driver calls ether_poll_deregister() if polling is enabled. - In polling handler driver obtains its lock and checks IFF_DRV_RUNNING flag. If there is no, then unlocks and returns. - In ioctl handler driver checks for IFCAP_POLLING flag requested to be set or cleared. Driver first calls ether_poll_[de]register(), then obtains driver lock and [dis/en]ables interrupts. - In interrupt handler driver checks IFCAP_POLLING flag in if_capenable. If present, then returns.This is important to protect from spurious interrupts. Reviewed by: ru, sam, jhb
2005-10-01 18:56:19 +00:00
#ifdef DEVICE_POLLING
if (ifp->if_capenable & IFCAP_POLLING)
ether_poll_deregister(ifp);
#endif
Use the BUS_DMA_ZERO flag.
2003-07-27 14:38:54 +00:00
/* These should only be active if attach succeeded. */
Use newly minted device_is_attached rather than device_is_alive to see if attach succeeded. device_is_alive just tells us that probe succeeded. Since we were using it to do things like detach net interfaces, this caused problems when there were errors in the attach routine. Symptoms of problem reported by: martin blapp
2003-04-21 18:34:04 +00:00
if (device_is_attached(dev)) {
Small fixes to sis(4): - Remove sis_unit and use device_printf() and if_printf() instead. - Use callout_init_mtx() for the callout. - Remove spls. - Fix locking for ifmedia to happen in the ifmedia handlers rather than in sis_ioctl(). - Log an error message if we fail to allocate any resources. Perform cleanup if we fail to allocate any resources so that we don't leave a mutex hanging around. Tested by: Jason Tsai jason dot tsai at newcyberian dot com (1-4) MFC after: 3 days
2005-09-26 18:42:27 +00:00
SIS_LOCK(sc);
Revise attach/detach resource cleanup - Unconditionally call *_stop() if device is in the tree. This is to prevent callouts from happening after the device is gone. Checks for bus_child_present() should be added in the future to keep from touching potentially non-existent hardware in *_detach(). Found by iedowse@. - Always check for and free miibus children, even if the device is not in the tree since some failure cases could have gotten here. - Call ether_ifdetach() in the irq setup failure case - ti(4), xl(4): move ifmedia_init() calls to the beginning of attach so that ifmedia_removeall() can be unconditionally called on detach. There is no way to detect whether ifmedia has been initialized without using a separate variable (as tl(4) does). - Add comments to indicate assumptions of code path
2003-04-17 20:32:06 +00:00
sis_stop(sc);
Small fixes to sis(4): - Remove sis_unit and use device_printf() and if_printf() instead. - Use callout_init_mtx() for the callout. - Remove spls. - Fix locking for ifmedia to happen in the ifmedia handlers rather than in sis_ioctl(). - Log an error message if we fail to allocate any resources. Perform cleanup if we fail to allocate any resources so that we don't leave a mutex hanging around. Tested by: Jason Tsai jason dot tsai at newcyberian dot com (1-4) MFC after: 3 days
2005-09-26 18:42:27 +00:00
SIS_UNLOCK(sc);
callout_drain(&sc->sis_stat_ch);
Clean up locking and resource management for pci/if_* - Remove locking of the softc in the attach method, instead depending on bus_setup_intr being at the end of attach (delaying interrupt enable until after ether_ifattach is called) - Call *_detach directly in the error case of attach, depending on checking in detach to only free resources that were allocated. This puts all resource freeing in one place, avoiding thinkos that lead to memory leaks. - Add bus_child_present check to calls to *_stop in the detach method to be sure hw is present before touching its registers. - Remove bzero softc calls since device_t should do this for us. - dc: move interrupt allocation back where it was before. It was unnecessary to move it. This reverts part of 1.88 - rl: move irq allocation before ether_ifattach. Problems might have been caused by allocating the irq after enabling interrupts on the card. - rl: call rl_stop before ether_ifdetach - sf: call sf_stop before ether_ifdetach - sis: add missed free of sis_tag - sis: check errors from tag creation - sis: move dmamem_alloc and dmamap_load to happen at same time as tag creation - sk: remove duplicate initialization of sk_dev - ste: add missed bus_generic_detach - ti: call ti_stop before ether_ifdetach - ti: add missed error setting in ti_rdata alloc failure - vr: add missed error setting in I/O, memory mapping cases - xl: add missed error setting in I/O, memory mapping cases - xl: remove multi-level goto on attach failure - xl: move dmamem_alloc and dmamap_load to happen at same time as tag creation - Calls to free(9) are unconditional because it is valid to call free with a null pointer. Reviewed by: imp, mdodd
2003-03-31 17:29:43 +00:00
ether_ifdetach(ifp);
}
Revise attach/detach resource cleanup - Unconditionally call *_stop() if device is in the tree. This is to prevent callouts from happening after the device is gone. Checks for bus_child_present() should be added in the future to keep from touching potentially non-existent hardware in *_detach(). Found by iedowse@. - Always check for and free miibus children, even if the device is not in the tree since some failure cases could have gotten here. - Call ether_ifdetach() in the irq setup failure case - ti(4), xl(4): move ifmedia_init() calls to the beginning of attach so that ifmedia_removeall() can be unconditionally called on detach. There is no way to detect whether ifmedia has been initialized without using a separate variable (as tl(4) does). - Add comments to indicate assumptions of code path
2003-04-17 20:32:06 +00:00
if (sc->sis_miibus)
device_delete_child(dev, sc->sis_miibus);
bus_generic_detach(dev);
Clean up locking and resource management for pci/if_* - Remove locking of the softc in the attach method, instead depending on bus_setup_intr being at the end of attach (delaying interrupt enable until after ether_ifattach is called) - Call *_detach directly in the error case of attach, depending on checking in detach to only free resources that were allocated. This puts all resource freeing in one place, avoiding thinkos that lead to memory leaks. - Add bus_child_present check to calls to *_stop in the detach method to be sure hw is present before touching its registers. - Remove bzero softc calls since device_t should do this for us. - dc: move interrupt allocation back where it was before. It was unnecessary to move it. This reverts part of 1.88 - rl: move irq allocation before ether_ifattach. Problems might have been caused by allocating the irq after enabling interrupts on the card. - rl: call rl_stop before ether_ifdetach - sf: call sf_stop before ether_ifdetach - sis: add missed free of sis_tag - sis: check errors from tag creation - sis: move dmamem_alloc and dmamap_load to happen at same time as tag creation - sk: remove duplicate initialization of sk_dev - ste: add missed bus_generic_detach - ti: call ti_stop before ether_ifdetach - ti: add missed error setting in ti_rdata alloc failure - vr: add missed error setting in I/O, memory mapping cases - xl: add missed error setting in I/O, memory mapping cases - xl: remove multi-level goto on attach failure - xl: move dmamem_alloc and dmamap_load to happen at same time as tag creation - Calls to free(9) are unconditional because it is valid to call free with a null pointer. Reviewed by: imp, mdodd
2003-03-31 17:29:43 +00:00
if (sc->sis_intrhand)
Use the new bus_space/resource convenience functions.
2005-09-24 20:46:02 +00:00
bus_teardown_intr(dev, sc->sis_res[1], sc->sis_intrhand);
bus_release_resources(dev, sis_res_spec, sc->sis_res);
Clean up locking and resource management for pci/if_* - Remove locking of the softc in the attach method, instead depending on bus_setup_intr being at the end of attach (delaying interrupt enable until after ether_ifattach is called) - Call *_detach directly in the error case of attach, depending on checking in detach to only free resources that were allocated. This puts all resource freeing in one place, avoiding thinkos that lead to memory leaks. - Add bus_child_present check to calls to *_stop in the detach method to be sure hw is present before touching its registers. - Remove bzero softc calls since device_t should do this for us. - dc: move interrupt allocation back where it was before. It was unnecessary to move it. This reverts part of 1.88 - rl: move irq allocation before ether_ifattach. Problems might have been caused by allocating the irq after enabling interrupts on the card. - rl: call rl_stop before ether_ifdetach - sf: call sf_stop before ether_ifdetach - sis: add missed free of sis_tag - sis: check errors from tag creation - sis: move dmamem_alloc and dmamap_load to happen at same time as tag creation - sk: remove duplicate initialization of sk_dev - ste: add missed bus_generic_detach - ti: call ti_stop before ether_ifdetach - ti: add missed error setting in ti_rdata alloc failure - vr: add missed error setting in I/O, memory mapping cases - xl: add missed error setting in I/O, memory mapping cases - xl: remove multi-level goto on attach failure - xl: move dmamem_alloc and dmamap_load to happen at same time as tag creation - Calls to free(9) are unconditional because it is valid to call free with a null pointer. Reviewed by: imp, mdodd
2003-03-31 17:29:43 +00:00
In detach method, move if_free() after bus_teardown_intr().
2005-10-13 21:11:20 +00:00
if (ifp)
if_free(ifp);
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
sis_dma_free(sc);
mtx_destroy(&sc->sis_mtx);
return (0);
}
struct sis_dmamap_arg {
bus_addr_t sis_busaddr;
};
static void
sis_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
{
struct sis_dmamap_arg *ctx;
if (error != 0)
return;
KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
ctx = (struct sis_dmamap_arg *)arg;
ctx->sis_busaddr = segs[0].ds_addr;
}
static int
sis_dma_ring_alloc(struct sis_softc *sc, bus_size_t alignment,
bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
bus_addr_t *paddr, const char *msg)
{
struct sis_dmamap_arg ctx;
int error;
error = bus_dma_tag_create(sc->sis_parent_tag, alignment, 0,
BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, maxsize, 1,
maxsize, 0, NULL, NULL, tag);
if (error != 0) {
device_printf(sc->sis_dev,
"could not create %s dma tag\n", msg);
return (ENOMEM);
Clean up locking and resource management for pci/if_* - Remove locking of the softc in the attach method, instead depending on bus_setup_intr being at the end of attach (delaying interrupt enable until after ether_ifattach is called) - Call *_detach directly in the error case of attach, depending on checking in detach to only free resources that were allocated. This puts all resource freeing in one place, avoiding thinkos that lead to memory leaks. - Add bus_child_present check to calls to *_stop in the detach method to be sure hw is present before touching its registers. - Remove bzero softc calls since device_t should do this for us. - dc: move interrupt allocation back where it was before. It was unnecessary to move it. This reverts part of 1.88 - rl: move irq allocation before ether_ifattach. Problems might have been caused by allocating the irq after enabling interrupts on the card. - rl: call rl_stop before ether_ifdetach - sf: call sf_stop before ether_ifdetach - sis: add missed free of sis_tag - sis: check errors from tag creation - sis: move dmamem_alloc and dmamap_load to happen at same time as tag creation - sk: remove duplicate initialization of sk_dev - ste: add missed bus_generic_detach - ti: call ti_stop before ether_ifdetach - ti: add missed error setting in ti_rdata alloc failure - vr: add missed error setting in I/O, memory mapping cases - xl: add missed error setting in I/O, memory mapping cases - xl: remove multi-level goto on attach failure - xl: move dmamem_alloc and dmamap_load to happen at same time as tag creation - Calls to free(9) are unconditional because it is valid to call free with a null pointer. Reviewed by: imp, mdodd
2003-03-31 17:29:43 +00:00
}
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
/* Allocate DMA'able memory for ring. */
error = bus_dmamem_alloc(*tag, (void **)ring,
BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
if (error != 0) {
device_printf(sc->sis_dev,
"could not allocate DMA'able memory for %s\n", msg);
return (ENOMEM);
}
/* Load the address of the ring. */
ctx.sis_busaddr = 0;
error = bus_dmamap_load(*tag, *map, *ring, maxsize, sis_dmamap_cb,
&ctx, BUS_DMA_NOWAIT);
if (error != 0) {
device_printf(sc->sis_dev,
"could not load DMA'able memory for %s\n", msg);
return (ENOMEM);
Clean up locking and resource management for pci/if_* - Remove locking of the softc in the attach method, instead depending on bus_setup_intr being at the end of attach (delaying interrupt enable until after ether_ifattach is called) - Call *_detach directly in the error case of attach, depending on checking in detach to only free resources that were allocated. This puts all resource freeing in one place, avoiding thinkos that lead to memory leaks. - Add bus_child_present check to calls to *_stop in the detach method to be sure hw is present before touching its registers. - Remove bzero softc calls since device_t should do this for us. - dc: move interrupt allocation back where it was before. It was unnecessary to move it. This reverts part of 1.88 - rl: move irq allocation before ether_ifattach. Problems might have been caused by allocating the irq after enabling interrupts on the card. - rl: call rl_stop before ether_ifdetach - sf: call sf_stop before ether_ifdetach - sis: add missed free of sis_tag - sis: check errors from tag creation - sis: move dmamem_alloc and dmamap_load to happen at same time as tag creation - sk: remove duplicate initialization of sk_dev - ste: add missed bus_generic_detach - ti: call ti_stop before ether_ifdetach - ti: add missed error setting in ti_rdata alloc failure - vr: add missed error setting in I/O, memory mapping cases - xl: add missed error setting in I/O, memory mapping cases - xl: remove multi-level goto on attach failure - xl: move dmamem_alloc and dmamap_load to happen at same time as tag creation - Calls to free(9) are unconditional because it is valid to call free with a null pointer. Reviewed by: imp, mdodd
2003-03-31 17:29:43 +00:00
}
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
*paddr = ctx.sis_busaddr;
return (0);
}
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
static int
sis_dma_alloc(struct sis_softc *sc)
{
struct sis_rxdesc *rxd;
struct sis_txdesc *txd;
int error, i;
/* Allocate the parent bus DMA tag appropriate for PCI. */
error = bus_dma_tag_create(bus_get_dma_tag(sc->sis_dev),
1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
0, NULL, NULL, &sc->sis_parent_tag);
if (error != 0) {
device_printf(sc->sis_dev,
"could not allocate parent dma tag\n");
return (ENOMEM);
}
/* Create RX ring. */
error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_RX_LIST_SZ,
&sc->sis_rx_list_tag, (uint8_t **)&sc->sis_rx_list,
&sc->sis_rx_list_map, &sc->sis_rx_paddr, "RX ring");
if (error)
return (error);
/* Create TX ring. */
error = sis_dma_ring_alloc(sc, SIS_DESC_ALIGN, SIS_TX_LIST_SZ,
&sc->sis_tx_list_tag, (uint8_t **)&sc->sis_tx_list,
&sc->sis_tx_list_map, &sc->sis_tx_paddr, "TX ring");
if (error)
return (error);
/* Create tag for RX mbufs. */
error = bus_dma_tag_create(sc->sis_parent_tag, SIS_RX_BUF_ALIGN, 0,
BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1,
MCLBYTES, 0, NULL, NULL, &sc->sis_rx_tag);
if (error) {
device_printf(sc->sis_dev, "could not allocate RX dma tag\n");
return (error);
}
/* Create tag for TX mbufs. */
error = bus_dma_tag_create(sc->sis_parent_tag, 1, 0,
BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
MCLBYTES * SIS_MAXTXSEGS, SIS_MAXTXSEGS, MCLBYTES, 0, NULL, NULL,
&sc->sis_tx_tag);
if (error) {
device_printf(sc->sis_dev, "could not allocate TX dma tag\n");
return (error);
}
/* Create DMA maps for RX buffers. */
error = bus_dmamap_create(sc->sis_rx_tag, 0, &sc->sis_rx_sparemap);
if (error) {
device_printf(sc->sis_dev,
"can't create spare DMA map for RX\n");
return (error);
}
for (i = 0; i < SIS_RX_LIST_CNT; i++) {
rxd = &sc->sis_rxdesc[i];
rxd->rx_m = NULL;
error = bus_dmamap_create(sc->sis_rx_tag, 0, &rxd->rx_dmamap);
if (error) {
device_printf(sc->sis_dev,
"can't create DMA map for RX\n");
return (error);
}
}
/* Create DMA maps for TX buffers. */
for (i = 0; i < SIS_TX_LIST_CNT; i++) {
txd = &sc->sis_txdesc[i];
txd->tx_m = NULL;
error = bus_dmamap_create(sc->sis_tx_tag, 0, &txd->tx_dmamap);
if (error) {
device_printf(sc->sis_dev,
"can't create DMA map for TX\n");
return (error);
}
}
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
style(9) - space after keywords.
2010-09-01 18:39:35 +00:00
return (0);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
static void
sis_dma_free(struct sis_softc *sc)
{
struct sis_rxdesc *rxd;
struct sis_txdesc *txd;
int i;
/* Destroy DMA maps for RX buffers. */
for (i = 0; i < SIS_RX_LIST_CNT; i++) {
rxd = &sc->sis_rxdesc[i];
if (rxd->rx_dmamap)
bus_dmamap_destroy(sc->sis_rx_tag, rxd->rx_dmamap);
}
if (sc->sis_rx_sparemap)
bus_dmamap_destroy(sc->sis_rx_tag, sc->sis_rx_sparemap);
/* Destroy DMA maps for TX buffers. */
for (i = 0; i < SIS_TX_LIST_CNT; i++) {
txd = &sc->sis_txdesc[i];
if (txd->tx_dmamap)
bus_dmamap_destroy(sc->sis_tx_tag, txd->tx_dmamap);
}
if (sc->sis_rx_tag)
bus_dma_tag_destroy(sc->sis_rx_tag);
if (sc->sis_tx_tag)
bus_dma_tag_destroy(sc->sis_tx_tag);
/* Destroy RX ring. */
Fix various NIC drivers to properly cleanup static DMA resources. In particular, don't check the value of the bus_dma map against NULL to determine if either bus_dmamem_alloc() or bus_dmamap_load() succeeded. Instead, assume that bus_dmamap_load() succeeeded (and thus that bus_dmamap_unload() should be called) if the bus address for a resource is non-zero, and assume that bus_dmamem_alloc() succeeded (and thus that bus_dmamem_free() should be called) if the virtual address for a resource is not NULL. In many cases these bugs could result in leaks when a driver was detached. Reviewed by: yongari MFC after: 2 weeks
2014-06-11 14:53:58 +00:00
if (sc->sis_rx_paddr)
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
bus_dmamap_unload(sc->sis_rx_list_tag, sc->sis_rx_list_map);
Fix various NIC drivers to properly cleanup static DMA resources. In particular, don't check the value of the bus_dma map against NULL to determine if either bus_dmamem_alloc() or bus_dmamap_load() succeeded. Instead, assume that bus_dmamap_load() succeeeded (and thus that bus_dmamap_unload() should be called) if the bus address for a resource is non-zero, and assume that bus_dmamem_alloc() succeeded (and thus that bus_dmamem_free() should be called) if the virtual address for a resource is not NULL. In many cases these bugs could result in leaks when a driver was detached. Reviewed by: yongari MFC after: 2 weeks
2014-06-11 14:53:58 +00:00
if (sc->sis_rx_list)
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
bus_dmamem_free(sc->sis_rx_list_tag, sc->sis_rx_list,
sc->sis_rx_list_map);
if (sc->sis_rx_list_tag)
bus_dma_tag_destroy(sc->sis_rx_list_tag);
/* Destroy TX ring. */
Fix various NIC drivers to properly cleanup static DMA resources. In particular, don't check the value of the bus_dma map against NULL to determine if either bus_dmamem_alloc() or bus_dmamap_load() succeeded. Instead, assume that bus_dmamap_load() succeeeded (and thus that bus_dmamap_unload() should be called) if the bus address for a resource is non-zero, and assume that bus_dmamem_alloc() succeeded (and thus that bus_dmamem_free() should be called) if the virtual address for a resource is not NULL. In many cases these bugs could result in leaks when a driver was detached. Reviewed by: yongari MFC after: 2 weeks
2014-06-11 14:53:58 +00:00
if (sc->sis_tx_paddr)
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
bus_dmamap_unload(sc->sis_tx_list_tag, sc->sis_tx_list_map);
Fix various NIC drivers to properly cleanup static DMA resources. In particular, don't check the value of the bus_dma map against NULL to determine if either bus_dmamem_alloc() or bus_dmamap_load() succeeded. Instead, assume that bus_dmamap_load() succeeeded (and thus that bus_dmamap_unload() should be called) if the bus address for a resource is non-zero, and assume that bus_dmamem_alloc() succeeded (and thus that bus_dmamem_free() should be called) if the virtual address for a resource is not NULL. In many cases these bugs could result in leaks when a driver was detached. Reviewed by: yongari MFC after: 2 weeks
2014-06-11 14:53:58 +00:00
if (sc->sis_tx_list)
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
bus_dmamem_free(sc->sis_tx_list_tag, sc->sis_tx_list,
sc->sis_tx_list_map);
if (sc->sis_tx_list_tag)
bus_dma_tag_destroy(sc->sis_tx_list_tag);
/* Destroy the parent tag. */
if (sc->sis_parent_tag)
bus_dma_tag_destroy(sc->sis_parent_tag);
}
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
/*
Rewrite the rx/tx ring initialization to use pointers instead of arrays.
2005-01-06 23:31:41 +00:00
* Initialize the TX and RX descriptors and allocate mbufs for them. Note that
* we arrange the descriptors in a closed ring, so that the last descriptor
* points back to the first.
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
*/
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static int
Rewrite the rx/tx ring initialization to use pointers instead of arrays.
2005-01-06 23:31:41 +00:00
sis_ring_init(struct sis_softc *sc)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
struct sis_rxdesc *rxd;
struct sis_txdesc *txd;
bus_addr_t next;
int error, i;
bzero(&sc->sis_tx_list[0], SIS_TX_LIST_SZ);
for (i = 0; i < SIS_TX_LIST_CNT; i++) {
txd = &sc->sis_txdesc[i];
txd->tx_m = NULL;
if (i == SIS_TX_LIST_CNT - 1)
next = SIS_TX_RING_ADDR(sc, 0);
Rewrite the rx/tx ring initialization to use pointers instead of arrays.
2005-01-06 23:31:41 +00:00
else
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
next = SIS_TX_RING_ADDR(sc, i + 1);
sc->sis_tx_list[i].sis_next = htole32(SIS_ADDR_LO(next));
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
Forget about the sis_list_data and sis_ring_data structures and embedd their fields directly in the softc structure. This is a no-op which shortens most of the affected source lines by N * 10 characters.
2005-01-04 22:25:58 +00:00
sc->sis_tx_prod = sc->sis_tx_cons = sc->sis_tx_cnt = 0;
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
sc->sis_rx_cons = 0;
bzero(&sc->sis_rx_list[0], SIS_RX_LIST_SZ);
for (i = 0; i < SIS_RX_LIST_CNT; i++) {
rxd = &sc->sis_rxdesc[i];
rxd->rx_desc = &sc->sis_rx_list[i];
if (i == SIS_RX_LIST_CNT - 1)
next = SIS_RX_RING_ADDR(sc, 0);
else
next = SIS_RX_RING_ADDR(sc, i + 1);
rxd->rx_desc->sis_next = htole32(SIS_ADDR_LO(next));
error = sis_newbuf(sc, rxd);
Rewrite the rx/tx ring initialization to use pointers instead of arrays.
2005-01-06 23:31:41 +00:00
if (error)
style(9) - space after keywords.
2010-09-01 18:39:35 +00:00
return (error);
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
}
bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
style(9) - space after keywords.
2010-09-01 18:39:35 +00:00
return (0);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
/*
* Initialize an RX descriptor and attach an MBUF cluster.
*/
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static int
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
sis_newbuf(struct sis_softc *sc, struct sis_rxdesc *rxd)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
struct mbuf *m;
bus_dma_segment_t segs[1];
bus_dmamap_t map;
int nsegs;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Mechanically substitute flags from historic mbuf allocator with malloc(9) flags in sys/dev.
2012-12-04 09:32:43 +00:00
m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
if (m == NULL)
return (ENOBUFS);
m->m_len = m->m_pkthdr.len = SIS_RXLEN;
#ifndef __NO_STRICT_ALIGNMENT
m_adj(m, SIS_RX_BUF_ALIGN);
#endif
Convert the if_sis and if_rl drivers to use the bus_dma API instead of calling vtophys() and contigmalloc()/contigfree() directly. Hopefully, I have shaken out all of the problems with busdma on the alpha now. (Everything seems to work as expected.) Also, change the max RX DMA limit to 1024 bytes instead of "unlimited," as the latter seems not to work correctly on the alpha that I tested. (At 100Mbps, all attempts to receive frames yield RX errors.)
2001-08-15 17:38:43 +00:00
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
if (bus_dmamap_load_mbuf_sg(sc->sis_rx_tag, sc->sis_rx_sparemap, m,
segs, &nsegs, 0) != 0) {
m_freem(m);
return (ENOBUFS);
}
KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
if (rxd->rx_m != NULL) {
bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap,
BUS_DMASYNC_POSTREAD);
bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap);
}
map = rxd->rx_dmamap;
rxd->rx_dmamap = sc->sis_rx_sparemap;
sc->sis_rx_sparemap = map;
bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap, BUS_DMASYNC_PREREAD);
rxd->rx_m = m;
rxd->rx_desc->sis_ptr = htole32(SIS_ADDR_LO(segs[0].ds_addr));
Make sure changing ownership of RX descriptor to be done as last operation. Previously ownership was transferred to hardware before setting address of new RX buffer such that it was possible for hardware to use wrong RX buffer address. While here keep compiler from re-ordering instructions by declaring descriptor members volatile. Memory barriers would do the same job but volatile is supposed to be cheaper than using memory barriers, especially on MP systems. Submitted by: marius MFC after: 1 week
2011-02-28 20:37:48 +00:00
rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN);
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
return (0);
}
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
static __inline void
sis_discard_rxbuf(struct sis_rxdesc *rxd)
{
Convert the if_sis and if_rl drivers to use the bus_dma API instead of calling vtophys() and contigmalloc()/contigfree() directly. Hopefully, I have shaken out all of the problems with busdma on the alpha now. (Everything seems to work as expected.) Also, change the max RX DMA limit to 1024 bytes instead of "unlimited," as the latter seems not to work correctly on the alpha that I tested. (At 100Mbps, all attempts to receive frames yield RX errors.)
2001-08-15 17:38:43 +00:00
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
rxd->rx_desc->sis_cmdsts = htole32(SIS_RXLEN);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
#ifndef __NO_STRICT_ALIGNMENT
static __inline void
sis_fixup_rx(struct mbuf *m)
{
uint16_t *src, *dst;
int i;
src = mtod(m, uint16_t *);
dst = src - (SIS_RX_BUF_ALIGN - ETHER_ALIGN) / sizeof(*src);
for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
*dst++ = *src++;
m->m_data -= SIS_RX_BUF_ALIGN - ETHER_ALIGN;
}
#endif
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
/*
* A frame has been uploaded: pass the resulting mbuf chain up to
* the higher level protocols.
*/
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
static int
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
sis_rxeof(struct sis_softc *sc)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
struct mbuf *m;
Wrap code optimized for architectures without alignment constraints in #ifdef __NO_STRICT_ALIGNMENT rather than #if defined(__i386__) || defined(__amd64__). Currently this change is cosmetic only though. While at it, fix a nearby style(9) bug and remove a no longer used header.
2006-10-29 20:19:41 +00:00
struct ifnet *ifp;
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
struct sis_rxdesc *rxd;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
struct sis_desc *cur_rx;
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
int prog, rx_cons, rx_npkts = 0, total_len;
uint32_t rxstat;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Drop the driver lock around calls to if_input to avoid a LOR when the packets are immediately returned for sending (e.g. when bridging or packet forwarding). There are more efficient ways to do this but for now use the least intrusive approach. Reviewed by: imp, rwatson
2003-11-14 19:00:32 +00:00
SIS_LOCK_ASSERT(sc);
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
rx_cons = sc->sis_rx_cons;
ifp = sc->sis_ifp;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;
SIS_INC(rx_cons, SIS_RX_LIST_CNT), prog++) {
Device Polling code for -current. Non-SMP, i386-only, no polling in the idle loop at the moment. To use this code you must compile a kernel with options DEVICE_POLLING and at runtime enable polling with sysctl kern.polling.enable=1 The percentage of CPU reserved to userland can be set with sysctl kern.polling.user_frac=NN (default is 50) while the remainder is used by polling device drivers and netisr's. These are the only two variables that you should need to touch. There are a few more parameters in kern.polling but the default values are adequate for all purposes. See the code in kern_poll.c for more details on them. Polling in the idle loop will be implemented shortly by introducing a kernel thread which does the job. Until then, the amount of CPU dedicated to polling will never exceed (100-user_frac). The equivalent (actually, better) code for -stable is at http://info.iet.unipi.it/~luigi/polling/ and also supports polling in the idle loop. NOTE to Alpha developers: There is really nothing in this code that is i386-specific. If you move the 2 lines supporting the new option from sys/conf/{files,options}.i386 to sys/conf/{files,options} I am pretty sure that this should work on the Alpha as well, just that I do not have a suitable test box to try it. If someone feels like trying it, I would appreciate it. NOTE to other developers: sure some things could be done better, and as always I am open to constructive criticism, which a few of you have already given and I greatly appreciated. However, before proposing radical architectural changes, please take some time to possibly try out this code, or at the very least read the comments in kern_poll.c, especially re. the reason why I am using a soft netisr and cannot (I believe) replace it with a simple timeout. Quick description of files touched by this commit: sys/conf/files.i386 new file kern/kern_poll.c sys/conf/options.i386 new option sys/i386/i386/trap.c poll in trap (disabled by default) sys/kern/kern_clock.c initialization and hardclock hooks. sys/kern/kern_intr.c minor swi_net changes sys/kern/kern_poll.c the bulk of the code. sys/net/if.h new flag sys/net/if_var.h declaration for functions used in device drivers. sys/net/netisr.h NETISR_POLL sys/dev/fxp/if_fxp.c sys/dev/fxp/if_fxpvar.h sys/pci/if_dc.c sys/pci/if_dcreg.h sys/pci/if_sis.c sys/pci/if_sisreg.h device driver modifications
2001-12-14 17:56:12 +00:00
#ifdef DEVICE_POLLING
Big polling(4) cleanup. o Axe poll in trap. o Axe IFF_POLLING flag from if_flags. o Rework revision 1.21 (Giant removal), in such a way that poll_mtx is not dropped during call to polling handler. This fixes problem with idle polling. o Make registration and deregistration from polling in a functional way, insted of next tick/interrupt. o Obsolete kern.polling.enable. Polling is turned on/off with ifconfig. Detailed kern_poll.c changes: - Remove polling handler flags, introduced in 1.21. The are not needed now. - Forget and do not check if_flags, if_capenable and if_drv_flags. - Call all registered polling handlers unconditionally. - Do not drop poll_mtx, when entering polling handlers. - In ether_poll() NET_LOCK_GIANT prior to locking poll_mtx. - In netisr_poll() axe the block, where polling code asks drivers to unregister. - In netisr_poll() and ether_poll() do polling always, if any handlers are present. - In ether_poll_[de]register() remove a lot of error hiding code. Assert that arguments are correct, instead. - In ether_poll_[de]register() use standard return values in case of error or success. - Introduce poll_switch() that is a sysctl handler for kern.polling.enable. poll_switch() goes through interface list and enabled/disables polling. A message that kern.polling.enable is deprecated is printed. Detailed driver changes: - On attach driver announces IFCAP_POLLING in if_capabilities, but not in if_capenable. - On detach driver calls ether_poll_deregister() if polling is enabled. - In polling handler driver obtains its lock and checks IFF_DRV_RUNNING flag. If there is no, then unlocks and returns. - In ioctl handler driver checks for IFCAP_POLLING flag requested to be set or cleared. Driver first calls ether_poll_[de]register(), then obtains driver lock and [dis/en]ables interrupts. - In interrupt handler driver checks IFCAP_POLLING flag in if_capenable. If present, then returns.This is important to protect from spurious interrupts. Reviewed by: ru, sam, jhb
2005-10-01 18:56:19 +00:00
if (ifp->if_capenable & IFCAP_POLLING) {
Device Polling code for -current. Non-SMP, i386-only, no polling in the idle loop at the moment. To use this code you must compile a kernel with options DEVICE_POLLING and at runtime enable polling with sysctl kern.polling.enable=1 The percentage of CPU reserved to userland can be set with sysctl kern.polling.user_frac=NN (default is 50) while the remainder is used by polling device drivers and netisr's. These are the only two variables that you should need to touch. There are a few more parameters in kern.polling but the default values are adequate for all purposes. See the code in kern_poll.c for more details on them. Polling in the idle loop will be implemented shortly by introducing a kernel thread which does the job. Until then, the amount of CPU dedicated to polling will never exceed (100-user_frac). The equivalent (actually, better) code for -stable is at http://info.iet.unipi.it/~luigi/polling/ and also supports polling in the idle loop. NOTE to Alpha developers: There is really nothing in this code that is i386-specific. If you move the 2 lines supporting the new option from sys/conf/{files,options}.i386 to sys/conf/{files,options} I am pretty sure that this should work on the Alpha as well, just that I do not have a suitable test box to try it. If someone feels like trying it, I would appreciate it. NOTE to other developers: sure some things could be done better, and as always I am open to constructive criticism, which a few of you have already given and I greatly appreciated. However, before proposing radical architectural changes, please take some time to possibly try out this code, or at the very least read the comments in kern_poll.c, especially re. the reason why I am using a soft netisr and cannot (I believe) replace it with a simple timeout. Quick description of files touched by this commit: sys/conf/files.i386 new file kern/kern_poll.c sys/conf/options.i386 new option sys/i386/i386/trap.c poll in trap (disabled by default) sys/kern/kern_clock.c initialization and hardclock hooks. sys/kern/kern_intr.c minor swi_net changes sys/kern/kern_poll.c the bulk of the code. sys/net/if.h new flag sys/net/if_var.h declaration for functions used in device drivers. sys/net/netisr.h NETISR_POLL sys/dev/fxp/if_fxp.c sys/dev/fxp/if_fxpvar.h sys/pci/if_dc.c sys/pci/if_dcreg.h sys/pci/if_sis.c sys/pci/if_sisreg.h device driver modifications
2001-12-14 17:56:12 +00:00
if (sc->rxcycles <= 0)
break;
sc->rxcycles--;
}
Big polling(4) cleanup. o Axe poll in trap. o Axe IFF_POLLING flag from if_flags. o Rework revision 1.21 (Giant removal), in such a way that poll_mtx is not dropped during call to polling handler. This fixes problem with idle polling. o Make registration and deregistration from polling in a functional way, insted of next tick/interrupt. o Obsolete kern.polling.enable. Polling is turned on/off with ifconfig. Detailed kern_poll.c changes: - Remove polling handler flags, introduced in 1.21. The are not needed now. - Forget and do not check if_flags, if_capenable and if_drv_flags. - Call all registered polling handlers unconditionally. - Do not drop poll_mtx, when entering polling handlers. - In ether_poll() NET_LOCK_GIANT prior to locking poll_mtx. - In netisr_poll() axe the block, where polling code asks drivers to unregister. - In netisr_poll() and ether_poll() do polling always, if any handlers are present. - In ether_poll_[de]register() remove a lot of error hiding code. Assert that arguments are correct, instead. - In ether_poll_[de]register() use standard return values in case of error or success. - Introduce poll_switch() that is a sysctl handler for kern.polling.enable. poll_switch() goes through interface list and enabled/disables polling. A message that kern.polling.enable is deprecated is printed. Detailed driver changes: - On attach driver announces IFCAP_POLLING in if_capabilities, but not in if_capenable. - On detach driver calls ether_poll_deregister() if polling is enabled. - In polling handler driver obtains its lock and checks IFF_DRV_RUNNING flag. If there is no, then unlocks and returns. - In ioctl handler driver checks for IFCAP_POLLING flag requested to be set or cleared. Driver first calls ether_poll_[de]register(), then obtains driver lock and [dis/en]ables interrupts. - In interrupt handler driver checks IFCAP_POLLING flag in if_capenable. If present, then returns.This is important to protect from spurious interrupts. Reviewed by: ru, sam, jhb
2005-10-01 18:56:19 +00:00
#endif
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
cur_rx = &sc->sis_rx_list[rx_cons];
rxstat = le32toh(cur_rx->sis_cmdsts);
if ((rxstat & SIS_CMDSTS_OWN) == 0)
break;
rxd = &sc->sis_rxdesc[rx_cons];
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
total_len = (rxstat & SIS_CMDSTS_BUFLEN) - ETHER_CRC_LEN;
Fix a long standing VLAN tagged frame handling bug. When VLAN tagged frame is received the hardware sets 'LONG' bit of Rx status word. It is always set when the size of received frame exceeded 1518 bytes, including CRC. This VLAN tagged frame clears 'OK' bit of Rx status word such that driver should not rely on 'OK' bit of Rx status word to pass the VLAN tagged frame to upper stack. To fix the bug, don't use SIS_CMDSTS_PKT_OK for Rx error check and introduce SIS_RXSTAT_ERROR macro that checks Rx errors. If we are configured to accept VLAN tagged frames and the received frame size is less than or equal to maximum allowed length of VLAN tagged frame, clear 'LONG' bit of Rx status word before checking Rx errors. Reported by: Vladimir Ermako < samflanker <> gmail DOT com > Tested by: Vladimir Ermako < samflanker <> gmail DOT com >
2008-12-09 04:30:47 +00:00
if ((ifp->if_capenable & IFCAP_VLAN_MTU) != 0 &&
total_len <= (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN -
ETHER_CRC_LEN))
rxstat &= ~SIS_RXSTAT_GIANT;
if (SIS_RXSTAT_ERROR(rxstat) != 0) {
Mechanically convert to if_inc_counter().
2014-09-18 20:09:35 +00:00
if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
if (rxstat & SIS_RXSTAT_COLL)
Mechanically convert to if_inc_counter().
2014-09-18 20:09:35 +00:00
if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
sis_discard_rxbuf(rxd);
continue;
}
/* Add a new receive buffer to the ring. */
m = rxd->rx_m;
if (sis_newbuf(sc, rxd) != 0) {
Mechanically convert to if_inc_counter().
2014-09-18 20:09:35 +00:00
if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
sis_discard_rxbuf(rxd);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
continue;
}
Remove leading and trailing white spaces. No functional changes.
2010-09-01 18:28:08 +00:00
/* No errors; receive the packet. */
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
m->m_pkthdr.len = m->m_len = total_len;
#ifndef __NO_STRICT_ALIGNMENT
Remove the need for an expensive m_devget on the i386, which does not have alignment problems. On small boxes (e.g. the net4501 from Soekris, featuring a 486/133) this provides huge performance benefits: the peak forwarding rate with avg.sized packets goes up by 50-70% because of this change alone. Faster CPUs might benefit less from this change, but in any case the CPU has better things to do than waste time on useless memory-to-memory copies. Several drivers (for Tulip-like cards) might benefit from a similar change. Right now the new behaviour is controlled by a sysctl variable, hw.sis_quick which defaults to 1 (on), you can set it to 0 to reintroduce the old behaviour (and compare the results). The variable is only there to show how much you can gain with this change, it will go away soon. Also, slightly simplify the code to initialize the ring buffers, and remove a couple of dangerous printf's which could trigger on any packet in case of mbuf shortage. MFC-after: 3 days
2001-11-28 16:10:37 +00:00
/*
Wrap code optimized for architectures without alignment constraints in #ifdef __NO_STRICT_ALIGNMENT rather than #if defined(__i386__) || defined(__amd64__). Currently this change is cosmetic only though. While at it, fix a nearby style(9) bug and remove a no longer used header.
2006-10-29 20:19:41 +00:00
* On architectures without alignment problems we try to
Remove the need for an expensive m_devget on the i386, which does not have alignment problems. On small boxes (e.g. the net4501 from Soekris, featuring a 486/133) this provides huge performance benefits: the peak forwarding rate with avg.sized packets goes up by 50-70% because of this change alone. Faster CPUs might benefit less from this change, but in any case the CPU has better things to do than waste time on useless memory-to-memory copies. Several drivers (for Tulip-like cards) might benefit from a similar change. Right now the new behaviour is controlled by a sysctl variable, hw.sis_quick which defaults to 1 (on), you can set it to 0 to reintroduce the old behaviour (and compare the results). The variable is only there to show how much you can gain with this change, it will go away soon. Also, slightly simplify the code to initialize the ring buffers, and remove a couple of dangerous printf's which could trigger on any packet in case of mbuf shortage. MFC-after: 3 days
2001-11-28 16:10:37 +00:00
* allocate a new buffer for the receive ring, and pass up
* the one where the packet is already, saving the expensive
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
* copy operation.
Remove the need for an expensive m_devget on the i386, which does not have alignment problems. On small boxes (e.g. the net4501 from Soekris, featuring a 486/133) this provides huge performance benefits: the peak forwarding rate with avg.sized packets goes up by 50-70% because of this change alone. Faster CPUs might benefit less from this change, but in any case the CPU has better things to do than waste time on useless memory-to-memory copies. Several drivers (for Tulip-like cards) might benefit from a similar change. Right now the new behaviour is controlled by a sysctl variable, hw.sis_quick which defaults to 1 (on), you can set it to 0 to reintroduce the old behaviour (and compare the results). The variable is only there to show how much you can gain with this change, it will go away soon. Also, slightly simplify the code to initialize the ring buffers, and remove a couple of dangerous printf's which could trigger on any packet in case of mbuf shortage. MFC-after: 3 days
2001-11-28 16:10:37 +00:00
*/
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
sis_fixup_rx(m);
Remove the need for an expensive m_devget on the i386, which does not have alignment problems. On small boxes (e.g. the net4501 from Soekris, featuring a 486/133) this provides huge performance benefits: the peak forwarding rate with avg.sized packets goes up by 50-70% because of this change alone. Faster CPUs might benefit less from this change, but in any case the CPU has better things to do than waste time on useless memory-to-memory copies. Several drivers (for Tulip-like cards) might benefit from a similar change. Right now the new behaviour is controlled by a sysctl variable, hw.sis_quick which defaults to 1 (on), you can set it to 0 to reintroduce the old behaviour (and compare the results). The variable is only there to show how much you can gain with this change, it will go away soon. Also, slightly simplify the code to initialize the ring buffers, and remove a couple of dangerous printf's which could trigger on any packet in case of mbuf shortage. MFC-after: 3 days
2001-11-28 16:10:37 +00:00
#endif
Mechanically convert to if_inc_counter().
2014-09-18 20:09:35 +00:00
if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
o track either_ifattach/ether_ifdetach API changes o use if_input for input packet processing o don't strip the Ethernet header for input packets o use BPF_* macros bpf tapping o call ether_ioctl to handle default ioctl case o track vlan changes Reviewed by: many Approved by: re
2002-11-14 23:49:09 +00:00
m->m_pkthdr.rcvif = ifp;
Drop the driver lock around calls to if_input to avoid a LOR when the packets are immediately returned for sending (e.g. when bridging or packet forwarding). There are more efficient ways to do this but for now use the least intrusive approach. Reviewed by: imp, rwatson
2003-11-14 19:00:32 +00:00
SIS_UNLOCK(sc);
o track either_ifattach/ether_ifdetach API changes o use if_input for input packet processing o don't strip the Ethernet header for input packets o use BPF_* macros bpf tapping o call ether_ioctl to handle default ioctl case o track vlan changes Reviewed by: many Approved by: re
2002-11-14 23:49:09 +00:00
(*ifp->if_input)(ifp, m);
Drop the driver lock around calls to if_input to avoid a LOR when the packets are immediately returned for sending (e.g. when bridging or packet forwarding). There are more efficient ways to do this but for now use the least intrusive approach. Reviewed by: imp, rwatson
2003-11-14 19:00:32 +00:00
SIS_LOCK(sc);
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
rx_npkts++;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
if (prog > 0) {
sc->sis_rx_cons = rx_cons;
bus_dmamap_sync(sc->sis_rx_list_tag, sc->sis_rx_list_map,
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
}
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
return (rx_npkts);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
/*
* A frame was downloaded to the chip. It's safe for us to clean up
* the list buffers.
*/
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static void
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
sis_txeof(struct sis_softc *sc)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
struct ifnet *ifp;
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
struct sis_desc *cur_tx;
struct sis_txdesc *txd;
uint32_t cons, txstat;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Add locked/unlocked variants of sis_init()
2005-01-05 10:11:37 +00:00
SIS_LOCK_ASSERT(sc);
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
cons = sc->sis_tx_cons;
if (cons == sc->sis_tx_prod)
return;
Stop embedding struct ifnet at the top of driver softcs. Instead the struct ifnet or the layer 2 common structure it was embedded in have been replaced with a struct ifnet pointer to be filled by a call to the new function, if_alloc(). The layer 2 common structure is also allocated via if_alloc() based on the interface type. It is hung off the new struct ifnet member, if_l2com. This change removes the size of these structures from the kernel ABI and will allow us to better manage them as interfaces come and go. Other changes of note: - Struct arpcom is no longer referenced in normal interface code. Instead the Ethernet address is accessed via the IFP2ENADDR() macro. To enforce this ac_enaddr has been renamed to _ac_enaddr. - The second argument to ether_ifattach is now always the mac address from driver private storage rather than sometimes being ac_enaddr. Reviewed by: sobomax, sam
2005-06-10 16:49:24 +00:00
ifp = sc->sis_ifp;
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
/*
* Go through our tx list and free mbufs for those
* frames that have been transmitted.
*/
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
for (; cons != sc->sis_tx_prod; SIS_INC(cons, SIS_TX_LIST_CNT)) {
cur_tx = &sc->sis_tx_list[cons];
txstat = le32toh(cur_tx->sis_cmdsts);
if ((txstat & SIS_CMDSTS_OWN) != 0)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
break;
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
txd = &sc->sis_txdesc[cons];
if (txd->tx_m != NULL) {
bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap,
BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
m_freem(txd->tx_m);
txd->tx_m = NULL;
if ((txstat & SIS_CMDSTS_PKT_OK) != 0) {
Mechanically convert to if_inc_counter().
2014-09-18 20:09:35 +00:00
if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
(txstat & SIS_TXSTAT_COLLCNT) >> 16);
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
} else {
Mechanically convert to if_inc_counter().
2014-09-18 20:09:35 +00:00
if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
if (txstat & SIS_TXSTAT_EXCESSCOLLS)
Mechanically convert to if_inc_counter().
2014-09-18 20:09:35 +00:00
if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
if (txstat & SIS_TXSTAT_OUTOFWINCOLL)
Mechanically convert to if_inc_counter().
2014-09-18 20:09:35 +00:00
if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
}
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
sc->sis_tx_cnt--;
Propagate rename of IFF_OACTIVE and IFF_RUNNING to IFF_DRV_OACTIVE and IFF_DRV_RUNNING, as well as the move from ifnet.if_flags to ifnet.if_drv_flags. Device drivers are now responsible for synchronizing access to these flags, as they are in if_drv_flags. This helps prevent races between the network stack and device driver in maintaining the interface flags field. Many __FreeBSD__ and __FreeBSD_version checks maintained and continued; some less so. Reviewed by: pjd, bz MFC after: 7 days
2005-08-09 10:20:02 +00:00
ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
Make sure that if_timer does not get reset if there are packets still queued for transmission. This should solve the problem of the device stalling on transmissions if some link event prevents transmission. There are other drivers which have the same problem and need to be fixed in the same way. MFC after: 3 days
2002-06-30 21:59:08 +00:00
}
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
sc->sis_tx_cons = cons;
if (sc->sis_tx_cnt == 0)
sc->sis_watchdog_timer = 0;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static void
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
sis_tick(void *xsc)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
struct sis_softc *sc;
struct mii_data *mii;
sc = xsc;
Small fixes to sis(4): - Remove sis_unit and use device_printf() and if_printf() instead. - Use callout_init_mtx() for the callout. - Remove spls. - Fix locking for ifmedia to happen in the ifmedia handlers rather than in sis_ioctl(). - Log an error message if we fail to allocate any resources. Perform cleanup if we fail to allocate any resources so that we don't leave a mutex hanging around. Tested by: Jason Tsai jason dot tsai at newcyberian dot com (1-4) MFC after: 3 days
2005-09-26 18:42:27 +00:00
SIS_LOCK_ASSERT(sc);
Fix up the sis driver, largely to improve the NatSemi DP83815 support: - Modify the driver to poll the link state and positively set the MAC to full or half duplex as needed. Previously, it was possible for the MAC to remain in half duplex even though the PHY had negotiated full duplex with its link partner, which would result in bursty performance. - Program some of the NatSemi's registers as specified by the datasheet. The manual says these are necessary for "optimum perofrmance," though a couple of them are marked as reserved in the register map. *shrug* - Select the TX DMA burst size correctly for 10 and 100mbps modes. Previously I was using 64 bytes in both modes, which worked in 100mbps mode, but resulting in spotty performance in 10mbps. 32 bytes works much better; without this change, the natsemi chip yields piss poor performance at 10mbps. With these fixes, the NatSemi chip finally performs to my satisfaction. I should be merging the support for this controller into -stable shortly. Phew.
2000-08-22 23:26:51 +00:00
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
mii = device_get_softc(sc->sis_miibus);
mii_tick(mii);
Convert sis(4) to use its own watchdog procedure. Submitted by: Florian C. Smeets <flo kasimir com>
2007-02-24 14:27:36 +00:00
sis_watchdog(sc);
Unlike most other controllers, NS DP83815/DP83816 controllers seem to pad with 0xFF when it encounter short frames. According to RFC 1042 the pad bytes should be 0x00. Because manual padding consumes extra CPU cycles, introduce a new tunable which controls the padding behavior. Turning this tunable on will have driver pad manually but it's disabled by default. Users can enable software padding by setting the following tunable to non-zero value. dev.sis.%d.manual_pad="1" PR: kern/35422 (patch not used)
2010-09-02 18:10:11 +00:00
if ((sc->sis_flags & SIS_FLAG_LINK) == 0)
Overhaul link state change handling. Previously sis(4) blindly configured TX/RX MACs before getting a valid link. After that, when link state change callback is called, it called device initialization again to reconfigure TX/RX MACs depending on resolved link state. This hack created several bad side effects and it required more hacks to not collide with sis_tick callback as well as disabling switching to currently selected media in device initialization. Also it seems sis(4) was used to be a template driver for long time so other drivers which was modeled after sis(4) also should be changed. TX/RX MACs are now reconfigured after getting a valid link. Fix for short cable error is also applied after getting a link because it's only valid when the resolved speed is 100Mbps. While I'm here slightly reorganize interrupt handler such that sis(4) always read SIS_ISR register to see whether the interrupt is ours or not. This change removes another hack and make it possible to nuke sis_stopped variable in softc.
2010-09-01 21:42:19 +00:00
sis_miibus_statchg(sc->sis_dev);
change timer to MPSAFE Sponsored by: FreeBSD Foundation
2003-09-05 22:33:44 +00:00
callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
Device Polling code for -current. Non-SMP, i386-only, no polling in the idle loop at the moment. To use this code you must compile a kernel with options DEVICE_POLLING and at runtime enable polling with sysctl kern.polling.enable=1 The percentage of CPU reserved to userland can be set with sysctl kern.polling.user_frac=NN (default is 50) while the remainder is used by polling device drivers and netisr's. These are the only two variables that you should need to touch. There are a few more parameters in kern.polling but the default values are adequate for all purposes. See the code in kern_poll.c for more details on them. Polling in the idle loop will be implemented shortly by introducing a kernel thread which does the job. Until then, the amount of CPU dedicated to polling will never exceed (100-user_frac). The equivalent (actually, better) code for -stable is at http://info.iet.unipi.it/~luigi/polling/ and also supports polling in the idle loop. NOTE to Alpha developers: There is really nothing in this code that is i386-specific. If you move the 2 lines supporting the new option from sys/conf/{files,options}.i386 to sys/conf/{files,options} I am pretty sure that this should work on the Alpha as well, just that I do not have a suitable test box to try it. If someone feels like trying it, I would appreciate it. NOTE to other developers: sure some things could be done better, and as always I am open to constructive criticism, which a few of you have already given and I greatly appreciated. However, before proposing radical architectural changes, please take some time to possibly try out this code, or at the very least read the comments in kern_poll.c, especially re. the reason why I am using a soft netisr and cannot (I believe) replace it with a simple timeout. Quick description of files touched by this commit: sys/conf/files.i386 new file kern/kern_poll.c sys/conf/options.i386 new option sys/i386/i386/trap.c poll in trap (disabled by default) sys/kern/kern_clock.c initialization and hardclock hooks. sys/kern/kern_intr.c minor swi_net changes sys/kern/kern_poll.c the bulk of the code. sys/net/if.h new flag sys/net/if_var.h declaration for functions used in device drivers. sys/net/netisr.h NETISR_POLL sys/dev/fxp/if_fxp.c sys/dev/fxp/if_fxpvar.h sys/pci/if_dc.c sys/pci/if_dcreg.h sys/pci/if_sis.c sys/pci/if_sisreg.h device driver modifications
2001-12-14 17:56:12 +00:00
#ifdef DEVICE_POLLING
static poll_handler_t sis_poll;
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
static int
Device Polling code for -current. Non-SMP, i386-only, no polling in the idle loop at the moment. To use this code you must compile a kernel with options DEVICE_POLLING and at runtime enable polling with sysctl kern.polling.enable=1 The percentage of CPU reserved to userland can be set with sysctl kern.polling.user_frac=NN (default is 50) while the remainder is used by polling device drivers and netisr's. These are the only two variables that you should need to touch. There are a few more parameters in kern.polling but the default values are adequate for all purposes. See the code in kern_poll.c for more details on them. Polling in the idle loop will be implemented shortly by introducing a kernel thread which does the job. Until then, the amount of CPU dedicated to polling will never exceed (100-user_frac). The equivalent (actually, better) code for -stable is at http://info.iet.unipi.it/~luigi/polling/ and also supports polling in the idle loop. NOTE to Alpha developers: There is really nothing in this code that is i386-specific. If you move the 2 lines supporting the new option from sys/conf/{files,options}.i386 to sys/conf/{files,options} I am pretty sure that this should work on the Alpha as well, just that I do not have a suitable test box to try it. If someone feels like trying it, I would appreciate it. NOTE to other developers: sure some things could be done better, and as always I am open to constructive criticism, which a few of you have already given and I greatly appreciated. However, before proposing radical architectural changes, please take some time to possibly try out this code, or at the very least read the comments in kern_poll.c, especially re. the reason why I am using a soft netisr and cannot (I believe) replace it with a simple timeout. Quick description of files touched by this commit: sys/conf/files.i386 new file kern/kern_poll.c sys/conf/options.i386 new option sys/i386/i386/trap.c poll in trap (disabled by default) sys/kern/kern_clock.c initialization and hardclock hooks. sys/kern/kern_intr.c minor swi_net changes sys/kern/kern_poll.c the bulk of the code. sys/net/if.h new flag sys/net/if_var.h declaration for functions used in device drivers. sys/net/netisr.h NETISR_POLL sys/dev/fxp/if_fxp.c sys/dev/fxp/if_fxpvar.h sys/pci/if_dc.c sys/pci/if_dcreg.h sys/pci/if_sis.c sys/pci/if_sisreg.h device driver modifications
2001-12-14 17:56:12 +00:00
sis_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
{
Patch up some existing style bugs and some that crept in with the DEVICE_POLLING stuff.
2001-12-15 02:51:21 +00:00
struct sis_softc *sc = ifp->if_softc;
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
int rx_npkts = 0;
Patch up some existing style bugs and some that crept in with the DEVICE_POLLING stuff.
2001-12-15 02:51:21 +00:00
Device Polling code for -current. Non-SMP, i386-only, no polling in the idle loop at the moment. To use this code you must compile a kernel with options DEVICE_POLLING and at runtime enable polling with sysctl kern.polling.enable=1 The percentage of CPU reserved to userland can be set with sysctl kern.polling.user_frac=NN (default is 50) while the remainder is used by polling device drivers and netisr's. These are the only two variables that you should need to touch. There are a few more parameters in kern.polling but the default values are adequate for all purposes. See the code in kern_poll.c for more details on them. Polling in the idle loop will be implemented shortly by introducing a kernel thread which does the job. Until then, the amount of CPU dedicated to polling will never exceed (100-user_frac). The equivalent (actually, better) code for -stable is at http://info.iet.unipi.it/~luigi/polling/ and also supports polling in the idle loop. NOTE to Alpha developers: There is really nothing in this code that is i386-specific. If you move the 2 lines supporting the new option from sys/conf/{files,options}.i386 to sys/conf/{files,options} I am pretty sure that this should work on the Alpha as well, just that I do not have a suitable test box to try it. If someone feels like trying it, I would appreciate it. NOTE to other developers: sure some things could be done better, and as always I am open to constructive criticism, which a few of you have already given and I greatly appreciated. However, before proposing radical architectural changes, please take some time to possibly try out this code, or at the very least read the comments in kern_poll.c, especially re. the reason why I am using a soft netisr and cannot (I believe) replace it with a simple timeout. Quick description of files touched by this commit: sys/conf/files.i386 new file kern/kern_poll.c sys/conf/options.i386 new option sys/i386/i386/trap.c poll in trap (disabled by default) sys/kern/kern_clock.c initialization and hardclock hooks. sys/kern/kern_intr.c minor swi_net changes sys/kern/kern_poll.c the bulk of the code. sys/net/if.h new flag sys/net/if_var.h declaration for functions used in device drivers. sys/net/netisr.h NETISR_POLL sys/dev/fxp/if_fxp.c sys/dev/fxp/if_fxpvar.h sys/pci/if_dc.c sys/pci/if_dcreg.h sys/pci/if_sis.c sys/pci/if_sisreg.h device driver modifications
2001-12-14 17:56:12 +00:00
SIS_LOCK(sc);
Big polling(4) cleanup. o Axe poll in trap. o Axe IFF_POLLING flag from if_flags. o Rework revision 1.21 (Giant removal), in such a way that poll_mtx is not dropped during call to polling handler. This fixes problem with idle polling. o Make registration and deregistration from polling in a functional way, insted of next tick/interrupt. o Obsolete kern.polling.enable. Polling is turned on/off with ifconfig. Detailed kern_poll.c changes: - Remove polling handler flags, introduced in 1.21. The are not needed now. - Forget and do not check if_flags, if_capenable and if_drv_flags. - Call all registered polling handlers unconditionally. - Do not drop poll_mtx, when entering polling handlers. - In ether_poll() NET_LOCK_GIANT prior to locking poll_mtx. - In netisr_poll() axe the block, where polling code asks drivers to unregister. - In netisr_poll() and ether_poll() do polling always, if any handlers are present. - In ether_poll_[de]register() remove a lot of error hiding code. Assert that arguments are correct, instead. - In ether_poll_[de]register() use standard return values in case of error or success. - Introduce poll_switch() that is a sysctl handler for kern.polling.enable. poll_switch() goes through interface list and enabled/disables polling. A message that kern.polling.enable is deprecated is printed. Detailed driver changes: - On attach driver announces IFCAP_POLLING in if_capabilities, but not in if_capenable. - On detach driver calls ether_poll_deregister() if polling is enabled. - In polling handler driver obtains its lock and checks IFF_DRV_RUNNING flag. If there is no, then unlocks and returns. - In ioctl handler driver checks for IFCAP_POLLING flag requested to be set or cleared. Driver first calls ether_poll_[de]register(), then obtains driver lock and [dis/en]ables interrupts. - In interrupt handler driver checks IFCAP_POLLING flag in if_capenable. If present, then returns.This is important to protect from spurious interrupts. Reviewed by: ru, sam, jhb
2005-10-01 18:56:19 +00:00
if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
SIS_UNLOCK(sc);
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
return (rx_npkts);
Device Polling code for -current. Non-SMP, i386-only, no polling in the idle loop at the moment. To use this code you must compile a kernel with options DEVICE_POLLING and at runtime enable polling with sysctl kern.polling.enable=1 The percentage of CPU reserved to userland can be set with sysctl kern.polling.user_frac=NN (default is 50) while the remainder is used by polling device drivers and netisr's. These are the only two variables that you should need to touch. There are a few more parameters in kern.polling but the default values are adequate for all purposes. See the code in kern_poll.c for more details on them. Polling in the idle loop will be implemented shortly by introducing a kernel thread which does the job. Until then, the amount of CPU dedicated to polling will never exceed (100-user_frac). The equivalent (actually, better) code for -stable is at http://info.iet.unipi.it/~luigi/polling/ and also supports polling in the idle loop. NOTE to Alpha developers: There is really nothing in this code that is i386-specific. If you move the 2 lines supporting the new option from sys/conf/{files,options}.i386 to sys/conf/{files,options} I am pretty sure that this should work on the Alpha as well, just that I do not have a suitable test box to try it. If someone feels like trying it, I would appreciate it. NOTE to other developers: sure some things could be done better, and as always I am open to constructive criticism, which a few of you have already given and I greatly appreciated. However, before proposing radical architectural changes, please take some time to possibly try out this code, or at the very least read the comments in kern_poll.c, especially re. the reason why I am using a soft netisr and cannot (I believe) replace it with a simple timeout. Quick description of files touched by this commit: sys/conf/files.i386 new file kern/kern_poll.c sys/conf/options.i386 new option sys/i386/i386/trap.c poll in trap (disabled by default) sys/kern/kern_clock.c initialization and hardclock hooks. sys/kern/kern_intr.c minor swi_net changes sys/kern/kern_poll.c the bulk of the code. sys/net/if.h new flag sys/net/if_var.h declaration for functions used in device drivers. sys/net/netisr.h NETISR_POLL sys/dev/fxp/if_fxp.c sys/dev/fxp/if_fxpvar.h sys/pci/if_dc.c sys/pci/if_dcreg.h sys/pci/if_sis.c sys/pci/if_sisreg.h device driver modifications
2001-12-14 17:56:12 +00:00
}
/*
* On the sis, reading the status register also clears it.
* So before returning to intr mode we must make sure that all
* possible pending sources of interrupts have been served.
* In practice this means run to completion the *eof routines,
* and then call the interrupt routine
*/
sc->rxcycles = count;
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
rx_npkts = sis_rxeof(sc);
Device Polling code for -current. Non-SMP, i386-only, no polling in the idle loop at the moment. To use this code you must compile a kernel with options DEVICE_POLLING and at runtime enable polling with sysctl kern.polling.enable=1 The percentage of CPU reserved to userland can be set with sysctl kern.polling.user_frac=NN (default is 50) while the remainder is used by polling device drivers and netisr's. These are the only two variables that you should need to touch. There are a few more parameters in kern.polling but the default values are adequate for all purposes. See the code in kern_poll.c for more details on them. Polling in the idle loop will be implemented shortly by introducing a kernel thread which does the job. Until then, the amount of CPU dedicated to polling will never exceed (100-user_frac). The equivalent (actually, better) code for -stable is at http://info.iet.unipi.it/~luigi/polling/ and also supports polling in the idle loop. NOTE to Alpha developers: There is really nothing in this code that is i386-specific. If you move the 2 lines supporting the new option from sys/conf/{files,options}.i386 to sys/conf/{files,options} I am pretty sure that this should work on the Alpha as well, just that I do not have a suitable test box to try it. If someone feels like trying it, I would appreciate it. NOTE to other developers: sure some things could be done better, and as always I am open to constructive criticism, which a few of you have already given and I greatly appreciated. However, before proposing radical architectural changes, please take some time to possibly try out this code, or at the very least read the comments in kern_poll.c, especially re. the reason why I am using a soft netisr and cannot (I believe) replace it with a simple timeout. Quick description of files touched by this commit: sys/conf/files.i386 new file kern/kern_poll.c sys/conf/options.i386 new option sys/i386/i386/trap.c poll in trap (disabled by default) sys/kern/kern_clock.c initialization and hardclock hooks. sys/kern/kern_intr.c minor swi_net changes sys/kern/kern_poll.c the bulk of the code. sys/net/if.h new flag sys/net/if_var.h declaration for functions used in device drivers. sys/net/netisr.h NETISR_POLL sys/dev/fxp/if_fxp.c sys/dev/fxp/if_fxpvar.h sys/pci/if_dc.c sys/pci/if_dcreg.h sys/pci/if_sis.c sys/pci/if_sisreg.h device driver modifications
2001-12-14 17:56:12 +00:00
sis_txeof(sc);
Bring in the first chunk of altq driver modifications. This covers the following drivers: bfe(4), em(4), fxp(4), lnc(4), tun(4), de(4) rl(4), sis(4) and xl(4) More patches are pending on: http://peoples.freebsd.org/~mlaier/ Please take a look and tell me if "your" driver is missing, so I can fix this. Tested-by: many No-objection: -current, -net
2004-07-02 12:16:02 +00:00
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
Make a locked and unlocked variant of sis_start()
2005-01-05 10:04:45 +00:00
sis_startl(ifp);
Device Polling code for -current. Non-SMP, i386-only, no polling in the idle loop at the moment. To use this code you must compile a kernel with options DEVICE_POLLING and at runtime enable polling with sysctl kern.polling.enable=1 The percentage of CPU reserved to userland can be set with sysctl kern.polling.user_frac=NN (default is 50) while the remainder is used by polling device drivers and netisr's. These are the only two variables that you should need to touch. There are a few more parameters in kern.polling but the default values are adequate for all purposes. See the code in kern_poll.c for more details on them. Polling in the idle loop will be implemented shortly by introducing a kernel thread which does the job. Until then, the amount of CPU dedicated to polling will never exceed (100-user_frac). The equivalent (actually, better) code for -stable is at http://info.iet.unipi.it/~luigi/polling/ and also supports polling in the idle loop. NOTE to Alpha developers: There is really nothing in this code that is i386-specific. If you move the 2 lines supporting the new option from sys/conf/{files,options}.i386 to sys/conf/{files,options} I am pretty sure that this should work on the Alpha as well, just that I do not have a suitable test box to try it. If someone feels like trying it, I would appreciate it. NOTE to other developers: sure some things could be done better, and as always I am open to constructive criticism, which a few of you have already given and I greatly appreciated. However, before proposing radical architectural changes, please take some time to possibly try out this code, or at the very least read the comments in kern_poll.c, especially re. the reason why I am using a soft netisr and cannot (I believe) replace it with a simple timeout. Quick description of files touched by this commit: sys/conf/files.i386 new file kern/kern_poll.c sys/conf/options.i386 new option sys/i386/i386/trap.c poll in trap (disabled by default) sys/kern/kern_clock.c initialization and hardclock hooks. sys/kern/kern_intr.c minor swi_net changes sys/kern/kern_poll.c the bulk of the code. sys/net/if.h new flag sys/net/if_var.h declaration for functions used in device drivers. sys/net/netisr.h NETISR_POLL sys/dev/fxp/if_fxp.c sys/dev/fxp/if_fxpvar.h sys/pci/if_dc.c sys/pci/if_dcreg.h sys/pci/if_sis.c sys/pci/if_sisreg.h device driver modifications
2001-12-14 17:56:12 +00:00
if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
s/u_intXX_t/uintXX_t/g
2010-09-01 19:53:15 +00:00
uint32_t status;
Device Polling code for -current. Non-SMP, i386-only, no polling in the idle loop at the moment. To use this code you must compile a kernel with options DEVICE_POLLING and at runtime enable polling with sysctl kern.polling.enable=1 The percentage of CPU reserved to userland can be set with sysctl kern.polling.user_frac=NN (default is 50) while the remainder is used by polling device drivers and netisr's. These are the only two variables that you should need to touch. There are a few more parameters in kern.polling but the default values are adequate for all purposes. See the code in kern_poll.c for more details on them. Polling in the idle loop will be implemented shortly by introducing a kernel thread which does the job. Until then, the amount of CPU dedicated to polling will never exceed (100-user_frac). The equivalent (actually, better) code for -stable is at http://info.iet.unipi.it/~luigi/polling/ and also supports polling in the idle loop. NOTE to Alpha developers: There is really nothing in this code that is i386-specific. If you move the 2 lines supporting the new option from sys/conf/{files,options}.i386 to sys/conf/{files,options} I am pretty sure that this should work on the Alpha as well, just that I do not have a suitable test box to try it. If someone feels like trying it, I would appreciate it. NOTE to other developers: sure some things could be done better, and as always I am open to constructive criticism, which a few of you have already given and I greatly appreciated. However, before proposing radical architectural changes, please take some time to possibly try out this code, or at the very least read the comments in kern_poll.c, especially re. the reason why I am using a soft netisr and cannot (I believe) replace it with a simple timeout. Quick description of files touched by this commit: sys/conf/files.i386 new file kern/kern_poll.c sys/conf/options.i386 new option sys/i386/i386/trap.c poll in trap (disabled by default) sys/kern/kern_clock.c initialization and hardclock hooks. sys/kern/kern_intr.c minor swi_net changes sys/kern/kern_poll.c the bulk of the code. sys/net/if.h new flag sys/net/if_var.h declaration for functions used in device drivers. sys/net/netisr.h NETISR_POLL sys/dev/fxp/if_fxp.c sys/dev/fxp/if_fxpvar.h sys/pci/if_dc.c sys/pci/if_dcreg.h sys/pci/if_sis.c sys/pci/if_sisreg.h device driver modifications
2001-12-14 17:56:12 +00:00
/* Reading the ISR register clears all interrupts. */
status = CSR_READ_4(sc, SIS_ISR);
if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW))
Mechanically convert to if_inc_counter().
2014-09-18 20:09:35 +00:00
if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
Device Polling code for -current. Non-SMP, i386-only, no polling in the idle loop at the moment. To use this code you must compile a kernel with options DEVICE_POLLING and at runtime enable polling with sysctl kern.polling.enable=1 The percentage of CPU reserved to userland can be set with sysctl kern.polling.user_frac=NN (default is 50) while the remainder is used by polling device drivers and netisr's. These are the only two variables that you should need to touch. There are a few more parameters in kern.polling but the default values are adequate for all purposes. See the code in kern_poll.c for more details on them. Polling in the idle loop will be implemented shortly by introducing a kernel thread which does the job. Until then, the amount of CPU dedicated to polling will never exceed (100-user_frac). The equivalent (actually, better) code for -stable is at http://info.iet.unipi.it/~luigi/polling/ and also supports polling in the idle loop. NOTE to Alpha developers: There is really nothing in this code that is i386-specific. If you move the 2 lines supporting the new option from sys/conf/{files,options}.i386 to sys/conf/{files,options} I am pretty sure that this should work on the Alpha as well, just that I do not have a suitable test box to try it. If someone feels like trying it, I would appreciate it. NOTE to other developers: sure some things could be done better, and as always I am open to constructive criticism, which a few of you have already given and I greatly appreciated. However, before proposing radical architectural changes, please take some time to possibly try out this code, or at the very least read the comments in kern_poll.c, especially re. the reason why I am using a soft netisr and cannot (I believe) replace it with a simple timeout. Quick description of files touched by this commit: sys/conf/files.i386 new file kern/kern_poll.c sys/conf/options.i386 new option sys/i386/i386/trap.c poll in trap (disabled by default) sys/kern/kern_clock.c initialization and hardclock hooks. sys/kern/kern_intr.c minor swi_net changes sys/kern/kern_poll.c the bulk of the code. sys/net/if.h new flag sys/net/if_var.h declaration for functions used in device drivers. sys/net/netisr.h NETISR_POLL sys/dev/fxp/if_fxp.c sys/dev/fxp/if_fxpvar.h sys/pci/if_dc.c sys/pci/if_dcreg.h sys/pci/if_sis.c sys/pci/if_sisreg.h device driver modifications
2001-12-14 17:56:12 +00:00
if (status & (SIS_ISR_RX_IDLE))
SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
if (status & SIS_ISR_SYSERR) {
Avoid controller reinitialization which could be triggered by dhclient(8) or alias addresses are added. PR: kern/87506
2010-09-01 22:16:25 +00:00
ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
Add locked/unlocked variants of sis_init()
2005-01-05 10:11:37 +00:00
sis_initl(sc);
Device Polling code for -current. Non-SMP, i386-only, no polling in the idle loop at the moment. To use this code you must compile a kernel with options DEVICE_POLLING and at runtime enable polling with sysctl kern.polling.enable=1 The percentage of CPU reserved to userland can be set with sysctl kern.polling.user_frac=NN (default is 50) while the remainder is used by polling device drivers and netisr's. These are the only two variables that you should need to touch. There are a few more parameters in kern.polling but the default values are adequate for all purposes. See the code in kern_poll.c for more details on them. Polling in the idle loop will be implemented shortly by introducing a kernel thread which does the job. Until then, the amount of CPU dedicated to polling will never exceed (100-user_frac). The equivalent (actually, better) code for -stable is at http://info.iet.unipi.it/~luigi/polling/ and also supports polling in the idle loop. NOTE to Alpha developers: There is really nothing in this code that is i386-specific. If you move the 2 lines supporting the new option from sys/conf/{files,options}.i386 to sys/conf/{files,options} I am pretty sure that this should work on the Alpha as well, just that I do not have a suitable test box to try it. If someone feels like trying it, I would appreciate it. NOTE to other developers: sure some things could be done better, and as always I am open to constructive criticism, which a few of you have already given and I greatly appreciated. However, before proposing radical architectural changes, please take some time to possibly try out this code, or at the very least read the comments in kern_poll.c, especially re. the reason why I am using a soft netisr and cannot (I believe) replace it with a simple timeout. Quick description of files touched by this commit: sys/conf/files.i386 new file kern/kern_poll.c sys/conf/options.i386 new option sys/i386/i386/trap.c poll in trap (disabled by default) sys/kern/kern_clock.c initialization and hardclock hooks. sys/kern/kern_intr.c minor swi_net changes sys/kern/kern_poll.c the bulk of the code. sys/net/if.h new flag sys/net/if_var.h declaration for functions used in device drivers. sys/net/netisr.h NETISR_POLL sys/dev/fxp/if_fxp.c sys/dev/fxp/if_fxpvar.h sys/pci/if_dc.c sys/pci/if_dcreg.h sys/pci/if_sis.c sys/pci/if_sisreg.h device driver modifications
2001-12-14 17:56:12 +00:00
}
}
Big polling(4) cleanup. o Axe poll in trap. o Axe IFF_POLLING flag from if_flags. o Rework revision 1.21 (Giant removal), in such a way that poll_mtx is not dropped during call to polling handler. This fixes problem with idle polling. o Make registration and deregistration from polling in a functional way, insted of next tick/interrupt. o Obsolete kern.polling.enable. Polling is turned on/off with ifconfig. Detailed kern_poll.c changes: - Remove polling handler flags, introduced in 1.21. The are not needed now. - Forget and do not check if_flags, if_capenable and if_drv_flags. - Call all registered polling handlers unconditionally. - Do not drop poll_mtx, when entering polling handlers. - In ether_poll() NET_LOCK_GIANT prior to locking poll_mtx. - In netisr_poll() axe the block, where polling code asks drivers to unregister. - In netisr_poll() and ether_poll() do polling always, if any handlers are present. - In ether_poll_[de]register() remove a lot of error hiding code. Assert that arguments are correct, instead. - In ether_poll_[de]register() use standard return values in case of error or success. - Introduce poll_switch() that is a sysctl handler for kern.polling.enable. poll_switch() goes through interface list and enabled/disables polling. A message that kern.polling.enable is deprecated is printed. Detailed driver changes: - On attach driver announces IFCAP_POLLING in if_capabilities, but not in if_capenable. - On detach driver calls ether_poll_deregister() if polling is enabled. - In polling handler driver obtains its lock and checks IFF_DRV_RUNNING flag. If there is no, then unlocks and returns. - In ioctl handler driver checks for IFCAP_POLLING flag requested to be set or cleared. Driver first calls ether_poll_[de]register(), then obtains driver lock and [dis/en]ables interrupts. - In interrupt handler driver checks IFCAP_POLLING flag in if_capenable. If present, then returns.This is important to protect from spurious interrupts. Reviewed by: ru, sam, jhb
2005-10-01 18:56:19 +00:00
Device Polling code for -current. Non-SMP, i386-only, no polling in the idle loop at the moment. To use this code you must compile a kernel with options DEVICE_POLLING and at runtime enable polling with sysctl kern.polling.enable=1 The percentage of CPU reserved to userland can be set with sysctl kern.polling.user_frac=NN (default is 50) while the remainder is used by polling device drivers and netisr's. These are the only two variables that you should need to touch. There are a few more parameters in kern.polling but the default values are adequate for all purposes. See the code in kern_poll.c for more details on them. Polling in the idle loop will be implemented shortly by introducing a kernel thread which does the job. Until then, the amount of CPU dedicated to polling will never exceed (100-user_frac). The equivalent (actually, better) code for -stable is at http://info.iet.unipi.it/~luigi/polling/ and also supports polling in the idle loop. NOTE to Alpha developers: There is really nothing in this code that is i386-specific. If you move the 2 lines supporting the new option from sys/conf/{files,options}.i386 to sys/conf/{files,options} I am pretty sure that this should work on the Alpha as well, just that I do not have a suitable test box to try it. If someone feels like trying it, I would appreciate it. NOTE to other developers: sure some things could be done better, and as always I am open to constructive criticism, which a few of you have already given and I greatly appreciated. However, before proposing radical architectural changes, please take some time to possibly try out this code, or at the very least read the comments in kern_poll.c, especially re. the reason why I am using a soft netisr and cannot (I believe) replace it with a simple timeout. Quick description of files touched by this commit: sys/conf/files.i386 new file kern/kern_poll.c sys/conf/options.i386 new option sys/i386/i386/trap.c poll in trap (disabled by default) sys/kern/kern_clock.c initialization and hardclock hooks. sys/kern/kern_intr.c minor swi_net changes sys/kern/kern_poll.c the bulk of the code. sys/net/if.h new flag sys/net/if_var.h declaration for functions used in device drivers. sys/net/netisr.h NETISR_POLL sys/dev/fxp/if_fxp.c sys/dev/fxp/if_fxpvar.h sys/pci/if_dc.c sys/pci/if_dcreg.h sys/pci/if_sis.c sys/pci/if_sisreg.h device driver modifications
2001-12-14 17:56:12 +00:00
SIS_UNLOCK(sc);
When user_frac in the polling subsystem is low it is going to busy the CPU for too long period than necessary. Additively, interfaces are kept polled (in the tick) even if no more packets are available. In order to avoid such situations a new generic mechanism can be implemented in proactive way, keeping track of the time spent on any packet and fragmenting the time for any tick, stopping the processing as soon as possible. In order to implement such mechanism, the polling handler needs to change, returning the number of packets processed. While the intended logic is not part of this patch, the polling KPI is broken by this commit, adding an int return value and the new flag IFCAP_POLLING_NOCOUNT (which will signal that the return value is meaningless for the installed handler and checking should be skipped). Bump __FreeBSD_version in order to signal such situation. Reviewed by: emaste Sponsored by: Sandvine Incorporated
2009-05-30 15:14:44 +00:00
return (rx_npkts);
Device Polling code for -current. Non-SMP, i386-only, no polling in the idle loop at the moment. To use this code you must compile a kernel with options DEVICE_POLLING and at runtime enable polling with sysctl kern.polling.enable=1 The percentage of CPU reserved to userland can be set with sysctl kern.polling.user_frac=NN (default is 50) while the remainder is used by polling device drivers and netisr's. These are the only two variables that you should need to touch. There are a few more parameters in kern.polling but the default values are adequate for all purposes. See the code in kern_poll.c for more details on them. Polling in the idle loop will be implemented shortly by introducing a kernel thread which does the job. Until then, the amount of CPU dedicated to polling will never exceed (100-user_frac). The equivalent (actually, better) code for -stable is at http://info.iet.unipi.it/~luigi/polling/ and also supports polling in the idle loop. NOTE to Alpha developers: There is really nothing in this code that is i386-specific. If you move the 2 lines supporting the new option from sys/conf/{files,options}.i386 to sys/conf/{files,options} I am pretty sure that this should work on the Alpha as well, just that I do not have a suitable test box to try it. If someone feels like trying it, I would appreciate it. NOTE to other developers: sure some things could be done better, and as always I am open to constructive criticism, which a few of you have already given and I greatly appreciated. However, before proposing radical architectural changes, please take some time to possibly try out this code, or at the very least read the comments in kern_poll.c, especially re. the reason why I am using a soft netisr and cannot (I believe) replace it with a simple timeout. Quick description of files touched by this commit: sys/conf/files.i386 new file kern/kern_poll.c sys/conf/options.i386 new option sys/i386/i386/trap.c poll in trap (disabled by default) sys/kern/kern_clock.c initialization and hardclock hooks. sys/kern/kern_intr.c minor swi_net changes sys/kern/kern_poll.c the bulk of the code. sys/net/if.h new flag sys/net/if_var.h declaration for functions used in device drivers. sys/net/netisr.h NETISR_POLL sys/dev/fxp/if_fxp.c sys/dev/fxp/if_fxpvar.h sys/pci/if_dc.c sys/pci/if_dcreg.h sys/pci/if_sis.c sys/pci/if_sisreg.h device driver modifications
2001-12-14 17:56:12 +00:00
}
#endif /* DEVICE_POLLING */
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static void
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
sis_intr(void *arg)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
struct sis_softc *sc;
struct ifnet *ifp;
s/u_intXX_t/uintXX_t/g
2010-09-01 19:53:15 +00:00
uint32_t status;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
sc = arg;
Stop embedding struct ifnet at the top of driver softcs. Instead the struct ifnet or the layer 2 common structure it was embedded in have been replaced with a struct ifnet pointer to be filled by a call to the new function, if_alloc(). The layer 2 common structure is also allocated via if_alloc() based on the interface type. It is hung off the new struct ifnet member, if_l2com. This change removes the size of these structures from the kernel ABI and will allow us to better manage them as interfaces come and go. Other changes of note: - Struct arpcom is no longer referenced in normal interface code. Instead the Ethernet address is accessed via the IFP2ENADDR() macro. To enforce this ac_enaddr has been renamed to _ac_enaddr. - The second argument to ether_ifattach is now always the mac address from driver private storage rather than sometimes being ac_enaddr. Reviewed by: sobomax, sam
2005-06-10 16:49:24 +00:00
ifp = sc->sis_ifp;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Fix a bug in the driver -- under load, the receive unit could become idle and the driver would not detect the event, requiring userland to cycle the interface to bring it up again. The fix consists in adding SIS_IMR_RX_IDLE to the interrupt mask and add a command in sis_intr() to restart the receiver when this happens. While at it, make the test of status bits more efficient.
2001-11-27 16:29:11 +00:00
SIS_LOCK(sc);
Device Polling code for -current. Non-SMP, i386-only, no polling in the idle loop at the moment. To use this code you must compile a kernel with options DEVICE_POLLING and at runtime enable polling with sysctl kern.polling.enable=1 The percentage of CPU reserved to userland can be set with sysctl kern.polling.user_frac=NN (default is 50) while the remainder is used by polling device drivers and netisr's. These are the only two variables that you should need to touch. There are a few more parameters in kern.polling but the default values are adequate for all purposes. See the code in kern_poll.c for more details on them. Polling in the idle loop will be implemented shortly by introducing a kernel thread which does the job. Until then, the amount of CPU dedicated to polling will never exceed (100-user_frac). The equivalent (actually, better) code for -stable is at http://info.iet.unipi.it/~luigi/polling/ and also supports polling in the idle loop. NOTE to Alpha developers: There is really nothing in this code that is i386-specific. If you move the 2 lines supporting the new option from sys/conf/{files,options}.i386 to sys/conf/{files,options} I am pretty sure that this should work on the Alpha as well, just that I do not have a suitable test box to try it. If someone feels like trying it, I would appreciate it. NOTE to other developers: sure some things could be done better, and as always I am open to constructive criticism, which a few of you have already given and I greatly appreciated. However, before proposing radical architectural changes, please take some time to possibly try out this code, or at the very least read the comments in kern_poll.c, especially re. the reason why I am using a soft netisr and cannot (I believe) replace it with a simple timeout. Quick description of files touched by this commit: sys/conf/files.i386 new file kern/kern_poll.c sys/conf/options.i386 new option sys/i386/i386/trap.c poll in trap (disabled by default) sys/kern/kern_clock.c initialization and hardclock hooks. sys/kern/kern_intr.c minor swi_net changes sys/kern/kern_poll.c the bulk of the code. sys/net/if.h new flag sys/net/if_var.h declaration for functions used in device drivers. sys/net/netisr.h NETISR_POLL sys/dev/fxp/if_fxp.c sys/dev/fxp/if_fxpvar.h sys/pci/if_dc.c sys/pci/if_dcreg.h sys/pci/if_sis.c sys/pci/if_sisreg.h device driver modifications
2001-12-14 17:56:12 +00:00
#ifdef DEVICE_POLLING
Big polling(4) cleanup. o Axe poll in trap. o Axe IFF_POLLING flag from if_flags. o Rework revision 1.21 (Giant removal), in such a way that poll_mtx is not dropped during call to polling handler. This fixes problem with idle polling. o Make registration and deregistration from polling in a functional way, insted of next tick/interrupt. o Obsolete kern.polling.enable. Polling is turned on/off with ifconfig. Detailed kern_poll.c changes: - Remove polling handler flags, introduced in 1.21. The are not needed now. - Forget and do not check if_flags, if_capenable and if_drv_flags. - Call all registered polling handlers unconditionally. - Do not drop poll_mtx, when entering polling handlers. - In ether_poll() NET_LOCK_GIANT prior to locking poll_mtx. - In netisr_poll() axe the block, where polling code asks drivers to unregister. - In netisr_poll() and ether_poll() do polling always, if any handlers are present. - In ether_poll_[de]register() remove a lot of error hiding code. Assert that arguments are correct, instead. - In ether_poll_[de]register() use standard return values in case of error or success. - Introduce poll_switch() that is a sysctl handler for kern.polling.enable. poll_switch() goes through interface list and enabled/disables polling. A message that kern.polling.enable is deprecated is printed. Detailed driver changes: - On attach driver announces IFCAP_POLLING in if_capabilities, but not in if_capenable. - On detach driver calls ether_poll_deregister() if polling is enabled. - In polling handler driver obtains its lock and checks IFF_DRV_RUNNING flag. If there is no, then unlocks and returns. - In ioctl handler driver checks for IFCAP_POLLING flag requested to be set or cleared. Driver first calls ether_poll_[de]register(), then obtains driver lock and [dis/en]ables interrupts. - In interrupt handler driver checks IFCAP_POLLING flag in if_capenable. If present, then returns.This is important to protect from spurious interrupts. Reviewed by: ru, sam, jhb
2005-10-01 18:56:19 +00:00
if (ifp->if_capenable & IFCAP_POLLING) {
SIS_UNLOCK(sc);
return;
Device Polling code for -current. Non-SMP, i386-only, no polling in the idle loop at the moment. To use this code you must compile a kernel with options DEVICE_POLLING and at runtime enable polling with sysctl kern.polling.enable=1 The percentage of CPU reserved to userland can be set with sysctl kern.polling.user_frac=NN (default is 50) while the remainder is used by polling device drivers and netisr's. These are the only two variables that you should need to touch. There are a few more parameters in kern.polling but the default values are adequate for all purposes. See the code in kern_poll.c for more details on them. Polling in the idle loop will be implemented shortly by introducing a kernel thread which does the job. Until then, the amount of CPU dedicated to polling will never exceed (100-user_frac). The equivalent (actually, better) code for -stable is at http://info.iet.unipi.it/~luigi/polling/ and also supports polling in the idle loop. NOTE to Alpha developers: There is really nothing in this code that is i386-specific. If you move the 2 lines supporting the new option from sys/conf/{files,options}.i386 to sys/conf/{files,options} I am pretty sure that this should work on the Alpha as well, just that I do not have a suitable test box to try it. If someone feels like trying it, I would appreciate it. NOTE to other developers: sure some things could be done better, and as always I am open to constructive criticism, which a few of you have already given and I greatly appreciated. However, before proposing radical architectural changes, please take some time to possibly try out this code, or at the very least read the comments in kern_poll.c, especially re. the reason why I am using a soft netisr and cannot (I believe) replace it with a simple timeout. Quick description of files touched by this commit: sys/conf/files.i386 new file kern/kern_poll.c sys/conf/options.i386 new option sys/i386/i386/trap.c poll in trap (disabled by default) sys/kern/kern_clock.c initialization and hardclock hooks. sys/kern/kern_intr.c minor swi_net changes sys/kern/kern_poll.c the bulk of the code. sys/net/if.h new flag sys/net/if_var.h declaration for functions used in device drivers. sys/net/netisr.h NETISR_POLL sys/dev/fxp/if_fxp.c sys/dev/fxp/if_fxpvar.h sys/pci/if_dc.c sys/pci/if_dcreg.h sys/pci/if_sis.c sys/pci/if_sisreg.h device driver modifications
2001-12-14 17:56:12 +00:00
}
Big polling(4) cleanup. o Axe poll in trap. o Axe IFF_POLLING flag from if_flags. o Rework revision 1.21 (Giant removal), in such a way that poll_mtx is not dropped during call to polling handler. This fixes problem with idle polling. o Make registration and deregistration from polling in a functional way, insted of next tick/interrupt. o Obsolete kern.polling.enable. Polling is turned on/off with ifconfig. Detailed kern_poll.c changes: - Remove polling handler flags, introduced in 1.21. The are not needed now. - Forget and do not check if_flags, if_capenable and if_drv_flags. - Call all registered polling handlers unconditionally. - Do not drop poll_mtx, when entering polling handlers. - In ether_poll() NET_LOCK_GIANT prior to locking poll_mtx. - In netisr_poll() axe the block, where polling code asks drivers to unregister. - In netisr_poll() and ether_poll() do polling always, if any handlers are present. - In ether_poll_[de]register() remove a lot of error hiding code. Assert that arguments are correct, instead. - In ether_poll_[de]register() use standard return values in case of error or success. - Introduce poll_switch() that is a sysctl handler for kern.polling.enable. poll_switch() goes through interface list and enabled/disables polling. A message that kern.polling.enable is deprecated is printed. Detailed driver changes: - On attach driver announces IFCAP_POLLING in if_capabilities, but not in if_capenable. - On detach driver calls ether_poll_deregister() if polling is enabled. - In polling handler driver obtains its lock and checks IFF_DRV_RUNNING flag. If there is no, then unlocks and returns. - In ioctl handler driver checks for IFCAP_POLLING flag requested to be set or cleared. Driver first calls ether_poll_[de]register(), then obtains driver lock and [dis/en]ables interrupts. - In interrupt handler driver checks IFCAP_POLLING flag in if_capenable. If present, then returns.This is important to protect from spurious interrupts. Reviewed by: ru, sam, jhb
2005-10-01 18:56:19 +00:00
#endif
Device Polling code for -current. Non-SMP, i386-only, no polling in the idle loop at the moment. To use this code you must compile a kernel with options DEVICE_POLLING and at runtime enable polling with sysctl kern.polling.enable=1 The percentage of CPU reserved to userland can be set with sysctl kern.polling.user_frac=NN (default is 50) while the remainder is used by polling device drivers and netisr's. These are the only two variables that you should need to touch. There are a few more parameters in kern.polling but the default values are adequate for all purposes. See the code in kern_poll.c for more details on them. Polling in the idle loop will be implemented shortly by introducing a kernel thread which does the job. Until then, the amount of CPU dedicated to polling will never exceed (100-user_frac). The equivalent (actually, better) code for -stable is at http://info.iet.unipi.it/~luigi/polling/ and also supports polling in the idle loop. NOTE to Alpha developers: There is really nothing in this code that is i386-specific. If you move the 2 lines supporting the new option from sys/conf/{files,options}.i386 to sys/conf/{files,options} I am pretty sure that this should work on the Alpha as well, just that I do not have a suitable test box to try it. If someone feels like trying it, I would appreciate it. NOTE to other developers: sure some things could be done better, and as always I am open to constructive criticism, which a few of you have already given and I greatly appreciated. However, before proposing radical architectural changes, please take some time to possibly try out this code, or at the very least read the comments in kern_poll.c, especially re. the reason why I am using a soft netisr and cannot (I believe) replace it with a simple timeout. Quick description of files touched by this commit: sys/conf/files.i386 new file kern/kern_poll.c sys/conf/options.i386 new option sys/i386/i386/trap.c poll in trap (disabled by default) sys/kern/kern_clock.c initialization and hardclock hooks. sys/kern/kern_intr.c minor swi_net changes sys/kern/kern_poll.c the bulk of the code. sys/net/if.h new flag sys/net/if_var.h declaration for functions used in device drivers. sys/net/netisr.h NETISR_POLL sys/dev/fxp/if_fxp.c sys/dev/fxp/if_fxpvar.h sys/pci/if_dc.c sys/pci/if_dcreg.h sys/pci/if_sis.c sys/pci/if_sisreg.h device driver modifications
2001-12-14 17:56:12 +00:00
Overhaul link state change handling. Previously sis(4) blindly configured TX/RX MACs before getting a valid link. After that, when link state change callback is called, it called device initialization again to reconfigure TX/RX MACs depending on resolved link state. This hack created several bad side effects and it required more hacks to not collide with sis_tick callback as well as disabling switching to currently selected media in device initialization. Also it seems sis(4) was used to be a template driver for long time so other drivers which was modeled after sis(4) also should be changed. TX/RX MACs are now reconfigured after getting a valid link. Fix for short cable error is also applied after getting a link because it's only valid when the resolved speed is 100Mbps. While I'm here slightly reorganize interrupt handler such that sis(4) always read SIS_ISR register to see whether the interrupt is ours or not. This change removes another hack and make it possible to nuke sis_stopped variable in softc.
2010-09-01 21:42:19 +00:00
/* Reading the ISR register clears all interrupts. */
status = CSR_READ_4(sc, SIS_ISR);
if ((status & SIS_INTRS) == 0) {
/* Not ours. */
SIS_UNLOCK(sc);
Correct handling of shared interrupt in sis_intr(). r212116 incorrectly released a drver lock for shared interrupt case such that it caused panic. While I'm here check whether driver is still running before serving TX/RX handler. Reported by: Jerahmy Pocott < QUAKENET1 <> optusnet dot com dot au > Tested by: Jerahmy Pocott < QUAKENET1 <> optusnet dot com dot au > MFC after: 3 days
2010-10-20 00:19:25 +00:00
return;
Overhaul link state change handling. Previously sis(4) blindly configured TX/RX MACs before getting a valid link. After that, when link state change callback is called, it called device initialization again to reconfigure TX/RX MACs depending on resolved link state. This hack created several bad side effects and it required more hacks to not collide with sis_tick callback as well as disabling switching to currently selected media in device initialization. Also it seems sis(4) was used to be a template driver for long time so other drivers which was modeled after sis(4) also should be changed. TX/RX MACs are now reconfigured after getting a valid link. Fix for short cable error is also applied after getting a link because it's only valid when the resolved speed is 100Mbps. While I'm here slightly reorganize interrupt handler such that sis(4) always read SIS_ISR register to see whether the interrupt is ours or not. This change removes another hack and make it possible to nuke sis_stopped variable in softc.
2010-09-01 21:42:19 +00:00
}
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
/* Disable interrupts. */
CSR_WRITE_4(sc, SIS_IER, 0);
Overhaul link state change handling. Previously sis(4) blindly configured TX/RX MACs before getting a valid link. After that, when link state change callback is called, it called device initialization again to reconfigure TX/RX MACs depending on resolved link state. This hack created several bad side effects and it required more hacks to not collide with sis_tick callback as well as disabling switching to currently selected media in device initialization. Also it seems sis(4) was used to be a template driver for long time so other drivers which was modeled after sis(4) also should be changed. TX/RX MACs are now reconfigured after getting a valid link. Fix for short cable error is also applied after getting a link because it's only valid when the resolved speed is 100Mbps. While I'm here slightly reorganize interrupt handler such that sis(4) always read SIS_ISR register to see whether the interrupt is ours or not. This change removes another hack and make it possible to nuke sis_stopped variable in softc.
2010-09-01 21:42:19 +00:00
for (;(status & SIS_INTRS) != 0;) {
Correct handling of shared interrupt in sis_intr(). r212116 incorrectly released a drver lock for shared interrupt case such that it caused panic. While I'm here check whether driver is still running before serving TX/RX handler. Reported by: Jerahmy Pocott < QUAKENET1 <> optusnet dot com dot au > Tested by: Jerahmy Pocott < QUAKENET1 <> optusnet dot com dot au > MFC after: 3 days
2010-10-20 00:19:25 +00:00
if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
break;
Fix a bug in the driver -- under load, the receive unit could become idle and the driver would not detect the event, requiring userland to cycle the interface to bring it up again. The fix consists in adding SIS_IMR_RX_IDLE to the interrupt mask and add a command in sis_intr() to restart the receiver when this happens. While at it, make the test of status bits more efficient.
2001-11-27 16:29:11 +00:00
if (status &
(SIS_ISR_TX_DESC_OK | SIS_ISR_TX_ERR |
Remove leading and trailing white spaces. No functional changes.
2010-09-01 18:28:08 +00:00
SIS_ISR_TX_OK | SIS_ISR_TX_IDLE) )
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
sis_txeof(sc);
Receving VLAN oversized frames raise SIS_ISR_RX_ERR interrupt, so make sis_rxeof() handle that too. Previously it used to receive the frame and reset controller. PR: kern/131414
2009-02-13 02:08:20 +00:00
if (status & (SIS_ISR_RX_DESC_OK | SIS_ISR_RX_OK |
SIS_ISR_RX_ERR | SIS_ISR_RX_IDLE))
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
sis_rxeof(sc);
Receving VLAN oversized frames raise SIS_ISR_RX_ERR interrupt, so make sis_rxeof() handle that too. Previously it used to receive the frame and reset controller. PR: kern/131414
2009-02-13 02:08:20 +00:00
if (status & SIS_ISR_RX_OFLOW)
Mechanically convert to if_inc_counter().
2014-09-18 20:09:35 +00:00
if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
Fix a bug in the driver -- under load, the receive unit could become idle and the driver would not detect the event, requiring userland to cycle the interface to bring it up again. The fix consists in adding SIS_IMR_RX_IDLE to the interrupt mask and add a command in sis_intr() to restart the receiver when this happens. While at it, make the test of status bits more efficient.
2001-11-27 16:29:11 +00:00
if (status & (SIS_ISR_RX_IDLE))
SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
if (status & SIS_ISR_SYSERR) {
Avoid controller reinitialization which could be triggered by dhclient(8) or alias addresses are added. PR: kern/87506
2010-09-01 22:16:25 +00:00
ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
Add locked/unlocked variants of sis_init()
2005-01-05 10:11:37 +00:00
sis_initl(sc);
Overhaul link state change handling. Previously sis(4) blindly configured TX/RX MACs before getting a valid link. After that, when link state change callback is called, it called device initialization again to reconfigure TX/RX MACs depending on resolved link state. This hack created several bad side effects and it required more hacks to not collide with sis_tick callback as well as disabling switching to currently selected media in device initialization. Also it seems sis(4) was used to be a template driver for long time so other drivers which was modeled after sis(4) also should be changed. TX/RX MACs are now reconfigured after getting a valid link. Fix for short cable error is also applied after getting a link because it's only valid when the resolved speed is 100Mbps. While I'm here slightly reorganize interrupt handler such that sis(4) always read SIS_ISR register to see whether the interrupt is ours or not. This change removes another hack and make it possible to nuke sis_stopped variable in softc.
2010-09-01 21:42:19 +00:00
SIS_UNLOCK(sc);
return;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
Overhaul link state change handling. Previously sis(4) blindly configured TX/RX MACs before getting a valid link. After that, when link state change callback is called, it called device initialization again to reconfigure TX/RX MACs depending on resolved link state. This hack created several bad side effects and it required more hacks to not collide with sis_tick callback as well as disabling switching to currently selected media in device initialization. Also it seems sis(4) was used to be a template driver for long time so other drivers which was modeled after sis(4) also should be changed. TX/RX MACs are now reconfigured after getting a valid link. Fix for short cable error is also applied after getting a link because it's only valid when the resolved speed is 100Mbps. While I'm here slightly reorganize interrupt handler such that sis(4) always read SIS_ISR register to see whether the interrupt is ours or not. This change removes another hack and make it possible to nuke sis_stopped variable in softc.
2010-09-01 21:42:19 +00:00
status = CSR_READ_4(sc, SIS_ISR);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
Correct handling of shared interrupt in sis_intr(). r212116 incorrectly released a drver lock for shared interrupt case such that it caused panic. While I'm here check whether driver is still running before serving TX/RX handler. Reported by: Jerahmy Pocott < QUAKENET1 <> optusnet dot com dot au > Tested by: Jerahmy Pocott < QUAKENET1 <> optusnet dot com dot au > MFC after: 3 days
2010-10-20 00:19:25 +00:00
if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
/* Re-enable interrupts. */
CSR_WRITE_4(sc, SIS_IER, 1);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Correct handling of shared interrupt in sis_intr(). r212116 incorrectly released a drver lock for shared interrupt case such that it caused panic. While I'm here check whether driver is still running before serving TX/RX handler. Reported by: Jerahmy Pocott < QUAKENET1 <> optusnet dot com dot au > Tested by: Jerahmy Pocott < QUAKENET1 <> optusnet dot com dot au > MFC after: 3 days
2010-10-20 00:19:25 +00:00
if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
sis_startl(ifp);
}
First round of converting network drivers from spls to mutexes. This takes care of all the 10/100 and gigE PCI drivers that I've done. Next will be the wireless drivers, then the USB ones. I may pick up some stragglers along the way. I'm sort of playing this by ear: if anyone spots any places where I've screwed up horribly, please let me know.
2000-10-13 17:54:19 +00:00
If we get an interrupt and the interface is down, return before we grab the lock. This should help a tiny bit on machines where unused if_sis interfaces share IRQ.
2005-01-07 00:01:43 +00:00
SIS_UNLOCK(sc);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
/*
* Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
* pointers to the fragment pointers.
*/
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static int
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
sis_encap(struct sis_softc *sc, struct mbuf **m_head)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
struct mbuf *m;
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
struct sis_txdesc *txd;
struct sis_desc *f;
bus_dma_segment_t segs[SIS_MAXTXSEGS];
bus_dmamap_t map;
int error, i, frag, nsegs, prod;
Unlike most other controllers, NS DP83815/DP83816 controllers seem to pad with 0xFF when it encounter short frames. According to RFC 1042 the pad bytes should be 0x00. Because manual padding consumes extra CPU cycles, introduce a new tunable which controls the padding behavior. Turning this tunable on will have driver pad manually but it's disabled by default. Users can enable software padding by setting the following tunable to non-zero value. dev.sis.%d.manual_pad="1" PR: kern/35422 (patch not used)
2010-09-02 18:10:11 +00:00
int padlen;
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
prod = sc->sis_tx_prod;
txd = &sc->sis_txdesc[prod];
Unlike most other controllers, NS DP83815/DP83816 controllers seem to pad with 0xFF when it encounter short frames. According to RFC 1042 the pad bytes should be 0x00. Because manual padding consumes extra CPU cycles, introduce a new tunable which controls the padding behavior. Turning this tunable on will have driver pad manually but it's disabled by default. Users can enable software padding by setting the following tunable to non-zero value. dev.sis.%d.manual_pad="1" PR: kern/35422 (patch not used)
2010-09-02 18:10:11 +00:00
if ((sc->sis_flags & SIS_FLAG_MANUAL_PAD) != 0 &&
(*m_head)->m_pkthdr.len < SIS_MIN_FRAMELEN) {
m = *m_head;
padlen = SIS_MIN_FRAMELEN - m->m_pkthdr.len;
if (M_WRITABLE(m) == 0) {
/* Get a writable copy. */
Mechanically substitute flags from historic mbuf allocator with malloc(9) flags in sys/dev.
2012-12-04 09:32:43 +00:00
m = m_dup(*m_head, M_NOWAIT);
Unlike most other controllers, NS DP83815/DP83816 controllers seem to pad with 0xFF when it encounter short frames. According to RFC 1042 the pad bytes should be 0x00. Because manual padding consumes extra CPU cycles, introduce a new tunable which controls the padding behavior. Turning this tunable on will have driver pad manually but it's disabled by default. Users can enable software padding by setting the following tunable to non-zero value. dev.sis.%d.manual_pad="1" PR: kern/35422 (patch not used)
2010-09-02 18:10:11 +00:00
m_freem(*m_head);
if (m == NULL) {
*m_head = NULL;
return (ENOBUFS);
}
*m_head = m;
}
if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) {
Mechanically substitute flags from historic mbuf allocator with malloc(9) flags in sys/dev.
2012-12-04 09:32:43 +00:00
m = m_defrag(m, M_NOWAIT);
Unlike most other controllers, NS DP83815/DP83816 controllers seem to pad with 0xFF when it encounter short frames. According to RFC 1042 the pad bytes should be 0x00. Because manual padding consumes extra CPU cycles, introduce a new tunable which controls the padding behavior. Turning this tunable on will have driver pad manually but it's disabled by default. Users can enable software padding by setting the following tunable to non-zero value. dev.sis.%d.manual_pad="1" PR: kern/35422 (patch not used)
2010-09-02 18:10:11 +00:00
if (m == NULL) {
m_freem(*m_head);
*m_head = NULL;
return (ENOBUFS);
}
}
/*
* Manually pad short frames, and zero the pad space
* to avoid leaking data.
*/
bzero(mtod(m, char *) + m->m_pkthdr.len, padlen);
m->m_pkthdr.len += padlen;
m->m_len = m->m_pkthdr.len;
*m_head = m;
}
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap,
*m_head, segs, &nsegs, 0);
if (error == EFBIG) {
Mechanically substitute flags from historic mbuf allocator with malloc(9) flags in sys/dev.
2012-12-04 09:32:43 +00:00
m = m_collapse(*m_head, M_NOWAIT, SIS_MAXTXSEGS);
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
if (m == NULL) {
m_freem(*m_head);
*m_head = NULL;
return (ENOBUFS);
}
*m_head = m;
error = bus_dmamap_load_mbuf_sg(sc->sis_tx_tag, txd->tx_dmamap,
*m_head, segs, &nsegs, 0);
if (error != 0) {
m_freem(*m_head);
*m_head = NULL;
return (error);
}
} else if (error != 0)
return (error);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
/* Check for descriptor overruns. */
if (sc->sis_tx_cnt + nsegs > SIS_TX_LIST_CNT - 1) {
bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
Have sis_encap use m_defrag if: 1. The chain passed in is > 31 fragments long or 2. The chain will not fit in the remaining descriptors without defragmentation. This is slightly less clear than other network drivers because the sis chips share one descriptor list for all packets, it seems. Before this change, a > 127 fragment chain would get stuck in the IFQUEUE permanently, bringing all network traffic to a halt. MFC after: 2 weeks
2003-03-29 17:50:37 +00:00
return (ENOBUFS);
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
}
Have sis_encap use m_defrag if: 1. The chain passed in is > 31 fragments long or 2. The chain will not fit in the remaining descriptors without defragmentation. This is slightly less clear than other network drivers because the sis chips share one descriptor list for all packets, it seems. Before this change, a > 127 fragment chain would get stuck in the IFQUEUE permanently, bringing all network traffic to a halt. MFC after: 2 weeks
2003-03-29 17:50:37 +00:00
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap, BUS_DMASYNC_PREWRITE);
Have sis_encap use m_defrag if: 1. The chain passed in is > 31 fragments long or 2. The chain will not fit in the remaining descriptors without defragmentation. This is slightly less clear than other network drivers because the sis chips share one descriptor list for all packets, it seems. Before this change, a > 127 fragment chain would get stuck in the IFQUEUE permanently, bringing all network traffic to a halt. MFC after: 2 weeks
2003-03-29 17:50:37 +00:00
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
frag = prod;
for (i = 0; i < nsegs; i++) {
f = &sc->sis_tx_list[prod];
if (i == 0)
f->sis_cmdsts = htole32(segs[i].ds_len |
SIS_CMDSTS_MORE);
else
f->sis_cmdsts = htole32(segs[i].ds_len |
SIS_CMDSTS_OWN | SIS_CMDSTS_MORE);
f->sis_ptr = htole32(SIS_ADDR_LO(segs[i].ds_addr));
SIS_INC(prod, SIS_TX_LIST_CNT);
sc->sis_tx_cnt++;
Have sis_encap use m_defrag if: 1. The chain passed in is > 31 fragments long or 2. The chain will not fit in the remaining descriptors without defragmentation. This is slightly less clear than other network drivers because the sis chips share one descriptor list for all packets, it seems. Before this change, a > 127 fragment chain would get stuck in the IFQUEUE permanently, bringing all network traffic to a halt. MFC after: 2 weeks
2003-03-29 17:50:37 +00:00
}
Remove leading and trailing white spaces. No functional changes.
2010-09-01 18:28:08 +00:00
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
/* Update producer index. */
sc->sis_tx_prod = prod;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
/* Remove MORE flag on the last descriptor. */
prod = (prod - 1) & (SIS_TX_LIST_CNT - 1);
f = &sc->sis_tx_list[prod];
f->sis_cmdsts &= ~htole32(SIS_CMDSTS_MORE);
/* Lastly transfer ownership of packet to the controller. */
f = &sc->sis_tx_list[frag];
f->sis_cmdsts |= htole32(SIS_CMDSTS_OWN);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
/* Swap the last and the first dmamaps. */
map = txd->tx_dmamap;
Fix stupid error in r212109 which didn't swap DMA maps. This caused IOMMU panic on sparc64 under high TX load.
2010-09-02 00:44:05 +00:00
txd->tx_dmamap = sc->sis_txdesc[prod].tx_dmamap;
sc->sis_txdesc[prod].tx_dmamap = map;
Fix another bug introduced in r212109. We should unload DMA maps only after sending the last fragment of a frame so the mbuf pointer also should be stored in the last descriptor index.
2010-09-03 18:00:17 +00:00
sc->sis_txdesc[prod].tx_m = *m_head;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
style(9) - space after keywords.
2010-09-01 18:39:35 +00:00
return (0);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static void
Make sis_initl() take a typed argument. Expect caller to lock before calling sis_stop() Various style stuff.
2005-01-05 10:26:12 +00:00
sis_start(struct ifnet *ifp)
Make a locked and unlocked variant of sis_start()
2005-01-05 10:04:45 +00:00
{
struct sis_softc *sc;
sc = ifp->if_softc;
SIS_LOCK(sc);
sis_startl(ifp);
SIS_UNLOCK(sc);
}
static void
sis_startl(struct ifnet *ifp)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
struct sis_softc *sc;
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
struct mbuf *m_head;
int queued;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
sc = ifp->if_softc;
Make a locked and unlocked variant of sis_start()
2005-01-05 10:04:45 +00:00
SIS_LOCK_ASSERT(sc);
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
Unlike most other controllers, NS DP83815/DP83816 controllers seem to pad with 0xFF when it encounter short frames. According to RFC 1042 the pad bytes should be 0x00. Because manual padding consumes extra CPU cycles, introduce a new tunable which controls the padding behavior. Turning this tunable on will have driver pad manually but it's disabled by default. Users can enable software padding by setting the following tunable to non-zero value. dev.sis.%d.manual_pad="1" PR: kern/35422 (patch not used)
2010-09-02 18:10:11 +00:00
IFF_DRV_RUNNING || (sc->sis_flags & SIS_FLAG_LINK) == 0)
Fix up the sis driver, largely to improve the NatSemi DP83815 support: - Modify the driver to poll the link state and positively set the MAC to full or half duplex as needed. Previously, it was possible for the MAC to remain in half duplex even though the PHY had negotiated full duplex with its link partner, which would result in bursty performance. - Program some of the NatSemi's registers as specified by the datasheet. The manual says these are necessary for "optimum perofrmance," though a couple of them are marked as reserved in the register map. *shrug* - Select the TX DMA burst size correctly for 10 and 100mbps modes. Previously I was using 64 bytes in both modes, which worked in 100mbps mode, but resulting in spotty performance in 10mbps. 32 bytes works much better; without this change, the natsemi chip yields piss poor performance at 10mbps. With these fixes, the NatSemi chip finally performs to my satisfaction. I should be merging the support for this controller into -stable shortly. Phew.
2000-08-22 23:26:51 +00:00
return;
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
sc->sis_tx_cnt < SIS_TX_LIST_CNT - 4;) {
Bring in the first chunk of altq driver modifications. This covers the following drivers: bfe(4), em(4), fxp(4), lnc(4), tun(4), de(4) rl(4), sis(4) and xl(4) More patches are pending on: http://peoples.freebsd.org/~mlaier/ Please take a look and tell me if "your" driver is missing, so I can fix this. Tested-by: many No-objection: -current, -net
2004-07-02 12:16:02 +00:00
IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
if (m_head == NULL)
break;
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
if (sis_encap(sc, &m_head) != 0) {
if (m_head == NULL)
break;
Bring in the first chunk of altq driver modifications. This covers the following drivers: bfe(4), em(4), fxp(4), lnc(4), tun(4), de(4) rl(4), sis(4) and xl(4) More patches are pending on: http://peoples.freebsd.org/~mlaier/ Please take a look and tell me if "your" driver is missing, so I can fix this. Tested-by: many No-objection: -current, -net
2004-07-02 12:16:02 +00:00
IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
Propagate rename of IFF_OACTIVE and IFF_RUNNING to IFF_DRV_OACTIVE and IFF_DRV_RUNNING, as well as the move from ifnet.if_flags to ifnet.if_drv_flags. Device drivers are now responsible for synchronizing access to these flags, as they are in if_drv_flags. This helps prevent races between the network stack and device driver in maintaining the interface flags field. Many __FreeBSD__ and __FreeBSD_version checks maintained and continued; some less so. Reviewed by: pjd, bz MFC after: 7 days
2005-08-09 10:20:02 +00:00
ifp->if_drv_flags |= IFF_DRV_OACTIVE;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
break;
}
Fix sis, bfe and ndis in the same way dc was fixed: Do not tell the hardware to send when there were no packets enqueued. Found and reviewed by: green MFC after: 1 days
2004-10-08 16:14:42 +00:00
queued++;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
/*
* If there's a BPF listener, bounce a copy of this frame
* to him.
*/
o track either_ifattach/ether_ifdetach API changes o use if_input for input packet processing o don't strip the Ethernet header for input packets o use BPF_* macros bpf tapping o call ether_ioctl to handle default ioctl case o track vlan changes Reviewed by: many Approved by: re
2002-11-14 23:49:09 +00:00
BPF_MTAP(ifp, m_head);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
Fix sis, bfe and ndis in the same way dc was fixed: Do not tell the hardware to send when there were no packets enqueued. Found and reviewed by: green MFC after: 1 days
2004-10-08 16:14:42 +00:00
if (queued) {
/* Transmit */
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
bus_dmamap_sync(sc->sis_tx_list_tag, sc->sis_tx_list_map,
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
Fix sis, bfe and ndis in the same way dc was fixed: Do not tell the hardware to send when there were no packets enqueued. Found and reviewed by: green MFC after: 1 days
2004-10-08 16:14:42 +00:00
SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_ENABLE);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Fix sis, bfe and ndis in the same way dc was fixed: Do not tell the hardware to send when there were no packets enqueued. Found and reviewed by: green MFC after: 1 days
2004-10-08 16:14:42 +00:00
/*
* Set a timeout in case the chip goes out to lunch.
*/
Convert sis(4) to use its own watchdog procedure. Submitted by: Florian C. Smeets <flo kasimir com>
2007-02-24 14:27:36 +00:00
sc->sis_watchdog_timer = 5;
Fix sis, bfe and ndis in the same way dc was fixed: Do not tell the hardware to send when there were no packets enqueued. Found and reviewed by: green MFC after: 1 days
2004-10-08 16:14:42 +00:00
}
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static void
Add locked/unlocked variants of sis_init()
2005-01-05 10:11:37 +00:00
sis_init(void *xsc)
{
struct sis_softc *sc = xsc;
SIS_LOCK(sc);
Make sis_initl() take a typed argument. Expect caller to lock before calling sis_stop() Various style stuff.
2005-01-05 10:26:12 +00:00
sis_initl(sc);
Add locked/unlocked variants of sis_init()
2005-01-05 10:11:37 +00:00
SIS_UNLOCK(sc);
}
static void
Make sis_initl() take a typed argument. Expect caller to lock before calling sis_stop() Various style stuff.
2005-01-05 10:26:12 +00:00
sis_initl(struct sis_softc *sc)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
Stop embedding struct ifnet at the top of driver softcs. Instead the struct ifnet or the layer 2 common structure it was embedded in have been replaced with a struct ifnet pointer to be filled by a call to the new function, if_alloc(). The layer 2 common structure is also allocated via if_alloc() based on the interface type. It is hung off the new struct ifnet member, if_l2com. This change removes the size of these structures from the kernel ABI and will allow us to better manage them as interfaces come and go. Other changes of note: - Struct arpcom is no longer referenced in normal interface code. Instead the Ethernet address is accessed via the IFP2ENADDR() macro. To enforce this ac_enaddr has been renamed to _ac_enaddr. - The second argument to ether_ifattach is now always the mac address from driver private storage rather than sometimes being ac_enaddr. Reviewed by: sobomax, sam
2005-06-10 16:49:24 +00:00
struct ifnet *ifp = sc->sis_ifp;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
struct mii_data *mii;
Fix the last endianness issue on handling station address which prevented driver from working on big-endian machines. Also rewrite station address programming to make it work on strict-alignment architectures. With this change, sis(4) now works on sparc64 and performance number looks good even though sis(4) have to apply fixup code to align received frames on 2 bytes boundary on sparc64.
2010-09-02 17:51:41 +00:00
uint8_t *eaddr;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Add locked/unlocked variants of sis_init()
2005-01-05 10:11:37 +00:00
SIS_LOCK_ASSERT(sc);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Avoid controller reinitialization which could be triggered by dhclient(8) or alias addresses are added. PR: kern/87506
2010-09-01 22:16:25 +00:00
if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
return;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
/*
* Cancel pending I/O and free all RX/TX buffers.
*/
sis_stop(sc);
Move sis_reset() to sis_initl(). This ensures driver starts with known good state of controller.
2010-09-01 22:50:11 +00:00
/*
* Reset the chip to a known state.
*/
sis_reset(sc);
Examine and record the Silicon Revision Register on NS parts. We can't update the device description in attach (why not ?), so we device_print() what we find. Conditionalize the short cable fix on this being older than rev 16A. Call device_printf() when we apply short cable fix. Include interrupt hold-off setting for rev 16+ under "#ifdef notyet" The device_printf()'s will go under bootverbose once the various issues have settled a bit.
2003-09-03 07:40:04 +00:00
#ifdef notyet
if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr >= NS_SRR_16A) {
/*
* Configure 400usec of interrupt holdoff. This is based
* on emperical tests on a Soekris 4801.
*/
CSR_WRITE_4(sc, NS_IHR, 0x100 | 4);
}
#endif
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
mii = device_get_softc(sc->sis_miibus);
/* Set MAC address */
Fix the last endianness issue on handling station address which prevented driver from working on big-endian machines. Also rewrite station address programming to make it work on strict-alignment architectures. With this change, sis(4) now works on sparc64 and performance number looks good even though sis(4) have to apply fixup code to align received frames on 2 bytes boundary on sparc64.
2010-09-02 17:51:41 +00:00
eaddr = IF_LLADDR(sc->sis_ifp);
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
if (sc->sis_type == SIS_TYPE_83815) {
CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR0);
Fix the last endianness issue on handling station address which prevented driver from working on big-endian machines. Also rewrite station address programming to make it work on strict-alignment architectures. With this change, sis(4) now works on sparc64 and performance number looks good even though sis(4) have to apply fixup code to align received frames on 2 bytes boundary on sparc64.
2010-09-02 17:51:41 +00:00
CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8);
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR1);
Fix the last endianness issue on handling station address which prevented driver from working on big-endian machines. Also rewrite station address programming to make it work on strict-alignment architectures. With this change, sis(4) now works on sparc64 and performance number looks good even though sis(4) have to apply fixup code to align received frames on 2 bytes boundary on sparc64.
2010-09-02 17:51:41 +00:00
CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8);
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
CSR_WRITE_4(sc, SIS_RXFILT_CTL, NS_FILTADDR_PAR2);
Fix the last endianness issue on handling station address which prevented driver from working on big-endian machines. Also rewrite station address programming to make it work on strict-alignment architectures. With this change, sis(4) now works on sparc64 and performance number looks good even though sis(4) have to apply fixup code to align received frames on 2 bytes boundary on sparc64.
2010-09-02 17:51:41 +00:00
CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8);
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
} else {
CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR0);
Fix the last endianness issue on handling station address which prevented driver from working on big-endian machines. Also rewrite station address programming to make it work on strict-alignment architectures. With this change, sis(4) now works on sparc64 and performance number looks good even though sis(4) have to apply fixup code to align received frames on 2 bytes boundary on sparc64.
2010-09-02 17:51:41 +00:00
CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[0] | eaddr[1] << 8);
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR1);
Fix the last endianness issue on handling station address which prevented driver from working on big-endian machines. Also rewrite station address programming to make it work on strict-alignment architectures. With this change, sis(4) now works on sparc64 and performance number looks good even though sis(4) have to apply fixup code to align received frames on 2 bytes boundary on sparc64.
2010-09-02 17:51:41 +00:00
CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[2] | eaddr[3] << 8);
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
CSR_WRITE_4(sc, SIS_RXFILT_CTL, SIS_FILTADDR_PAR2);
Fix the last endianness issue on handling station address which prevented driver from working on big-endian machines. Also rewrite station address programming to make it work on strict-alignment architectures. With this change, sis(4) now works on sparc64 and performance number looks good even though sis(4) have to apply fixup code to align received frames on 2 bytes boundary on sparc64.
2010-09-02 17:51:41 +00:00
CSR_WRITE_4(sc, SIS_RXFILT_DATA, eaddr[4] | eaddr[5] << 8);
Add support for the National Semiconductor DP83815 fast ethernet controller chip. This chip is currently being used on the NetGear FA312-TX adapter, which I guess is a replacement for the FA310-TX (PNIC-based). I added support for this chip by modifying the sis driver since the SiS 900 and the NS DP83815 have almost the same programming interface (the RX filter programming and PHY access methods are different, but the general configuration, DMA scheme and register layout are identical). I would have had this done a lot sooner, but getting the damn MAC address out of the EEPROM proved to be more complicated than expected.
2000-07-06 06:02:04 +00:00
}
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Rewrite the rx/tx ring initialization to use pointers instead of arrays.
2005-01-06 23:31:41 +00:00
/* Init circular TX/RX lists. */
if (sis_ring_init(sc) != 0) {
Consistently use if_printf() only in interface methods: if_start, if_ioctl, if_watchdog, etc, or in functions that are used by these methods only. In all other cases use device_printf(). This also fixes several panics, when if_printf() is called before softc->ifp was initialized. Submitted by: Alex Lyashkov <umka sevcity.net>
2006-09-15 10:40:54 +00:00
device_printf(sc->sis_dev,
Small fixes to sis(4): - Remove sis_unit and use device_printf() and if_printf() instead. - Use callout_init_mtx() for the callout. - Remove spls. - Fix locking for ifmedia to happen in the ifmedia handlers rather than in sis_ioctl(). - Log an error message if we fail to allocate any resources. Perform cleanup if we fail to allocate any resources so that we don't leave a mutex hanging around. Tested by: Jason Tsai jason dot tsai at newcyberian dot com (1-4) MFC after: 3 days
2005-09-26 18:42:27 +00:00
"initialization failed: no memory for rx buffers\n");
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
sis_stop(sc);
return;
}
r119712 introduced SIS_TYPE_83816 but it was not actually set in driver such that checking against the type was always false. To detect NS DP83816, driver should have checked silicon revision register for NS controllers. While here, remove SIS_TYPE_83816 to not make the similar mistake again. Reported by: Brad Smith ( brad@openbsd )
2013-03-18 04:46:17 +00:00
if (sc->sis_type == SIS_TYPE_83815) {
Unlike most other controllers, NS DP83815/DP83816 controllers seem to pad with 0xFF when it encounter short frames. According to RFC 1042 the pad bytes should be 0x00. Because manual padding consumes extra CPU cycles, introduce a new tunable which controls the padding behavior. Turning this tunable on will have driver pad manually but it's disabled by default. Users can enable software padding by setting the following tunable to non-zero value. dev.sis.%d.manual_pad="1" PR: kern/35422 (patch not used)
2010-09-02 18:10:11 +00:00
if (sc->sis_manual_pad != 0)
sc->sis_flags |= SIS_FLAG_MANUAL_PAD;
else
sc->sis_flags &= ~SIS_FLAG_MANUAL_PAD;
}
Attempt to get the short cable fix to work better on the if_sis: Only do short-cable on revisions that need it. Move generic initialization before short-cable fix, in order to not clobber short cable fix register setting.
2003-12-12 10:15:39 +00:00
/*
Nail the short cable problem the exact way National says it should be.
2005-01-06 23:49:26 +00:00
* Short Cable Receive Errors (MP21.E)
* also: Page 78 of the DP83815 data sheet (september 2002 version)
Attempt to get the short cable fix to work better on the if_sis: Only do short-cable on revisions that need it. Move generic initialization before short-cable fix, in order to not clobber short cable fix register setting.
2003-12-12 10:15:39 +00:00
* recommends the following register settings "for optimum
Set all of the "optimum performance" PHY registers for the 15D parts as well as the 15C since it seems to be required in practice. The Linux natsemi.c driver mostly does this as well. PR: kern/112179 Submitted by: Mark Willson mark - hydrus org uk MFC after: 1 week
2008-07-30 17:28:49 +00:00
* performance." for rev 15C. Set this also for 15D parts as
* they require it in practice.
Attempt to get the short cable fix to work better on the if_sis: Only do short-cable on revisions that need it. Move generic initialization before short-cable fix, in order to not clobber short cable fix register setting.
2003-12-12 10:15:39 +00:00
*/
Nail the short cable problem the exact way National says it should be.
2005-01-06 23:49:26 +00:00
if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) {
Attempt to get the short cable fix to work better on the if_sis: Only do short-cable on revisions that need it. Move generic initialization before short-cable fix, in order to not clobber short cable fix register setting.
2003-12-12 10:15:39 +00:00
CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
Set all of the "optimum performance" PHY registers for the 15D parts as well as the 15C since it seems to be required in practice. The Linux natsemi.c driver mostly does this as well. PR: kern/112179 Submitted by: Mark Willson mark - hydrus org uk MFC after: 1 week
2008-07-30 17:28:49 +00:00
/* set val for c2 */
CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
/* load/kill c2 */
CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
/* rais SD off, from 4 to c */
CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
Attempt to get the short cable fix to work better on the if_sis: Only do short-cable on revisions that need it. Move generic initialization before short-cable fix, in order to not clobber short cable fix register setting.
2003-12-12 10:15:39 +00:00
CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
}
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
sis_rxfilter(sc);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
/*
* Load the address of the RX and TX lists.
*/
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
CSR_WRITE_4(sc, SIS_RX_LISTPTR, SIS_ADDR_LO(sc->sis_rx_paddr));
CSR_WRITE_4(sc, SIS_TX_LISTPTR, SIS_ADDR_LO(sc->sis_tx_paddr));
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of the PCI bus. When this bit is set, the Max DMA Burst Size for TX/RX DMA should be no larger than 64 bytes. Reviewed by: luoqi Obtained from: (idea from linux driver source) MFC after: 2 weeks
2003-01-10 08:12:20 +00:00
/* SIS_CFG_EDB_MASTER_EN indicates the EDB bus is used instead of
* the PCI bus. When this bit is set, the Max DMA Burst Size
* for TX/RX DMA should be no larger than 16 double words.
*/
if (CSR_READ_4(sc, SIS_CFG) & SIS_CFG_EDB_MASTER_EN) {
CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG64);
} else {
CSR_WRITE_4(sc, SIS_RX_CFG, SIS_RXCFG256);
}
Add VLAN support. MFC after: 7 days
2001-12-05 09:34:28 +00:00
/* Accept Long Packets for VLAN support */
SIS_SETBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_JABBER);
Overhaul link state change handling. Previously sis(4) blindly configured TX/RX MACs before getting a valid link. After that, when link state change callback is called, it called device initialization again to reconfigure TX/RX MACs depending on resolved link state. This hack created several bad side effects and it required more hacks to not collide with sis_tick callback as well as disabling switching to currently selected media in device initialization. Also it seems sis(4) was used to be a template driver for long time so other drivers which was modeled after sis(4) also should be changed. TX/RX MACs are now reconfigured after getting a valid link. Fix for short cable error is also applied after getting a link because it's only valid when the resolved speed is 100Mbps. While I'm here slightly reorganize interrupt handler such that sis(4) always read SIS_ISR register to see whether the interrupt is ours or not. This change removes another hack and make it possible to nuke sis_stopped variable in softc.
2010-09-01 21:42:19 +00:00
/*
* Assume 100Mbps link, actual MAC configuration is done
* after getting a valid link.
*/
CSR_WRITE_4(sc, SIS_TX_CFG, SIS_TXCFG_100);
"short cable" fix for DP8315 Derived from: netbsd and tech note at soekris web site MFC after: 1 week
2003-08-19 16:57:00 +00:00
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
/*
* Enable interrupts.
*/
CSR_WRITE_4(sc, SIS_IMR, SIS_INTRS);
Device Polling code for -current. Non-SMP, i386-only, no polling in the idle loop at the moment. To use this code you must compile a kernel with options DEVICE_POLLING and at runtime enable polling with sysctl kern.polling.enable=1 The percentage of CPU reserved to userland can be set with sysctl kern.polling.user_frac=NN (default is 50) while the remainder is used by polling device drivers and netisr's. These are the only two variables that you should need to touch. There are a few more parameters in kern.polling but the default values are adequate for all purposes. See the code in kern_poll.c for more details on them. Polling in the idle loop will be implemented shortly by introducing a kernel thread which does the job. Until then, the amount of CPU dedicated to polling will never exceed (100-user_frac). The equivalent (actually, better) code for -stable is at http://info.iet.unipi.it/~luigi/polling/ and also supports polling in the idle loop. NOTE to Alpha developers: There is really nothing in this code that is i386-specific. If you move the 2 lines supporting the new option from sys/conf/{files,options}.i386 to sys/conf/{files,options} I am pretty sure that this should work on the Alpha as well, just that I do not have a suitable test box to try it. If someone feels like trying it, I would appreciate it. NOTE to other developers: sure some things could be done better, and as always I am open to constructive criticism, which a few of you have already given and I greatly appreciated. However, before proposing radical architectural changes, please take some time to possibly try out this code, or at the very least read the comments in kern_poll.c, especially re. the reason why I am using a soft netisr and cannot (I believe) replace it with a simple timeout. Quick description of files touched by this commit: sys/conf/files.i386 new file kern/kern_poll.c sys/conf/options.i386 new option sys/i386/i386/trap.c poll in trap (disabled by default) sys/kern/kern_clock.c initialization and hardclock hooks. sys/kern/kern_intr.c minor swi_net changes sys/kern/kern_poll.c the bulk of the code. sys/net/if.h new flag sys/net/if_var.h declaration for functions used in device drivers. sys/net/netisr.h NETISR_POLL sys/dev/fxp/if_fxp.c sys/dev/fxp/if_fxpvar.h sys/pci/if_dc.c sys/pci/if_dcreg.h sys/pci/if_sis.c sys/pci/if_sisreg.h device driver modifications
2001-12-14 17:56:12 +00:00
#ifdef DEVICE_POLLING
/*
* ... only enable interrupts if we are not polling, make sure
* they are off otherwise.
*/
Big polling(4) cleanup. o Axe poll in trap. o Axe IFF_POLLING flag from if_flags. o Rework revision 1.21 (Giant removal), in such a way that poll_mtx is not dropped during call to polling handler. This fixes problem with idle polling. o Make registration and deregistration from polling in a functional way, insted of next tick/interrupt. o Obsolete kern.polling.enable. Polling is turned on/off with ifconfig. Detailed kern_poll.c changes: - Remove polling handler flags, introduced in 1.21. The are not needed now. - Forget and do not check if_flags, if_capenable and if_drv_flags. - Call all registered polling handlers unconditionally. - Do not drop poll_mtx, when entering polling handlers. - In ether_poll() NET_LOCK_GIANT prior to locking poll_mtx. - In netisr_poll() axe the block, where polling code asks drivers to unregister. - In netisr_poll() and ether_poll() do polling always, if any handlers are present. - In ether_poll_[de]register() remove a lot of error hiding code. Assert that arguments are correct, instead. - In ether_poll_[de]register() use standard return values in case of error or success. - Introduce poll_switch() that is a sysctl handler for kern.polling.enable. poll_switch() goes through interface list and enabled/disables polling. A message that kern.polling.enable is deprecated is printed. Detailed driver changes: - On attach driver announces IFCAP_POLLING in if_capabilities, but not in if_capenable. - On detach driver calls ether_poll_deregister() if polling is enabled. - In polling handler driver obtains its lock and checks IFF_DRV_RUNNING flag. If there is no, then unlocks and returns. - In ioctl handler driver checks for IFCAP_POLLING flag requested to be set or cleared. Driver first calls ether_poll_[de]register(), then obtains driver lock and [dis/en]ables interrupts. - In interrupt handler driver checks IFCAP_POLLING flag in if_capenable. If present, then returns.This is important to protect from spurious interrupts. Reviewed by: ru, sam, jhb
2005-10-01 18:56:19 +00:00
if (ifp->if_capenable & IFCAP_POLLING)
Device Polling code for -current. Non-SMP, i386-only, no polling in the idle loop at the moment. To use this code you must compile a kernel with options DEVICE_POLLING and at runtime enable polling with sysctl kern.polling.enable=1 The percentage of CPU reserved to userland can be set with sysctl kern.polling.user_frac=NN (default is 50) while the remainder is used by polling device drivers and netisr's. These are the only two variables that you should need to touch. There are a few more parameters in kern.polling but the default values are adequate for all purposes. See the code in kern_poll.c for more details on them. Polling in the idle loop will be implemented shortly by introducing a kernel thread which does the job. Until then, the amount of CPU dedicated to polling will never exceed (100-user_frac). The equivalent (actually, better) code for -stable is at http://info.iet.unipi.it/~luigi/polling/ and also supports polling in the idle loop. NOTE to Alpha developers: There is really nothing in this code that is i386-specific. If you move the 2 lines supporting the new option from sys/conf/{files,options}.i386 to sys/conf/{files,options} I am pretty sure that this should work on the Alpha as well, just that I do not have a suitable test box to try it. If someone feels like trying it, I would appreciate it. NOTE to other developers: sure some things could be done better, and as always I am open to constructive criticism, which a few of you have already given and I greatly appreciated. However, before proposing radical architectural changes, please take some time to possibly try out this code, or at the very least read the comments in kern_poll.c, especially re. the reason why I am using a soft netisr and cannot (I believe) replace it with a simple timeout. Quick description of files touched by this commit: sys/conf/files.i386 new file kern/kern_poll.c sys/conf/options.i386 new option sys/i386/i386/trap.c poll in trap (disabled by default) sys/kern/kern_clock.c initialization and hardclock hooks. sys/kern/kern_intr.c minor swi_net changes sys/kern/kern_poll.c the bulk of the code. sys/net/if.h new flag sys/net/if_var.h declaration for functions used in device drivers. sys/net/netisr.h NETISR_POLL sys/dev/fxp/if_fxp.c sys/dev/fxp/if_fxpvar.h sys/pci/if_dc.c sys/pci/if_dcreg.h sys/pci/if_sis.c sys/pci/if_sisreg.h device driver modifications
2001-12-14 17:56:12 +00:00
CSR_WRITE_4(sc, SIS_IER, 0);
else
Big polling(4) cleanup. o Axe poll in trap. o Axe IFF_POLLING flag from if_flags. o Rework revision 1.21 (Giant removal), in such a way that poll_mtx is not dropped during call to polling handler. This fixes problem with idle polling. o Make registration and deregistration from polling in a functional way, insted of next tick/interrupt. o Obsolete kern.polling.enable. Polling is turned on/off with ifconfig. Detailed kern_poll.c changes: - Remove polling handler flags, introduced in 1.21. The are not needed now. - Forget and do not check if_flags, if_capenable and if_drv_flags. - Call all registered polling handlers unconditionally. - Do not drop poll_mtx, when entering polling handlers. - In ether_poll() NET_LOCK_GIANT prior to locking poll_mtx. - In netisr_poll() axe the block, where polling code asks drivers to unregister. - In netisr_poll() and ether_poll() do polling always, if any handlers are present. - In ether_poll_[de]register() remove a lot of error hiding code. Assert that arguments are correct, instead. - In ether_poll_[de]register() use standard return values in case of error or success. - Introduce poll_switch() that is a sysctl handler for kern.polling.enable. poll_switch() goes through interface list and enabled/disables polling. A message that kern.polling.enable is deprecated is printed. Detailed driver changes: - On attach driver announces IFCAP_POLLING in if_capabilities, but not in if_capenable. - On detach driver calls ether_poll_deregister() if polling is enabled. - In polling handler driver obtains its lock and checks IFF_DRV_RUNNING flag. If there is no, then unlocks and returns. - In ioctl handler driver checks for IFCAP_POLLING flag requested to be set or cleared. Driver first calls ether_poll_[de]register(), then obtains driver lock and [dis/en]ables interrupts. - In interrupt handler driver checks IFCAP_POLLING flag in if_capenable. If present, then returns.This is important to protect from spurious interrupts. Reviewed by: ru, sam, jhb
2005-10-01 18:56:19 +00:00
#endif
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
CSR_WRITE_4(sc, SIS_IER, 1);
Overhaul link state change handling. Previously sis(4) blindly configured TX/RX MACs before getting a valid link. After that, when link state change callback is called, it called device initialization again to reconfigure TX/RX MACs depending on resolved link state. This hack created several bad side effects and it required more hacks to not collide with sis_tick callback as well as disabling switching to currently selected media in device initialization. Also it seems sis(4) was used to be a template driver for long time so other drivers which was modeled after sis(4) also should be changed. TX/RX MACs are now reconfigured after getting a valid link. Fix for short cable error is also applied after getting a link because it's only valid when the resolved speed is 100Mbps. While I'm here slightly reorganize interrupt handler such that sis(4) always read SIS_ISR register to see whether the interrupt is ours or not. This change removes another hack and make it possible to nuke sis_stopped variable in softc.
2010-09-01 21:42:19 +00:00
/* Clear MAC disable. */
SIS_CLRBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE | SIS_CSR_RX_DISABLE);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Unlike most other controllers, NS DP83815/DP83816 controllers seem to pad with 0xFF when it encounter short frames. According to RFC 1042 the pad bytes should be 0x00. Because manual padding consumes extra CPU cycles, introduce a new tunable which controls the padding behavior. Turning this tunable on will have driver pad manually but it's disabled by default. Users can enable software padding by setting the following tunable to non-zero value. dev.sis.%d.manual_pad="1" PR: kern/35422 (patch not used)
2010-09-02 18:10:11 +00:00
sc->sis_flags &= ~SIS_FLAG_LINK;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
mii_mediachg(mii);
Fix up the sis driver, largely to improve the NatSemi DP83815 support: - Modify the driver to poll the link state and positively set the MAC to full or half duplex as needed. Previously, it was possible for the MAC to remain in half duplex even though the PHY had negotiated full duplex with its link partner, which would result in bursty performance. - Program some of the NatSemi's registers as specified by the datasheet. The manual says these are necessary for "optimum perofrmance," though a couple of them are marked as reserved in the register map. *shrug* - Select the TX DMA burst size correctly for 10 and 100mbps modes. Previously I was using 64 bytes in both modes, which worked in 100mbps mode, but resulting in spotty performance in 10mbps. 32 bytes works much better; without this change, the natsemi chip yields piss poor performance at 10mbps. With these fixes, the NatSemi chip finally performs to my satisfaction. I should be merging the support for this controller into -stable shortly. Phew.
2000-08-22 23:26:51 +00:00
Propagate rename of IFF_OACTIVE and IFF_RUNNING to IFF_DRV_OACTIVE and IFF_DRV_RUNNING, as well as the move from ifnet.if_flags to ifnet.if_drv_flags. Device drivers are now responsible for synchronizing access to these flags, as they are in if_drv_flags. This helps prevent races between the network stack and device driver in maintaining the interface flags field. Many __FreeBSD__ and __FreeBSD_version checks maintained and continued; some less so. Reviewed by: pjd, bz MFC after: 7 days
2005-08-09 10:20:02 +00:00
ifp->if_drv_flags |= IFF_DRV_RUNNING;
ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Overhaul link state change handling. Previously sis(4) blindly configured TX/RX MACs before getting a valid link. After that, when link state change callback is called, it called device initialization again to reconfigure TX/RX MACs depending on resolved link state. This hack created several bad side effects and it required more hacks to not collide with sis_tick callback as well as disabling switching to currently selected media in device initialization. Also it seems sis(4) was used to be a template driver for long time so other drivers which was modeled after sis(4) also should be changed. TX/RX MACs are now reconfigured after getting a valid link. Fix for short cable error is also applied after getting a link because it's only valid when the resolved speed is 100Mbps. While I'm here slightly reorganize interrupt handler such that sis(4) always read SIS_ISR register to see whether the interrupt is ours or not. This change removes another hack and make it possible to nuke sis_stopped variable in softc.
2010-09-01 21:42:19 +00:00
callout_reset(&sc->sis_stat_ch, hz, sis_tick, sc);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
/*
* Set media options.
*/
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static int
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
sis_ifmedia_upd(struct ifnet *ifp)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
struct sis_softc *sc;
Fix up the sis driver, largely to improve the NatSemi DP83815 support: - Modify the driver to poll the link state and positively set the MAC to full or half duplex as needed. Previously, it was possible for the MAC to remain in half duplex even though the PHY had negotiated full duplex with its link partner, which would result in bursty performance. - Program some of the NatSemi's registers as specified by the datasheet. The manual says these are necessary for "optimum perofrmance," though a couple of them are marked as reserved in the register map. *shrug* - Select the TX DMA burst size correctly for 10 and 100mbps modes. Previously I was using 64 bytes in both modes, which worked in 100mbps mode, but resulting in spotty performance in 10mbps. 32 bytes works much better; without this change, the natsemi chip yields piss poor performance at 10mbps. With these fixes, the NatSemi chip finally performs to my satisfaction. I should be merging the support for this controller into -stable shortly. Phew.
2000-08-22 23:26:51 +00:00
struct mii_data *mii;
- Remove attempts to implement setting of BMCR_LOOP/MIIF_NOLOOP (reporting IFM_LOOP based on BMCR_LOOP is left in place though as it might provide useful for debugging). For most mii(4) drivers it was unclear whether the PHYs driven by them actually support loopback or not. Moreover, typically loopback mode also needs to be activated on the MAC, which none of the Ethernet drivers using mii(4) implements. Given that loopback media has no real use (and obviously hardly had a chance to actually work) besides for driver development (which just loopback mode should be sufficient for though, i.e one doesn't necessary need support for loopback media) support for it is just dropped as both NetBSD and OpenBSD already did quite some time ago. - Let mii_phy_add_media() also announce the support of IFM_NONE. - Restructure the PHY entry points to use a structure of entry points instead of discrete function pointers, and extend this to include a "reset" entry point. Make sure any PHY-specific reset routine is always used, and provide one for lxtphy(4) which disables MII interrupts (as is done for a few other PHYs we have drivers for). This includes changing NIC drivers which previously just called the generic mii_phy_reset() to now actually call the PHY-specific reset routine, which might be crucial in some cases. While at it, the redundant checks in these NIC drivers for mii->mii_instance not being zero before calling the reset routines were removed because as soon as one PHY driver attaches mii->mii_instance is incremented and we hardly can end up in their media change callbacks etc if no PHY driver has attached as mii_attach() would have failed in that case and not attach a miibus(4) instance. Consequently, NIC drivers now no longer should call mii_phy_reset() directly, so it was removed from EXPORT_SYMS. - Add a mii_phy_dev_attach() as a companion helper to mii_phy_dev_probe(). The purpose of that function is to perform the common steps to attach a PHY driver instance and to hook it up to the miibus(4) instance and to optionally also handle the probing, addition and initialization of the supported media. So all a PHY driver without any special requirements has to do in its bus attach method is to call mii_phy_dev_attach() along with PHY-specific MIIF_* flags, a pointer to its PHY functions and the add_media set to one. All PHY drivers were updated to take advantage of mii_phy_dev_attach() as appropriate. Along with these changes the capability mask was added to the mii_softc structure so PHY drivers taking advantage of mii_phy_dev_attach() but still handling media on their own do not need to fiddle with the MII attach arguments anyway. - Keep track of the PHY offset in the mii_softc structure. This is done for compatibility with NetBSD/OpenBSD. - Keep track of the PHY's OUI, model and revision in the mii_softc structure. Several PHY drivers require this information also after attaching and previously had to wrap their own softc around mii_softc. NetBSD/OpenBSD also keep track of the model and revision on their mii_softc structure. All PHY drivers were updated to take advantage as appropriate. - Convert the mebers of the MII data structure to unsigned where appropriate. This is partly inspired by NetBSD/OpenBSD. - According to IEEE 802.3-2002 the bits actually have to be reversed when mapping an OUI to the MII ID registers. All PHY drivers and miidevs where changed as necessary. Actually this now again allows to largely share miidevs with NetBSD, which fixed this problem already 9 years ago. Consequently miidevs was synced as far as possible. - Add MIIF_NOMANPAUSE and mii_phy_flowstatus() calls to drivers that weren't explicitly converted to support flow control before. It's unclear whether flow control actually works with these but typically it should and their net behavior should be more correct with these changes in place than without if the MAC driver sets MIIF_DOPAUSE. Obtained from: NetBSD (partially) Reviewed by: yongari (earlier version), silence on arch@ and net@
2011-05-03 19:51:29 +00:00
struct mii_softc *miisc;
Report result of link state change to caller. Previously it always returned success.
2010-09-01 21:44:36 +00:00
int error;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
sc = ifp->if_softc;
Small fixes to sis(4): - Remove sis_unit and use device_printf() and if_printf() instead. - Use callout_init_mtx() for the callout. - Remove spls. - Fix locking for ifmedia to happen in the ifmedia handlers rather than in sis_ioctl(). - Log an error message if we fail to allocate any resources. Perform cleanup if we fail to allocate any resources so that we don't leave a mutex hanging around. Tested by: Jason Tsai jason dot tsai at newcyberian dot com (1-4) MFC after: 3 days
2005-09-26 18:42:27 +00:00
SIS_LOCK(sc);
Fix up the sis driver, largely to improve the NatSemi DP83815 support: - Modify the driver to poll the link state and positively set the MAC to full or half duplex as needed. Previously, it was possible for the MAC to remain in half duplex even though the PHY had negotiated full duplex with its link partner, which would result in bursty performance. - Program some of the NatSemi's registers as specified by the datasheet. The manual says these are necessary for "optimum perofrmance," though a couple of them are marked as reserved in the register map. *shrug* - Select the TX DMA burst size correctly for 10 and 100mbps modes. Previously I was using 64 bytes in both modes, which worked in 100mbps mode, but resulting in spotty performance in 10mbps. 32 bytes works much better; without this change, the natsemi chip yields piss poor performance at 10mbps. With these fixes, the NatSemi chip finally performs to my satisfaction. I should be merging the support for this controller into -stable shortly. Phew.
2000-08-22 23:26:51 +00:00
mii = device_get_softc(sc->sis_miibus);
- Remove attempts to implement setting of BMCR_LOOP/MIIF_NOLOOP (reporting IFM_LOOP based on BMCR_LOOP is left in place though as it might provide useful for debugging). For most mii(4) drivers it was unclear whether the PHYs driven by them actually support loopback or not. Moreover, typically loopback mode also needs to be activated on the MAC, which none of the Ethernet drivers using mii(4) implements. Given that loopback media has no real use (and obviously hardly had a chance to actually work) besides for driver development (which just loopback mode should be sufficient for though, i.e one doesn't necessary need support for loopback media) support for it is just dropped as both NetBSD and OpenBSD already did quite some time ago. - Let mii_phy_add_media() also announce the support of IFM_NONE. - Restructure the PHY entry points to use a structure of entry points instead of discrete function pointers, and extend this to include a "reset" entry point. Make sure any PHY-specific reset routine is always used, and provide one for lxtphy(4) which disables MII interrupts (as is done for a few other PHYs we have drivers for). This includes changing NIC drivers which previously just called the generic mii_phy_reset() to now actually call the PHY-specific reset routine, which might be crucial in some cases. While at it, the redundant checks in these NIC drivers for mii->mii_instance not being zero before calling the reset routines were removed because as soon as one PHY driver attaches mii->mii_instance is incremented and we hardly can end up in their media change callbacks etc if no PHY driver has attached as mii_attach() would have failed in that case and not attach a miibus(4) instance. Consequently, NIC drivers now no longer should call mii_phy_reset() directly, so it was removed from EXPORT_SYMS. - Add a mii_phy_dev_attach() as a companion helper to mii_phy_dev_probe(). The purpose of that function is to perform the common steps to attach a PHY driver instance and to hook it up to the miibus(4) instance and to optionally also handle the probing, addition and initialization of the supported media. So all a PHY driver without any special requirements has to do in its bus attach method is to call mii_phy_dev_attach() along with PHY-specific MIIF_* flags, a pointer to its PHY functions and the add_media set to one. All PHY drivers were updated to take advantage of mii_phy_dev_attach() as appropriate. Along with these changes the capability mask was added to the mii_softc structure so PHY drivers taking advantage of mii_phy_dev_attach() but still handling media on their own do not need to fiddle with the MII attach arguments anyway. - Keep track of the PHY offset in the mii_softc structure. This is done for compatibility with NetBSD/OpenBSD. - Keep track of the PHY's OUI, model and revision in the mii_softc structure. Several PHY drivers require this information also after attaching and previously had to wrap their own softc around mii_softc. NetBSD/OpenBSD also keep track of the model and revision on their mii_softc structure. All PHY drivers were updated to take advantage as appropriate. - Convert the mebers of the MII data structure to unsigned where appropriate. This is partly inspired by NetBSD/OpenBSD. - According to IEEE 802.3-2002 the bits actually have to be reversed when mapping an OUI to the MII ID registers. All PHY drivers and miidevs where changed as necessary. Actually this now again allows to largely share miidevs with NetBSD, which fixed this problem already 9 years ago. Consequently miidevs was synced as far as possible. - Add MIIF_NOMANPAUSE and mii_phy_flowstatus() calls to drivers that weren't explicitly converted to support flow control before. It's unclear whether flow control actually works with these but typically it should and their net behavior should be more correct with these changes in place than without if the MAC driver sets MIIF_DOPAUSE. Obtained from: NetBSD (partially) Reviewed by: yongari (earlier version), silence on arch@ and net@
2011-05-03 19:51:29 +00:00
LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
PHY_RESET(miisc);
Report result of link state change to caller. Previously it always returned success.
2010-09-01 21:44:36 +00:00
error = mii_mediachg(mii);
Small fixes to sis(4): - Remove sis_unit and use device_printf() and if_printf() instead. - Use callout_init_mtx() for the callout. - Remove spls. - Fix locking for ifmedia to happen in the ifmedia handlers rather than in sis_ioctl(). - Log an error message if we fail to allocate any resources. Perform cleanup if we fail to allocate any resources so that we don't leave a mutex hanging around. Tested by: Jason Tsai jason dot tsai at newcyberian dot com (1-4) MFC after: 3 days
2005-09-26 18:42:27 +00:00
SIS_UNLOCK(sc);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Report result of link state change to caller. Previously it always returned success.
2010-09-01 21:44:36 +00:00
return (error);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
/*
* Report current media status.
*/
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static void
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
sis_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
struct sis_softc *sc;
struct mii_data *mii;
sc = ifp->if_softc;
Small fixes to sis(4): - Remove sis_unit and use device_printf() and if_printf() instead. - Use callout_init_mtx() for the callout. - Remove spls. - Fix locking for ifmedia to happen in the ifmedia handlers rather than in sis_ioctl(). - Log an error message if we fail to allocate any resources. Perform cleanup if we fail to allocate any resources so that we don't leave a mutex hanging around. Tested by: Jason Tsai jason dot tsai at newcyberian dot com (1-4) MFC after: 3 days
2005-09-26 18:42:27 +00:00
SIS_LOCK(sc);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
mii = device_get_softc(sc->sis_miibus);
mii_pollstat(mii);
ifmr->ifm_active = mii->mii_media_active;
ifmr->ifm_status = mii->mii_media_status;
Close a race where SIOCGIFMEDIA ioctl get inconsistent link status. Because driver is accessing a common MII structure in mii_pollstat(), updating user supplied structure should be done before dropping a driver lock. Reported by: Karim (fodillemlinkarimi <> gmail dot com)
2011-10-17 19:49:00 +00:00
SIS_UNLOCK(sc);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static int
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
sis_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
struct sis_softc *sc = ifp->if_softc;
struct ifreq *ifr = (struct ifreq *) data;
struct mii_data *mii;
Initial WOL support. NS DP8315 was tested but SiS900/SiS7016 was not tested. While I'm here, clean up SIOCSIFCAP handler.
2010-09-03 00:34:45 +00:00
int error = 0, mask;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
style(9) - space after keywords.
2010-09-01 18:39:35 +00:00
switch (command) {
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
case SIOCSIFFLAGS:
Small fixes to sis(4): - Remove sis_unit and use device_printf() and if_printf() instead. - Use callout_init_mtx() for the callout. - Remove spls. - Fix locking for ifmedia to happen in the ifmedia handlers rather than in sis_ioctl(). - Log an error message if we fail to allocate any resources. Perform cleanup if we fail to allocate any resources so that we don't leave a mutex hanging around. Tested by: Jason Tsai jason dot tsai at newcyberian dot com (1-4) MFC after: 3 days
2005-09-26 18:42:27 +00:00
SIS_LOCK(sc);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
if (ifp->if_flags & IFF_UP) {
Do not reinitialize controller whenever promiscuous mode or allmulti is toggled. Controller does not require reinitialization. This removes unnecessary controller reinitialization whenever tcpdump is used. While I'm here remove unnecessary variable reinitialization.
2010-09-01 22:08:23 +00:00
if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
((ifp->if_flags ^ sc->sis_if_flags) &
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
(IFF_PROMISC | IFF_ALLMULTI)) != 0)
sis_rxfilter(sc);
else
Do not reinitialize controller whenever promiscuous mode or allmulti is toggled. Controller does not require reinitialization. This removes unnecessary controller reinitialization whenever tcpdump is used. While I'm here remove unnecessary variable reinitialization.
2010-09-01 22:08:23 +00:00
sis_initl(sc);
Rework RX filter programming by providing separate handler for DP8381[56] and SiS 900/7016 controllers. After r212119, sis(4) no longer reinitializes controller if ALLMULTI/PROMISC was changed. However, RX filter handling code assumed some bits of the RX filter is programmed by driver initialization. This caused ALLMULTI/PROMISC configuration is ignored under certain conditions. Fix that issue by reprogramming all bits of RX filter register. While I'm here follow recommended RX filter programming steps recommended by National DP8381[56] data sheet(RX filter should be is disabled before programming). Reported by: Paul Schenkeveld < freebsd () psconsult dot nl > Tested by: Paul Schenkeveld < freebsd () psconsult dot nl > MFC after: 3 days
2011-01-18 17:50:14 +00:00
} else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
Align if else if properly
2005-01-05 22:28:24 +00:00
sis_stop(sc);
Do not reinitialize controller whenever promiscuous mode or allmulti is toggled. Controller does not require reinitialization. This removes unnecessary controller reinitialization whenever tcpdump is used. While I'm here remove unnecessary variable reinitialization.
2010-09-01 22:08:23 +00:00
sc->sis_if_flags = ifp->if_flags;
Small fixes to sis(4): - Remove sis_unit and use device_printf() and if_printf() instead. - Use callout_init_mtx() for the callout. - Remove spls. - Fix locking for ifmedia to happen in the ifmedia handlers rather than in sis_ioctl(). - Log an error message if we fail to allocate any resources. Perform cleanup if we fail to allocate any resources so that we don't leave a mutex hanging around. Tested by: Jason Tsai jason dot tsai at newcyberian dot com (1-4) MFC after: 3 days
2005-09-26 18:42:27 +00:00
SIS_UNLOCK(sc);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
break;
case SIOCADDMULTI:
case SIOCDELMULTI:
Convert the if_sis and if_rl drivers to use the bus_dma API instead of calling vtophys() and contigmalloc()/contigfree() directly. Hopefully, I have shaken out all of the problems with busdma on the alpha now. (Everything seems to work as expected.) Also, change the max RX DMA limit to 1024 bytes instead of "unlimited," as the latter seems not to work correctly on the alpha that I tested. (At 100Mbps, all attempts to receive frames yield RX errors.)
2001-08-15 17:38:43 +00:00
SIS_LOCK(sc);
Enable receive filter in sis_rxfilter(). While I'm here add a check for driver running state for multicast filter handling. Suggested by: brad@OpenBSD.org
2015-01-12 07:37:06 +00:00
if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
sis_rxfilter(sc);
Convert the if_sis and if_rl drivers to use the bus_dma API instead of calling vtophys() and contigmalloc()/contigfree() directly. Hopefully, I have shaken out all of the problems with busdma on the alpha now. (Everything seems to work as expected.) Also, change the max RX DMA limit to 1024 bytes instead of "unlimited," as the latter seems not to work correctly on the alpha that I tested. (At 100Mbps, all attempts to receive frames yield RX errors.)
2001-08-15 17:38:43 +00:00
SIS_UNLOCK(sc);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
break;
case SIOCGIFMEDIA:
case SIOCSIFMEDIA:
mii = device_get_softc(sc->sis_miibus);
error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
break;
Implemented per-interface polling(4) control.
2004-04-11 20:34:08 +00:00
case SIOCSIFCAP:
Initial WOL support. NS DP8315 was tested but SiS900/SiS7016 was not tested. While I'm here, clean up SIOCSIFCAP handler.
2010-09-03 00:34:45 +00:00
SIS_LOCK(sc);
mask = ifr->ifr_reqcap ^ ifp->if_capenable;
Big polling(4) cleanup. o Axe poll in trap. o Axe IFF_POLLING flag from if_flags. o Rework revision 1.21 (Giant removal), in such a way that poll_mtx is not dropped during call to polling handler. This fixes problem with idle polling. o Make registration and deregistration from polling in a functional way, insted of next tick/interrupt. o Obsolete kern.polling.enable. Polling is turned on/off with ifconfig. Detailed kern_poll.c changes: - Remove polling handler flags, introduced in 1.21. The are not needed now. - Forget and do not check if_flags, if_capenable and if_drv_flags. - Call all registered polling handlers unconditionally. - Do not drop poll_mtx, when entering polling handlers. - In ether_poll() NET_LOCK_GIANT prior to locking poll_mtx. - In netisr_poll() axe the block, where polling code asks drivers to unregister. - In netisr_poll() and ether_poll() do polling always, if any handlers are present. - In ether_poll_[de]register() remove a lot of error hiding code. Assert that arguments are correct, instead. - In ether_poll_[de]register() use standard return values in case of error or success. - Introduce poll_switch() that is a sysctl handler for kern.polling.enable. poll_switch() goes through interface list and enabled/disables polling. A message that kern.polling.enable is deprecated is printed. Detailed driver changes: - On attach driver announces IFCAP_POLLING in if_capabilities, but not in if_capenable. - On detach driver calls ether_poll_deregister() if polling is enabled. - In polling handler driver obtains its lock and checks IFF_DRV_RUNNING flag. If there is no, then unlocks and returns. - In ioctl handler driver checks for IFCAP_POLLING flag requested to be set or cleared. Driver first calls ether_poll_[de]register(), then obtains driver lock and [dis/en]ables interrupts. - In interrupt handler driver checks IFCAP_POLLING flag in if_capenable. If present, then returns.This is important to protect from spurious interrupts. Reviewed by: ru, sam, jhb
2005-10-01 18:56:19 +00:00
#ifdef DEVICE_POLLING
Initial WOL support. NS DP8315 was tested but SiS900/SiS7016 was not tested. While I'm here, clean up SIOCSIFCAP handler.
2010-09-03 00:34:45 +00:00
if ((mask & IFCAP_POLLING) != 0 &&
(IFCAP_POLLING & ifp->if_capabilities) != 0) {
ifp->if_capenable ^= IFCAP_POLLING;
if ((IFCAP_POLLING & ifp->if_capenable) != 0) {
error = ether_poll_register(sis_poll, ifp);
if (error != 0) {
SIS_UNLOCK(sc);
break;
}
/* Disable interrupts. */
CSR_WRITE_4(sc, SIS_IER, 0);
} else {
error = ether_poll_deregister(ifp);
/* Enable interrupts. */
CSR_WRITE_4(sc, SIS_IER, 1);
}
Big polling(4) cleanup. o Axe poll in trap. o Axe IFF_POLLING flag from if_flags. o Rework revision 1.21 (Giant removal), in such a way that poll_mtx is not dropped during call to polling handler. This fixes problem with idle polling. o Make registration and deregistration from polling in a functional way, insted of next tick/interrupt. o Obsolete kern.polling.enable. Polling is turned on/off with ifconfig. Detailed kern_poll.c changes: - Remove polling handler flags, introduced in 1.21. The are not needed now. - Forget and do not check if_flags, if_capenable and if_drv_flags. - Call all registered polling handlers unconditionally. - Do not drop poll_mtx, when entering polling handlers. - In ether_poll() NET_LOCK_GIANT prior to locking poll_mtx. - In netisr_poll() axe the block, where polling code asks drivers to unregister. - In netisr_poll() and ether_poll() do polling always, if any handlers are present. - In ether_poll_[de]register() remove a lot of error hiding code. Assert that arguments are correct, instead. - In ether_poll_[de]register() use standard return values in case of error or success. - Introduce poll_switch() that is a sysctl handler for kern.polling.enable. poll_switch() goes through interface list and enabled/disables polling. A message that kern.polling.enable is deprecated is printed. Detailed driver changes: - On attach driver announces IFCAP_POLLING in if_capabilities, but not in if_capenable. - On detach driver calls ether_poll_deregister() if polling is enabled. - In polling handler driver obtains its lock and checks IFF_DRV_RUNNING flag. If there is no, then unlocks and returns. - In ioctl handler driver checks for IFCAP_POLLING flag requested to be set or cleared. Driver first calls ether_poll_[de]register(), then obtains driver lock and [dis/en]ables interrupts. - In interrupt handler driver checks IFCAP_POLLING flag in if_capenable. If present, then returns.This is important to protect from spurious interrupts. Reviewed by: ru, sam, jhb
2005-10-01 18:56:19 +00:00
}
#endif /* DEVICE_POLLING */
Initial WOL support. NS DP8315 was tested but SiS900/SiS7016 was not tested. While I'm here, clean up SIOCSIFCAP handler.
2010-09-03 00:34:45 +00:00
if ((mask & IFCAP_WOL) != 0 &&
(ifp->if_capabilities & IFCAP_WOL) != 0) {
if ((mask & IFCAP_WOL_UCAST) != 0)
ifp->if_capenable ^= IFCAP_WOL_UCAST;
if ((mask & IFCAP_WOL_MCAST) != 0)
ifp->if_capenable ^= IFCAP_WOL_MCAST;
if ((mask & IFCAP_WOL_MAGIC) != 0)
ifp->if_capenable ^= IFCAP_WOL_MAGIC;
}
SIS_UNLOCK(sc);
Implemented per-interface polling(4) control.
2004-04-11 20:34:08 +00:00
break;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
default:
o track either_ifattach/ether_ifdetach API changes o use if_input for input packet processing o don't strip the Ethernet header for input packets o use BPF_* macros bpf tapping o call ether_ioctl to handle default ioctl case o track vlan changes Reviewed by: many Approved by: re
2002-11-14 23:49:09 +00:00
error = ether_ioctl(ifp, command, data);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
break;
}
style(9) - space after keywords.
2010-09-01 18:39:35 +00:00
return (error);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static void
Convert sis(4) to use its own watchdog procedure. Submitted by: Florian C. Smeets <flo kasimir com>
2007-02-24 14:27:36 +00:00
sis_watchdog(struct sis_softc *sc)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
Convert sis(4) to use its own watchdog procedure. Submitted by: Florian C. Smeets <flo kasimir com>
2007-02-24 14:27:36 +00:00
SIS_LOCK_ASSERT(sc);
First round of converting network drivers from spls to mutexes. This takes care of all the 10/100 and gigE PCI drivers that I've done. Next will be the wireless drivers, then the USB ones. I may pick up some stragglers along the way. I'm sort of playing this by ear: if anyone spots any places where I've screwed up horribly, please let me know.
2000-10-13 17:54:19 +00:00
Convert sis(4) to use its own watchdog procedure. Submitted by: Florian C. Smeets <flo kasimir com>
2007-02-24 14:27:36 +00:00
if (sc->sis_watchdog_timer == 0 || --sc->sis_watchdog_timer >0)
return;
device_printf(sc->sis_dev, "watchdog timeout\n");
Mechanically convert to if_inc_counter().
2014-09-18 20:09:35 +00:00
if_inc_counter(sc->sis_ifp, IFCOUNTER_OERRORS, 1);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Move sis_reset() to sis_initl(). This ensures driver starts with known good state of controller.
2010-09-01 22:50:11 +00:00
sc->sis_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
Add locked/unlocked variants of sis_init()
2005-01-05 10:11:37 +00:00
sis_initl(sc);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Convert sis(4) to use its own watchdog procedure. Submitted by: Florian C. Smeets <flo kasimir com>
2007-02-24 14:27:36 +00:00
if (!IFQ_DRV_IS_EMPTY(&sc->sis_ifp->if_snd))
sis_startl(sc->sis_ifp);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
/*
* Stop the adapter and free any mbufs allocated to the
* RX and TX lists.
*/
Put return values from functions on a line by themselves. Ok'd previously by: wpaul
2002-08-23 23:19:25 +00:00
static void
Style: new-speak functions, remove pointless "return".
2005-01-05 22:23:03 +00:00
sis_stop(struct sis_softc *sc)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
Simplify and fix bugs in rx/tx ring cleanup.
2005-01-06 23:36:43 +00:00
struct ifnet *ifp;
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
struct sis_rxdesc *rxd;
struct sis_txdesc *txd;
int i;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
Make sis_initl() take a typed argument. Expect caller to lock before calling sis_stop() Various style stuff.
2005-01-05 10:26:12 +00:00
SIS_LOCK_ASSERT(sc);
Overhaul link state change handling. Previously sis(4) blindly configured TX/RX MACs before getting a valid link. After that, when link state change callback is called, it called device initialization again to reconfigure TX/RX MACs depending on resolved link state. This hack created several bad side effects and it required more hacks to not collide with sis_tick callback as well as disabling switching to currently selected media in device initialization. Also it seems sis(4) was used to be a template driver for long time so other drivers which was modeled after sis(4) also should be changed. TX/RX MACs are now reconfigured after getting a valid link. Fix for short cable error is also applied after getting a link because it's only valid when the resolved speed is 100Mbps. While I'm here slightly reorganize interrupt handler such that sis(4) always read SIS_ISR register to see whether the interrupt is ours or not. This change removes another hack and make it possible to nuke sis_stopped variable in softc.
2010-09-01 21:42:19 +00:00
Stop embedding struct ifnet at the top of driver softcs. Instead the struct ifnet or the layer 2 common structure it was embedded in have been replaced with a struct ifnet pointer to be filled by a call to the new function, if_alloc(). The layer 2 common structure is also allocated via if_alloc() based on the interface type. It is hung off the new struct ifnet member, if_l2com. This change removes the size of these structures from the kernel ABI and will allow us to better manage them as interfaces come and go. Other changes of note: - Struct arpcom is no longer referenced in normal interface code. Instead the Ethernet address is accessed via the IFP2ENADDR() macro. To enforce this ac_enaddr has been renamed to _ac_enaddr. - The second argument to ether_ifattach is now always the mac address from driver private storage rather than sometimes being ac_enaddr. Reviewed by: sobomax, sam
2005-06-10 16:49:24 +00:00
ifp = sc->sis_ifp;
Convert sis(4) to use its own watchdog procedure. Submitted by: Florian C. Smeets <flo kasimir com>
2007-02-24 14:27:36 +00:00
sc->sis_watchdog_timer = 0;
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
change timer to MPSAFE Sponsored by: FreeBSD Foundation
2003-09-05 22:33:44 +00:00
callout_stop(&sc->sis_stat_ch);
MFS (merge from stable): rev 1.13.4.13, fix ordering of IFF_RUNNING mods. The reason we are required to commit to -current first is so that later MFC's do not risk the loss of existing bug fixes. Even if this was not strictly required in -current, it should still be fixed there too.
2001-12-07 00:58:37 +00:00
Propagate rename of IFF_OACTIVE and IFF_RUNNING to IFF_DRV_OACTIVE and IFF_DRV_RUNNING, as well as the move from ifnet.if_flags to ifnet.if_drv_flags. Device drivers are now responsible for synchronizing access to these flags, as they are in if_drv_flags. This helps prevent races between the network stack and device driver in maintaining the interface flags field. Many __FreeBSD__ and __FreeBSD_version checks maintained and continued; some less so. Reviewed by: pjd, bz MFC after: 7 days
2005-08-09 10:20:02 +00:00
ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
CSR_WRITE_4(sc, SIS_IER, 0);
CSR_WRITE_4(sc, SIS_IMR, 0);
Make sure to clear any pending interrupts when we stop the interface.
2005-01-06 23:18:44 +00:00
CSR_READ_4(sc, SIS_ISR); /* clear any interrupts already pending */
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
SIS_SETBIT(sc, SIS_CSR, SIS_CSR_TX_DISABLE|SIS_CSR_RX_DISABLE);
DELAY(1000);
CSR_WRITE_4(sc, SIS_TX_LISTPTR, 0);
CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
Unlike most other controllers, NS DP83815/DP83816 controllers seem to pad with 0xFF when it encounter short frames. According to RFC 1042 the pad bytes should be 0x00. Because manual padding consumes extra CPU cycles, introduce a new tunable which controls the padding behavior. Turning this tunable on will have driver pad manually but it's disabled by default. Users can enable software padding by setting the following tunable to non-zero value. dev.sis.%d.manual_pad="1" PR: kern/35422 (patch not used)
2010-09-02 18:10:11 +00:00
sc->sis_flags &= ~SIS_FLAG_LINK;
Fix up the sis driver, largely to improve the NatSemi DP83815 support: - Modify the driver to poll the link state and positively set the MAC to full or half duplex as needed. Previously, it was possible for the MAC to remain in half duplex even though the PHY had negotiated full duplex with its link partner, which would result in bursty performance. - Program some of the NatSemi's registers as specified by the datasheet. The manual says these are necessary for "optimum perofrmance," though a couple of them are marked as reserved in the register map. *shrug* - Select the TX DMA burst size correctly for 10 and 100mbps modes. Previously I was using 64 bytes in both modes, which worked in 100mbps mode, but resulting in spotty performance in 10mbps. 32 bytes works much better; without this change, the natsemi chip yields piss poor performance at 10mbps. With these fixes, the NatSemi chip finally performs to my satisfaction. I should be merging the support for this controller into -stable shortly. Phew.
2000-08-22 23:26:51 +00:00
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
/*
* Free data in the RX lists.
*/
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
for (i = 0; i < SIS_RX_LIST_CNT; i++) {
rxd = &sc->sis_rxdesc[i];
if (rxd->rx_m != NULL) {
bus_dmamap_sync(sc->sis_rx_tag, rxd->rx_dmamap,
BUS_DMASYNC_POSTREAD);
bus_dmamap_unload(sc->sis_rx_tag, rxd->rx_dmamap);
m_freem(rxd->rx_m);
rxd->rx_m = NULL;
}
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
/*
* Free the TX list buffers.
*/
bus_dma(9) cleanup. o Enforce TX/RX descriptor ring alignment. NS data sheet says the controller needs 4 bytes alignment but use 16 to cover both SiS and NS controllers. I don't have SiS data sheet so I'm not sure what is alignment restriction of SiS controller but 16 would be enough because it's larger than the size of a TX/RX descriptor. Previously sis(4) ignored the alignment restriction. o Enforce RX buffer alignment, 4. Previously sis(4) ignored RX buffer alignment restriction. o Limit number of TX DMA segment to be used to 16. It seems controller has no restriction on number of DMA segments but using more than 16 looks resource waste. o Collapse long mbuf chains with m_collapse(9) instead of calling expensive m_defrag(9). o TX/RX side bus_dmamap_load_mbuf_sg(9) support and remove unnecessary callbacks. o Initial endianness support. o Prefer local alignment fixup code to m_devget(9). o Pre-allocate TX/RX mbuf DMA maps instead of creating/destroying these maps in fast TX/RX path. On non-x86 architectures, this is very expensive operation and there is no need to do that. o Add missing bus_dmamap_sync(9) in TX/RX path. o watchdog is now unarmed only when there are no pending frames on controller. Previously sis(4) blindly unarmed watchdog without checking the number of queued frames. o For efficiency, loaded DMA map is reused for error frames. o DMA map loading failure is now gracefully handled. Previously sis(4) ignored any DMA map loading errors. o Nuke unused macros which are not appropriate for endianness operation. o Stop embedding driver maintained structures into descriptor rings. Because TX/RX descriptor structures are shared between host and controller, frequent bus_dmamap_sync(9) operations are required in fast path. Embedding driver structures will increase the size of DMA map which in turn will slow down performance.
2010-09-01 19:33:40 +00:00
for (i = 0; i < SIS_TX_LIST_CNT; i++) {
txd = &sc->sis_txdesc[i];
if (txd->tx_m != NULL) {
bus_dmamap_sync(sc->sis_tx_tag, txd->tx_dmamap,
BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sis_tx_tag, txd->tx_dmamap);
m_freem(txd->tx_m);
txd->tx_m = NULL;
}
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
}
/*
* Stop all chip I/O so that the kernel's probe routines don't
* get confused by errant DMAs when rebooting.
*/
Fix shutdown prototypes.
2009-02-10 23:17:20 +00:00
static int
Make sis_initl() take a typed argument. Expect caller to lock before calling sis_stop() Various style stuff.
2005-01-05 10:26:12 +00:00
sis_shutdown(device_t dev)
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
{
Initial WOL support. NS DP8315 was tested but SiS900/SiS7016 was not tested. While I'm here, clean up SIOCSIFCAP handler.
2010-09-03 00:34:45 +00:00
return (sis_suspend(dev));
This commit adds driver support for the Silicon Integrated Systems SiS 900 and SiS 7016 PCI fast ethernet chipsets. Full manuals for the SiS chips can be found at www.sis.com.tw. This is a fairly simple chipset. The receiver uses a 128-bit multicast hash table and single perfect entry for the station address. Transmit and receive DMA and FIFO thresholds are easily tuneable. Documentation is pretty decent and performance is not bad, even on my crufty 486. This driver uses newbus and miibus and is supported on both the i386 and alpha architectures.
1999-09-05 21:01:03 +00:00
}
Move the module related stuff to the bottom of the file. This will allow us to save prototypes.
2005-01-06 23:22:38 +00:00
Implement initial device suspend/resume method.
2010-09-02 22:37:13 +00:00
static int
sis_suspend(device_t dev)
{
struct sis_softc *sc;
sc = device_get_softc(dev);
SIS_LOCK(sc);
sis_stop(sc);
Initial WOL support. NS DP8315 was tested but SiS900/SiS7016 was not tested. While I'm here, clean up SIOCSIFCAP handler.
2010-09-03 00:34:45 +00:00
sis_wol(sc);
Implement initial device suspend/resume method.
2010-09-02 22:37:13 +00:00
SIS_UNLOCK(sc);
return (0);
}
static int
sis_resume(device_t dev)
{
struct sis_softc *sc;
struct ifnet *ifp;
sc = device_get_softc(dev);
SIS_LOCK(sc);
ifp = sc->sis_ifp;
if ((ifp->if_flags & IFF_UP) != 0) {
ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
sis_initl(sc);
}
SIS_UNLOCK(sc);
return (0);
}
Initial WOL support. NS DP8315 was tested but SiS900/SiS7016 was not tested. While I'm here, clean up SIOCSIFCAP handler.
2010-09-03 00:34:45 +00:00
static void
sis_wol(struct sis_softc *sc)
{
struct ifnet *ifp;
uint32_t val;
uint16_t pmstat;
int pmc;
ifp = sc->sis_ifp;
if ((ifp->if_capenable & IFCAP_WOL) == 0)
return;
if (sc->sis_type == SIS_TYPE_83815) {
/* Reset RXDP. */
CSR_WRITE_4(sc, SIS_RX_LISTPTR, 0);
/* Configure WOL events. */
CSR_READ_4(sc, NS_WCSR);
val = 0;
if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
val |= NS_WCSR_WAKE_UCAST;
if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
val |= NS_WCSR_WAKE_MCAST;
if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
val |= NS_WCSR_WAKE_MAGIC;
CSR_WRITE_4(sc, NS_WCSR, val);
/* Enable PME and clear PMESTS. */
val = CSR_READ_4(sc, NS_CLKRUN);
val |= NS_CLKRUN_PMEENB | NS_CLKRUN_PMESTS;
CSR_WRITE_4(sc, NS_CLKRUN, val);
/* Enable silent RX mode. */
SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE);
} else {
Do a sweep of the tree replacing calls to pci_find_extcap() with calls to pci_find_cap() instead.
2011-03-23 13:10:15 +00:00
if (pci_find_cap(sc->sis_dev, PCIY_PMG, &pmc) != 0)
Initial WOL support. NS DP8315 was tested but SiS900/SiS7016 was not tested. While I'm here, clean up SIOCSIFCAP handler.
2010-09-03 00:34:45 +00:00
return;
val = 0;
if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
val |= SIS_PWRMAN_WOL_MAGIC;
CSR_WRITE_4(sc, SIS_PWRMAN_CTL, val);
/* Request PME. */
pmstat = pci_read_config(sc->sis_dev,
pmc + PCIR_POWER_STATUS, 2);
pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
pci_write_config(sc->sis_dev,
pmc + PCIR_POWER_STATUS, pmstat, 2);
}
}
Unlike most other controllers, NS DP83815/DP83816 controllers seem to pad with 0xFF when it encounter short frames. According to RFC 1042 the pad bytes should be 0x00. Because manual padding consumes extra CPU cycles, introduce a new tunable which controls the padding behavior. Turning this tunable on will have driver pad manually but it's disabled by default. Users can enable software padding by setting the following tunable to non-zero value. dev.sis.%d.manual_pad="1" PR: kern/35422 (patch not used)
2010-09-02 18:10:11 +00:00
static void
sis_add_sysctls(struct sis_softc *sc)
{
struct sysctl_ctx_list *ctx;
struct sysctl_oid_list *children;
int unit;
ctx = device_get_sysctl_ctx(sc->sis_dev);
children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sis_dev));
unit = device_get_unit(sc->sis_dev);
/*
* Unlike most other controllers, NS DP83815/DP83816 controllers
* seem to pad with 0xFF when it encounter short frames. According
* to RFC 1042 the pad bytes should be 0x00. Turning this tunable
* on will have driver pad manully but it's disabled by default
* because it will consume extra CPU cycles for short frames.
*/
sc->sis_manual_pad = 0;
SYSCTL_ADD_INT(ctx, children, OID_AUTO, "manual_pad",
Pull in r267961 and r267973 again. Fix for issues reported will follow.
2014-06-28 03:56:17 +00:00
CTLFLAG_RWTUN, &sc->sis_manual_pad, 0, "Manually pad short frames");
Unlike most other controllers, NS DP83815/DP83816 controllers seem to pad with 0xFF when it encounter short frames. According to RFC 1042 the pad bytes should be 0x00. Because manual padding consumes extra CPU cycles, introduce a new tunable which controls the padding behavior. Turning this tunable on will have driver pad manually but it's disabled by default. Users can enable software padding by setting the following tunable to non-zero value. dev.sis.%d.manual_pad="1" PR: kern/35422 (patch not used)
2010-09-02 18:10:11 +00:00
}
Move the module related stuff to the bottom of the file. This will allow us to save prototypes.
2005-01-06 23:22:38 +00:00
static device_method_t sis_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, sis_probe),
DEVMETHOD(device_attach, sis_attach),
DEVMETHOD(device_detach, sis_detach),
DEVMETHOD(device_shutdown, sis_shutdown),
Implement initial device suspend/resume method.
2010-09-02 22:37:13 +00:00
DEVMETHOD(device_suspend, sis_suspend),
DEVMETHOD(device_resume, sis_resume),
Move the module related stuff to the bottom of the file. This will allow us to save prototypes.
2005-01-06 23:22:38 +00:00
/* MII interface */
DEVMETHOD(miibus_readreg, sis_miibus_readreg),
DEVMETHOD(miibus_writereg, sis_miibus_writereg),
DEVMETHOD(miibus_statchg, sis_miibus_statchg),
- There's no need to overwrite the default device method with the default one. Interestingly, these are actually the default for quite some time (bus_generic_driver_added(9) since r52045 and bus_generic_print_child(9) since r52045) but even recently added device drivers do this unnecessarily. Discussed with: jhb, marcel - While at it, use DEVMETHOD_END. Discussed with: jhb - Also while at it, use __FBSDID.
2011-11-22 21:28:20 +00:00
DEVMETHOD_END
Move the module related stuff to the bottom of the file. This will allow us to save prototypes.
2005-01-06 23:22:38 +00:00
};
static driver_t sis_driver = {
"sis",
sis_methods,
sizeof(struct sis_softc)
};
static devclass_t sis_devclass;
DRIVER_MODULE(sis, pci, sis_driver, sis_devclass, 0, 0);
DRIVER_MODULE(miibus, sis, miibus_driver, miibus_devclass, 0, 0);
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