Commit Graph

251 Commits

Author SHA1 Message Date
Ed Schouten
53627e400f Replace __signed by signed.
The signed keyword is an integral part of the C syntax. There's no need
to use __signed.
2011-12-13 13:38:03 +00:00
Jayachandran C.
fb1677186a XLP processors have the release 2 pagegrain register
Add accessors to cpufunc.h

Obtained from:	prabhath at netlogicmicro com
2011-11-21 07:55:37 +00:00
Jayachandran C.
eeb41c230d Fix COP0 hazards for XLR and XLP
The XLR CPUs do not have any software visible hazards for COP0 operations.
On XLP the hazard is a ehb, since it is mips64r2.
2011-11-18 09:30:24 +00:00
David Schultz
a50079b7ff People porting FreeBSD to new architectures ought not have to
implement a deprecated FPU control interface in addition to the
standard one.  To make this clearer, further deprecate ieeefp.h
by not declaring the function prototypes except on architectures
that implement them already.

Currently i386 and amd64 implement the ieeefp.h interface for
compatibility, and for fp[gs]etprec(), which doesn't exist on
most other hardware.  Powerpc, sparc64, and ia64 partially implement
it and probably shouldn't, and other architectures don't implement it
at all.
2011-10-21 06:41:46 +00:00
Jayachandran C.
29550c285c Fix wakeup latency when sleeping with 'wait'
If we handle an interrupt just before the 'wait' and the interrupt
schedules some work, we need to skip the 'wait' call. The simple solution
of calling sched_runnable() with interrupts disabled immediately before
wait still leaves a window after the call and before 'wait' in which
the same issue can occur.

The solution implemented is to check the EPC in the interrupt handler, and
if it is in a region before the 'wait' call, to fix up the EPC to skip the
wait call.

Reported/analysed by:	adrian
Fix suggested by:	kib

Reviewed by:	jmallett, imp
2011-10-18 16:37:28 +00:00
Jayachandran C.
8291dd8a41 Support for booting XLP using FDT.
- update xlp_machdep.c to read arguments from FDT if FDT support is
  compiled in.
- define rmi_uart_bus_space, and use it as fdtbus_bs_tag
- update conf files for FDT support
- add default dts file xlp-basic.dts
2011-10-18 08:10:23 +00:00
Jayachandran C.
29a99755a9 FDT support for MIPS.
Add architecture specific files needed to compile MIPS with
flattened device tree support.
2011-10-18 07:29:21 +00:00
Konstantin Belousov
6bfe4c78c8 Remove unused define.
MFC after:	1 month
2011-10-07 16:09:44 +00:00
Konstantin Belousov
877012982b Convert MIPS to the syscallenter/syscallret system call sequence handlers.
This was the last architecture used custom syscall entry sequence.

Reviewed, debugged, tested and approved by:	jchandra
MFC after:	1 month
2011-10-06 17:34:43 +00:00
Marcel Moolenaar
f11e3710b0 Remove bogus and wrong definition of BLKDEV_IOSIZE.
Wrong in that it must be guarded (it's configurable)
and bogus in that there's absolutely no rationale for
it not default to a page size like all other archs.
2011-10-04 18:06:08 +00:00
Attilio Rao
68b739cd6f Add the possibility to specify from kernel configs MAXCPU value.
This patch is going to help in cases like mips flavours where you
want a more granular support on MAXCPU.

No MFC is previewed for this patch.

Tested by:	pluknet
Approved by:	re (kib)
2011-07-19 00:37:24 +00:00
Jayachandran C.
ae78a2ad86 MIPS changes for Netlogic XLP support.
This patch adds support for the Netlogic XLP mips64 processors in
the common MIPS code. The changes are :

- Add CPU_NLM processor type
- Add cases for CPU_NLM, mostly were CPU_RMI is used.
- Update cache flush changes for CPU_NLM
- Add kernel build configuration files for xLP.

In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com>

Approved by:	bz(re), jmallett, imp(mips)
2011-07-16 20:31:29 +00:00
Attilio Rao
b2aa562e7b MFC 2011-05-13 20:58:48 +00:00
Attilio Rao
f89d6b3f06 Fix a brain-o in platform_cpu_mask() by just specifying a possible
cpuset_t to be copied, rather than return the array.
I can't rely anymore on this being a simple int/long object.

Reported by:	art
2011-05-13 19:56:58 +00:00
Matthew D Fleming
cfb00e5aa7 Move the ZERO_REGION_SIZE to a machine-dependent file, as on many
architectures (i386, for example) the virtual memory space may be
constrained enough that 2MB is a large chunk.  Use 64K for arches
other than amd64 and ia64, with special handling for sparc64 due to
differing hardware.

Also commit the comment changes to kmem_init_zero_region() that I
missed due to not saving the file.  (Darn the unfamiliar development
environment).

Arch maintainers, please feel free to adjust ZERO_REGION_SIZE as you
see fit.

Requested by:	alc
MFC after:	1 week
MFC with:	r221853
2011-05-13 19:35:01 +00:00
Attilio Rao
245a253538 Add the cpuset_t conversion for mips. 2011-05-13 16:42:05 +00:00
Attilio Rao
250c198bd7 Fix the _long() rappresentation on mips by casting the long arguments
to u_int for all the functions.

Reviewed by:	art, imp
2011-05-13 16:39:47 +00:00
Juli Mallett
dea2d4206e o) Properly size caches and TLB on Octeon.
o) Make COP0_SYNC do nothing on Octeon, which is fully interlocked.

Submitted by:	Bhanu Prakash (with modifications)
2011-03-16 08:22:29 +00:00
Jayachandran C.
1e4b58070b Increase NKPT in case of n32 and n64 to support more physical memory.
On n32, vm_page_startup() needs more virtual mem to map vm_page structs.
The new value of 256 will allow us to support 16GB RAM.
2011-03-01 04:21:56 +00:00
Alan Cox
e6ffa21488 Remove pmap fields that are either unused or not fully implemented.
Discussed with:	kib
2011-02-17 15:36:29 +00:00
Juli Mallett
1591f3f18c Allow the platform code to return a bitmask of running cores rather than just
a number of cores, this allows for a sparse set of CPUs.  Implement support
for sparse core masks on Octeon.

XXX jeff@ suggests that all_cpus should include cores that are offline or
    running other applications/OSes, so the platform API should be further
    extended to allow us to set all_cpus to include all cores that are
    physically-present as opposed to only those that are running FreeBSD.

Submitted by:	Bhanu Prakash (with modifications)
Reviewed by:	jchandra
Glanced at by:	kib, jeff, jhb
2011-02-12 02:08:24 +00:00
Juli Mallett
70019a0be7 o) Cavium Octeon doesn't need nop barriers.
o) Have mips_wblush just do syncw, not sync on Cavium Octeon.
o) Add support for reading and writing some Octeon-specific registers.
   NB: Some of these are not entirely Octeon-specific.

Submitted by:	Bhanu Prakash
2011-02-06 22:21:18 +00:00
Tijl Coosemans
4e518ddb21 Replace __LP64__ with __mips_n64. This partly reverts r217147.
Requested by:	jmallett, imp
Approved by:	kib (mentor)
2011-02-04 13:09:46 +00:00
Jayachandran C.
21835e695a Implement sf_buf using direct map (XKPHYS) in MIPS n64.
- Provide trivial implementation of sf_buf_alloc(), sf_buf_free(),
  sf_buf_kva() and sf_buf_page() using direct map for n64.
- uio_machdep.c - use macros so that the direct map will be used in
  case of n64.

Reviewed by:	imp (earlier version)
Obtained from:	jmallett (user/jmallett/octeon)
2011-01-27 14:49:22 +00:00
Jung-uk Kim
2fea643112 Add reader/writer lock around mem_range_attr_get() and mem_range_attr_set().
Compile sys/dev/mem/memutil.c for all supported platforms and remove now
unnecessary dev_mem_md_init().  Consistently define mem_range_softc from
mem.c for all platforms.  Add missing #include guards for machine/memdev.h
and sys/memrange.h.  Clean up some nearby style(9) nits.

MFC after:	1 month
2011-01-17 22:58:28 +00:00
Jayachandran C.
611f086953 Support for 64 bit PTEs on n32 and n64 compilation.
In n32 and n64, add support for physical address above 4GB by having
64 bit page table entries and physical addresses. Major changes are:
- param.h: update PTE sizes, masks and shift values to support 64 bit PTEs.
- param.h: remove DELAY(), mips_btop(same as atop), mips_ptob (same as
  ptoa), and reformat.
- param.h: remove casting to unsigned long in trunc_page and round_page
  since this will be used on physical addresses.
- _types.h: have 64 bit __vm_paddr_t for n32.
- pte.h: update TLB LO0/1 access macros to support 64 bit PTE
- pte.h: assembly macros for PTE operations.
- proc.h: md_upte is now 64 bit for n32 and n64.
- exception.S and swtch.S: use the new PTE macros for PTE operations.
- cpufunc.h: TLB_LO0/1 registers are 64bit for n32 and n64.
- xlr_machdep.c: Add memory segments above 4GB to phys_avail[] as they are
  supported now.

Reviewed by:	jmallett (earlier version)
2011-01-13 15:17:29 +00:00
Jayachandran C.
0dd873372a Cleanup physical address and PTE types on MIPS.
1. Use vm_paddr_t for physical addresses.

There are a few places in the MIPS platform code where vm_offset_t is
used for physical addresses, change these to use vm_paddr_t:
- phys_avail[], physmem_desc[] arrays
- pmap_mapdev(), page_is_managed(), is_cacheable_mem() pmap_map() args
- local variables of various pmap functions

2. Change init_pte_prot() return from int to pt_entry_t, as this can be
64 bit when using 64 bit TLB entries.

3. Update printing of pt_entry_t and of vm_paddr_t to use 'j' format with
uintmax_t. This will be useful later if we plan to use 64bit phsical addr
on 32 bit n32 compilation.

Reviewed by:	imp
2011-01-13 06:48:43 +00:00
Konstantin Belousov
50a57dfbec Move repeated MAXSLP definition from machine/vmparam.h to sys/vmmeter.h.
Update the outdated comments describing MAXSLP and the process
selection algorithm for swap out.

Comments wording and reviewed by:	alc
2011-01-09 12:50:44 +00:00
Tijl Coosemans
f65742b27b White space changes to align comments. The mips and powerpc _inttypes.h
are now exactly the same.

Approved by:	kib (mentor)
2011-01-08 18:02:46 +00:00
Tijl Coosemans
9821039a64 Rename PRIreg helper macro to PRIptr to better reflect its use. Registers
and pointers don't always have the same size, e.g. the __mips_n32 ABI
(ILP32) has 64 bit registers but 32 bit pointers.

On mips introduce PRIptr to fix the format specifier for (u)intptr_t.

Prefix PRI64 and PRIptr with underscores because macro names starting with
PRI[a-zX] are reserved for future use.

Approved by:	kib (mentor)
2011-01-08 18:00:19 +00:00
Tijl Coosemans
a56e818f29 On mixed 32/64 bit architectures (mips, powerpc) use __LP64__ rather than
architecture macros (__mips_n64, __powerpc64__) when 64 bit types (and
corresponding macros) are different from 32 bit. [1]

Correct the type of INT64_MIN, INT64_MAX and UINT64_MAX.

Define (U)INTMAX_C as an alias for (U)INT64_C matching the type definition
for (u)intmax_t. Do this on all architectures for consistency.

Suggested by:	bde [1]
Approved by:	kib (mentor)
2011-01-08 12:43:05 +00:00
Tijl Coosemans
d942996baf On 32 bit architectures define (u)int64_t as (unsigned) long long instead
of (unsigned) int __attribute__((__mode__(__DI__))). This aligns better
with macros such as (U)INT64_C, (U)INT64_MAX, etc. which assume (u)int64_t
has type (unsigned) long long.

The mode attribute was used because long long wasn't standardised until
C99. Nowadays compilers should support long long and use of the mode
attribute is discouraged according to GCC Internals documentation.

The type definition has to be marked with __extension__ to support
compilation with "-std=c89 -pedantic".

Discussed with:	bde
Approved by:	kib (mentor)
2011-01-08 11:47:55 +00:00
Tijl Coosemans
9858863cd4 Fix types of some values in machine/_limits.h.
On some architectures UCHAR_MAX and USHRT_MAX had type unsigned int.
However, lacking integer suffixes for types smaller than int, their type
should correspond to that of an object of type unsigned char (or short)
when used in an expression with objects of type int. In that case unsigned
char (short) are promoted to int (i.e. signed) so the type of UCHAR_MAX and
USHRT_MAX should also be int.

Where MIN/MAX constants implicitly have the correct type the suffix has
been removed.

While here, correct some comments.

Reviewed by:	bde
Approved by:	kib (mentor)
2011-01-08 11:13:34 +00:00
Tijl Coosemans
911127a0d6 Remove unused support for 64 bit long on 32 bit architectures.
It was used mainly to discover and fix some 64-bit portability problems
before 64-bit arches were widely available.

Discussed with:	bde
Approved by:	kib (mentor)
2011-01-07 22:57:31 +00:00
Konstantin Belousov
39198f15ee Add AT_STACKPROT elf aux vector. Will be used to inform rtld about the
initial stack protection set by the kernel image activator.
2011-01-07 14:22:34 +00:00
Juli Mallett
ab19dbcf8d Correct an 8-year-old typo which reliably leads to typo after typo today:
The macros here for generating coprocessor 0 accessors are named like:

	MIPS_RDRW32_COP0

That macro would produce mips_rd_<register>() and mips_wr_<register>()
inlines to access the specified register by name from C.  The problem is that
the R and the W were swapped in the macros originally; it was meant to be named
RDWR because it generated mips_rd_* and mips_wr_* functions, but was instead
spelled RDRW, which nobody should be expected to get right by anything other
than copy and paste.

It's too many consonants in a row to keep straight anyway, so just prefer e.g.:

	MIPS_RW32_COP0

While here, add a missing #undef.
2011-01-04 19:32:03 +00:00
Juli Mallett
7b62328843 o) Add MIPS_COP_0_EXC_PC accessors to <machine/cpufunc.h>.
o) Make the octeon_wdog driver work on multi-CPU systems and to also print more
   information on NMI that may aid debugging.  Simplify and clean up internal
   API and structure.
2011-01-04 02:33:48 +00:00
Jayachandran C.
6264198089 UMA_MD_SMALL_ALLOC for mips.
Implement uma_small_alloc() and uma_small_free() for mips that allocates
pages from direct mapped memory. Uses the same mechanism as the page table
page allocator, so that we allocate from KSEG0 in 32 bit, and from XKPHYS
on 64 bit.

Reviewed by:	alc, jmallett
2010-12-09 06:34:28 +00:00
Jayachandran C.
63ae6e6018 1. Fix off by one errors in calls to MIPS_DIRECT_MAPPABLE, reported by alc@
2. Remove unnecessary #defines from vmparam.h

Submitted by:	alc (2)
Reviewed by:	alc (1)
2010-12-03 19:22:18 +00:00
Jayachandran C.
42b73858e9 Fixup for r216141, dump_add_page needs to be non-static now.
Add it to sys/mips/include/md_var.h, make dump_drop_page non-static too
for completeness.
2010-12-03 14:20:20 +00:00
Rebecca Cran
c90f7d9b44 Revert r216134. This checkin broke platforms where bus_space are macros:
they need to be a single statement, and do { } while (0) doesn't work in this
situation so revert until a solution can be devised.
2010-12-03 07:09:23 +00:00
Rebecca Cran
15b4888a24 Disallow passing in a count of zero bytes to the bus_space(9) functions.
Passing a count of zero on i386 and amd64 for [I386|AMD64]_BUS_SPACE_MEM
causes a crash/hang since the 'loop' instruction decrements the counter
before checking if it's zero.

PR:	kern/80980
Discussed with:	jhb
2010-12-02 22:19:30 +00:00
Juli Mallett
2a89829bde Set MACHINE_ARCH based on ABI and endianness.
Reviewed by:	imp
2010-11-28 04:07:45 +00:00
John Baldwin
961135ead8 - Remove <machine/mutex.h>. Most of the headers were empty, and the
contents of the ones that were not empty were stale and unused.
- Now that <machine/mutex.h> no longer exists, there is no need to allow it
  to override various helper macros in <sys/mutex.h>.
- Rename various helper macros for low-level operations on mutexes to live
  in the _mtx_* or __mtx_* namespaces.  While here, change the names to more
  closely match the real API functions they are backing.
- Drop support for including <sys/mutex.h> in assembly source files.

Suggested by:	bde (1, 2)
2010-11-09 20:46:41 +00:00
Oleksandr Tymoshenko
903ba3da86 - Add minidump support for FreeBSD/mips 2010-11-07 03:09:02 +00:00
Neel Natu
5df4b6be91 Enforce that 'pmap_kenter()' is only used to establish cacheable mappings.
Mappings with other cacheability attributes can be established, if needed,
by using 'pmap_kenter_attr()'.

Suggested by:	jchandra, imp
2010-09-22 02:26:07 +00:00
Neel Natu
2f78c3e5a0 Get rid of the unnecessary redirection of 'is_cacheable_mem()' to
'is_physical_memory()' through a macro.

Implement 'is_cacheable_mem()' directly instead.
2010-09-17 02:20:12 +00:00
Neel Natu
db1a9b7dfb Get rid of unused macros. 2010-09-17 02:14:21 +00:00
Neel Natu
885b75a559 Make the meaning of the 'mask' argument to 'set_intr_mask(mask)' consistent
with the meaning of IM bits in the status register.

Reviewed by:	jmallett, jchandra
2010-09-15 05:10:50 +00:00
Alexander Motin
a157e42516 Refactor timer management code with priority to one-shot operation mode.
The main goal of this is to generate timer interrupts only when there is
some work to do. When CPU is busy interrupts are generating at full rate
of hz + stathz to fullfill scheduler and timekeeping requirements. But
when CPU is idle, only minimum set of interrupts (down to 8 interrupts per
second per CPU now), needed to handle scheduled callouts is executed.
This allows significantly increase idle CPU sleep time, increasing effect
of static power-saving technologies. Also it should reduce host CPU load
on virtualized systems, when guest system is idle.

There is set of tunables, also available as writable sysctls, allowing to
control wanted event timer subsystem behavior:
  kern.eventtimer.timer - allows to choose event timer hardware to use.
On x86 there is up to 4 different kinds of timers. Depending on whether
chosen timer is per-CPU, behavior of other options slightly differs.
  kern.eventtimer.periodic - allows to choose periodic and one-shot
operation mode. In periodic mode, current timer hardware taken as the only
source of time for time events. This mode is quite alike to previous kernel
behavior. One-shot mode instead uses currently selected time counter
hardware to schedule all needed events one by one and program timer to
generate interrupt exactly in specified time. Default value depends of
chosen timer capabilities, but one-shot mode is preferred, until other is
forced by user or hardware.
  kern.eventtimer.singlemul - in periodic mode specifies how much times
higher timer frequency should be, to not strictly alias hardclock() and
statclock() events. Default values are 2 and 4, but could be reduced to 1
if extra interrupts are unwanted.
  kern.eventtimer.idletick - makes each CPU to receive every timer interrupt
independently of whether they busy or not. By default this options is
disabled. If chosen timer is per-CPU and runs in periodic mode, this option
has no effect - all interrupts are generating.

As soon as this patch modifies cpu_idle() on some platforms, I have also
refactored one on x86. Now it makes use of MONITOR/MWAIT instrunctions
(if supported) under high sleep/wakeup rate, as fast alternative to other
methods. It allows SMP scheduler to wake up sleeping CPUs much faster
without using IPI, significantly increasing performance on some highly
task-switching loads.

Tested by:	many (on i386, amd64, sparc64 and powerc)
H/W donated by:	Gheorghe Ardelean
Sponsored by:	iXsystems, Inc.
2010-09-13 07:25:35 +00:00