Commit Graph

255 Commits

Author SHA1 Message Date
Warner Losh
a371f04d66 GC some now-unused items. Fix for 64-bit build. Note: this breaks
the 32-bit build (which we're not computing correctly anyway).
2009-07-06 18:17:48 +00:00
Warner Losh
4df29a25aa 64-bit fixes:
(1) fix printf formats.
(2) Prefer FreeBSD's MIPS_PHYS_TO_KSEG0 to hand-rolled one from Cavium.
(3) Mark a few 64-bit cleanliness issues (possible).
(4) Minor formatting fixes.
2009-07-06 18:15:57 +00:00
Warner Losh
9d7dcb83db Minor fixes to printf formats. 2009-07-06 18:12:49 +00:00
Warner Losh
4b9aa0a973 Prefer uintptr_t to int cast here. 2009-07-06 07:49:24 +00:00
Warner Losh
26b14c6dde Better types for 64-bit compatibility. Use %p and cast to void * and
prefer uintptr_t to other int-type casts.
2009-07-06 07:48:31 +00:00
Warner Losh
f548109087 No need to force mips32 here. 2009-07-06 07:47:39 +00:00
Warner Losh
025e48c64c Pass in the uint64 value, rather than a pointer to it. that's what
the function expects...
2009-07-06 07:46:13 +00:00
Warner Losh
e3c2111d5c Use ta0 instead of t4 and ta1 instead of t5. These map to the same
registers on O32 builds, but t4 and t5 don't exist on N32 or N64.
2009-07-06 07:45:02 +00:00
Warner Losh
10c8cc2b9f Use better casts for passing the small integer as a pointer here.
Basically, replace int with uintptr_t.
2009-07-06 07:43:50 +00:00
Warner Losh
243ab23fcf (1) Improvements for SB1. only allow real memory to be accessed.
(2) make compile n64 by using more-proper casts.

Submitted by:	Neelkanth Natu (1)
2009-07-06 07:42:54 +00:00
Warner Losh
b04ad5dd49 The MCOUNT macro isn't going to work in 64-bit mode. Add a note to
this effect.
2009-07-06 02:27:03 +00:00
Warner Losh
2967976763 Provide a macro for PTR_ADDU as well. We may need to implement this
differently for N32...  Use PTR_ADDU in DO_AST macro.
2009-07-06 02:22:51 +00:00
Warner Losh
54d05c03e5 Change the addu here to daddu.
addu paranoina prodded by: jmallet@
2009-07-06 02:22:06 +00:00
Warner Losh
3eecc82e89 addu and subu are special. We need to use daddu and dsubu here to get
proper behavior.

Submitted by:	jmallet@
2009-07-05 21:16:26 +00:00
Warner Losh
ece5503dbe (1) Use PTR_LA rather than bare la for N64 goodness (it is dla there)
(2) SB1 needs COHERENT policy, not cached for the config register

Submitted by:	(2) Neelkanth Natu
2009-07-05 15:23:54 +00:00
Warner Losh
4f4793e605 use "PTR_LA" in preference to a bare la so it translates to dla on
64-bit ABIs.
2009-07-05 15:22:22 +00:00
Warner Losh
add6da074c Now that we define atomic_{load,store}_64 inline in atomic.h, we don't
need to define them here for the !N64 case.

We now define atomic_readandclear_64 in atomic.h, so no need to repeat
it here.
2009-07-05 15:21:35 +00:00
Warner Losh
bd34d48210 The SB1 has cohernet memory, so add it.
Also, Maxmem is better as a long.

Submitted by:	Neelkanth Natu
2009-07-05 15:20:16 +00:00
Warner Losh
46d854bbdb The SB1 needs a special value for the cache field of the pte.
Submitted by:	Neelkanth Natu
2009-07-05 15:19:28 +00:00
Warner Losh
72322b2318 compute the areas to save registers in for 64-bit access correctly. 2009-07-05 15:18:06 +00:00
Warner Losh
f8b89abb9d First cut at 64-bit types. not 100% sure these are all correct for
N32 ABI.
2009-07-05 15:17:11 +00:00
Warner Losh
8de20ddba8 Trim unreferenced goo. SDRAM likely should be next, but it is still
referenced.
2009-07-05 15:16:27 +00:00
Warner Losh
61a1eed0b4 First cut at atomics for 64-bit machines and SMP machines.
# Note: Cavium provided a port that has atomics similar to these, but
# that does a syncw; sync; atomic; sync; syncw where we just do the classic
# mips 'atomic' operation (eg ll; frob; sc).  It is unclear to me why
# the extra is needed.  Since my initial target is one core, I'll defer
# investigation until I bring up multiple cores.  syncw is an octeon specific
# instruction.
2009-07-05 15:13:24 +00:00
Warner Losh
753b803f71 use %p in preference to 0x%08x for printing register_t values. Cast
them to void * first.  This neatly solves the "how do I print a
register_t" problem because sizeof(void *) is always the same as
sizeof(register_t), afaik.
2009-07-05 15:10:07 +00:00
Warner Losh
2d3c40cf49 Add config file for SWARM board, a sybyte SB-1-based board by
Broadcom.  BCM-91250.

Submitted by:	Neelkanth Natu
2009-07-05 08:40:26 +00:00
Warner Losh
24646e120c Bring in cdefs.h from NetBSD to define ABI goo.
Obtained from:	NetBSD
2009-07-05 08:14:00 +00:00
Warner Losh
0d978536b2 Pull in machine/cdefs.h for the ABI definitions. Provide a PTR_LA,
ala sgi, and use it in preference to a bare 'la' so that it gets
translated to a 'dla' for the 64-bit pointer ABIs.
2009-07-05 08:13:19 +00:00
Warner Losh
f547073088 Use uintptr_t rather than unsigned here for 64-bit correctness. 2009-07-05 07:01:34 +00:00
Warner Losh
da96ff5dae Define __ELF_WORD_SIZE appropriately for n64. Note for N32 I believe
this is correct.  While registers are 64-bit, n32 is a 32-bit ABI and
lives in a 32-bit world (with explicit 64-bit registers, however).
Change an 8, which was 4 + 4 or sizeof(int) + SZREG to be a simple '4
+ SZREG' to reflect the actual offset of the structure in question.
2009-07-05 07:00:51 +00:00
Warner Losh
64003afe2e (1) Use uintptr_t in preference to unsigned. The latter isn't right for
64-bit case, while the former is.

(2) include a SB1 specific coherency mapping

Submitted by:	Neelkanth Nath (2)
2009-07-05 06:56:51 +00:00
Warner Losh
220d1e7fb0 Go for broke: configure this to build mips64 N64 binary. 2009-07-05 06:49:56 +00:00
Warner Losh
bca296cba8 Publish PAGE_SHIFT to assembler
# we should likely phase out PGSHIFT

Submitted by:	Neelkanth Natu
2009-07-05 06:46:54 +00:00
Warner Losh
4ecfc54d9d db_expr_t should be a intptr_t, not an int. These expressions can be
addresses or numbers, and that's a intptr_t if I ever saw one.
2009-07-05 06:44:37 +00:00
Warner Losh
6855d90580 Define COP0_SYNC for SB1 CPU.
Submitted by:	Neelkanth Natu
2009-07-05 06:43:01 +00:00
Warner Losh
2c1c8bb345 Switch to ABI agnostic ta0-ta3. Provide defs for this in the right
places.  Provide n32/n64 register name defintions.  This should have
no effect for the O32 builds that everybody else uses, but should help
make N64 builds possible (lots of other changes are needed for that).

Obtained from:	NetBSD (for the regdef.h changes)
2009-07-05 06:39:37 +00:00
Warner Losh
561a3cc1a1 Move from using the lame invalid address I chose when trying to get
Octeon going...  Turns out that you get tlb shutdowns with this...
Use PGSHIFT instead of PAGE_SHIFT.

Submitted by:	Neelkanth Natu
2009-07-04 03:22:34 +00:00
Warner Losh
f94784e818 Add sibyte device support.
Submitted by:	Neelkanth Natu
2009-07-04 03:05:48 +00:00
Oleksandr Tymoshenko
09c817ba36 - MFC 2009-07-03 04:39:18 +00:00
Warner Losh
ca72c49f42 Fix copyrights to reflect the origin of these files.
Approved by:	re@ (rwatson)
2009-06-29 16:45:50 +00:00
Oleksandr Tymoshenko
fa596cbd83 - Replace casuword and casuword32 stubs with proper implementation 2009-06-28 21:01:00 +00:00
Oleksandr Tymoshenko
00741bfc80 - Add support for handling TLS area address in kernel space.
From the userland point of view get/set operations are
    performed using sysarch(2) call.
2009-06-27 23:27:41 +00:00
Oleksandr Tymoshenko
a79d8960b1 - Make cpu_set_upcall_kse conform MIPS ABI. T9 should be
the same as PC in subroutine entry point
- Preserve interrupt mask
2009-06-27 23:01:35 +00:00
Oleksandr Tymoshenko
5576af82b5 - Add guards to ensure that these files are included only once 2009-06-26 19:54:06 +00:00
Alan Cox
5797795f5a Correct the #endif comment.
Noticed by:	jmallett
Approved by:	re (kib)
2009-06-26 16:22:24 +00:00
Robert Watson
eb956cd041 Use if_maddr_rlock()/if_maddr_runlock() rather than IF_ADDR_LOCK()/
IF_ADDR_UNLOCK() across network device drivers when accessing the
per-interface multicast address list, if_multiaddrs.  This will
allow us to change the locking strategy without affecting our driver
programming interface or binary interface.

For two wireless drivers, remove unnecessary locking, since they
don't actually access the multicast address list.

Approved by:	re (kib)
MFC after:	6 weeks
2009-06-26 11:45:06 +00:00
Alan Cox
e999111ae7 This change is the next step in implementing the cache control functionality
required by video card drivers.  Specifically, this change introduces
vm_cache_mode_t with an appropriate VM_CACHE_DEFAULT definition on all
architectures.  In addition, this changes adds a vm_cache_mode_t parameter
to kmem_alloc_contig() and vm_phys_alloc_contig().  These will be the
interfaces for allocating mapped kernel memory and physical memory,
respectively, with non-default cache modes.

In collaboration with:	jhb
2009-06-26 04:47:43 +00:00
Oleksandr Tymoshenko
77edcd641c - Invalidate cache in pmap_qenter. Fixes corruption of data
that comes through pipe (may be other bugs)
2009-06-25 02:15:04 +00:00
Oleksandr Tymoshenko
790b067725 - Do not use hardcoded uart speed
- Call mips_timer_early_init before initializing uart in order
    to make DELAY usable for ns8250 driver

Submitted by:	Neelkanth Natu
2009-06-24 22:42:52 +00:00
Jeff Roberson
50c202c592 Implement a facility for dynamic per-cpu variables.
- Modules and kernel code alike may use DPCPU_DEFINE(),
   DPCPU_GET(), DPCPU_SET(), etc. akin to the statically defined
   PCPU_*.  Requires only one extra instruction more than PCPU_* and is
   virtually the same as __thread for builtin and much faster for shared
   objects.  DPCPU variables can be initialized when defined.
 - Modules are supported by relocating the module's per-cpu linker set
   over space reserved in the kernel.  Modules may fail to load if there
   is insufficient space available.
 - Track space available for modules with a one-off extent allocator.
   Free may block for memory to allocate space for an extent.

Reviewed by:    jhb, rwatson, kan, sam, grehan, marius, marcel, stas
2009-06-23 22:42:39 +00:00
Oleksandr Tymoshenko
e3ebc7a32e - Keep interrupts mask intact by RESTORE_CPU in MipsKernGenException
trap() function re-enables interrupts if exception happened with
    interrupts enabled and therefor status register might be modified
    by interrupt filters
2009-06-19 19:02:40 +00:00