required by video card drivers. Specifically, this change introduces
vm_cache_mode_t with an appropriate VM_CACHE_DEFAULT definition on all
architectures. In addition, this changes adds a vm_cache_mode_t parameter
to kmem_alloc_contig() and vm_phys_alloc_contig(). These will be the
interfaces for allocating mapped kernel memory and physical memory,
respectively, with non-default cache modes.
In collaboration with: jhb
- Modules and kernel code alike may use DPCPU_DEFINE(),
DPCPU_GET(), DPCPU_SET(), etc. akin to the statically defined
PCPU_*. Requires only one extra instruction more than PCPU_* and is
virtually the same as __thread for builtin and much faster for shared
objects. DPCPU variables can be initialized when defined.
- Modules are supported by relocating the module's per-cpu linker set
over space reserved in the kernel. Modules may fail to load if there
is insufficient space available.
- Track space available for modules with a one-off extent allocator.
Free may block for memory to allocate space for an extent.
Reviewed by: jhb, rwatson, kan, sam, grehan, marius, marcel, stas
driver's i/o ops must be locked to avoid chaos. Extend the cambria
bus tag to support ata and add a spin lock. The ata driver is
hacked to use that instead of it's builtin hack for ixp425. Once
the ata driver is fixed to not be confused about byte order we can
generalize the cambria bus tag code and make it generally useful.
While here take advantage of our being ixp435-specific to remove
delays when switching between byte+word accesses and to eliminate
the 2us delay for the uarts (the spin lock overhead looks to do
this for us).
used for the optional GPS+RS485 uarts on the Gateworks Cambria boards
which otherwise are unreliable
o setup the hack bus space tag for the GPS+RS485 uarts
o program the gpio interrupts for the uarts to be edge-rising
o force timing on the expansion bus for the uarts to be "slow"
Thanks to Chris Lang of Gateworks for these tips.
structure. When the page is shared, the kernel mapping becomes a special
type of managed page to force the cache off the page mappings. This is
needed to avoid stale entries on all ARM VIVT caches, and VIPT caches
with cache color issue.
Submitted by: Mark Tinguely
Reviewed by: alc
Tested by: Grzegorz Bernacki, thompsa
causes both to become inoperative; this apparently was done by the original
IAL code as a workaround for IMEM parity errors which we've not seen so
just disable the reset.
Note this problem does not occur on IXP425 boards. The linux driver does
fuse-resets on each NPE but in the order NPE-A < NPE-B < NPE-C (when probing
for which NPE's are present/operational); we may want to switch to a similar
scheme but for now disable the resets until we see an issue.
normally taken from the hints file so this should have no effect
o set the port address "just in case"
o add NPE-A support to the tx done qmgr callback
so that it isn't exposured unless needed. In particular this means
that it's easier to tune the memory layout based on board details.
While here, remove inclusion of <machine/intr.h> from mvreg.h. This
also contains exposure to SoC specifics in MI drivers, because NIRQ
depends on the SoC.
the implementation can guarantee forward progress in the event of
a stuck interrupt or interrupt storm. This is especially critical
for fast interrupt handlers, as they can cause a hard hang in that
case. When first called, arm_get_next_irq() is passed -1.
Obtained from: Juniper Networks, Inc.
When pages are removed from virtual address space by calling pmap_remove_all()
CPU caches were not invalidated, which led to read corruption when another
page got mapped at this same virtual address at later time (the CPU was
retrieving stale contents).
Submitted by: Piotr Ziecik
Obtained from: Semihalf
CPU for too long period than necessary. Additively, interfaces are kept
polled (in the tick) even if no more packets are available.
In order to avoid such situations a new generic mechanism can be
implemented in proactive way, keeping track of the time spent on any
packet and fragmenting the time for any tick, stopping the processing
as soon as possible.
In order to implement such mechanism, the polling handler needs to
change, returning the number of packets processed.
While the intended logic is not part of this patch, the polling KPI is
broken by this commit, adding an int return value and the new flag
IFCAP_POLLING_NOCOUNT (which will signal that the return value is
meaningless for the installed handler and checking should be skipped).
Bump __FreeBSD_version in order to signal such situation.
Reviewed by: emaste
Sponsored by: Sandvine Incorporated
The system hostname is now stored in prison0, and the global variable
"hostname" has been removed, as has the hostname_mtx mutex. Jails may
have their own host information, or they may inherit it from the
parent/system. The proper way to read the hostname is via
getcredhostname(), which will copy either the hostname associated with
the passed cred, or the system hostname if you pass NULL. The system
hostname can still be accessed directly (and without locking) at
prison0.pr_host, but that should be avoided where possible.
The "similar information" referred to is domainname, hostid, and
hostuuid, which have also become prison parameters and had their
associated global variables removed.
Approved by: bz (mentor)
possible future I-cache coherency operation can succeed. On ARM
for example the L1 cache can be (is) virtually mapped, which
means that any I/O that uses temporary mappings will not see the
I-cache made coherent. On ia64 a similar behaviour has been
observed. By flushing the D-cache, execution of binaries backed
by md(4) and/or NFS work reliably.
For Book-E (powerpc), execution over NFS exhibits SIGILL once in
a while as well, though cpu_flush_dcache() hasn't been implemented
yet.
Doing an explicit D-cache flush as part of the non-DMA based I/O
read operation eliminates the need to do it as part of the
I-cache coherency operation itself and as such avoids pessimizing
the DMA-based I/O read operations for which D-cache are already
flushed/invalidated. It also allows future optimizations whereby
the bcopy() followed by the D-cache flush can be integrated in a
single operation, which could be implemented using on-chips DMA
engines, by-passing the D-cache altogether.
registers contents.
- Use memory barriers to preserve the order of buffer space operations.
This might be needed if we'll ever use this driver on architectures
where ordering is not guaranteed.
used in some cases):
- Ignore DMA tag boundaries when allocating bounce pages. The boundaries
don't determine whether or not parts of a DMA request bounce. Instead,
they are just used to carve up segments.
- Allow tags with sub-page alignment to share bounce pages since bounce
pages are always page aligned.
Reviewed by: scottl (amd64)
MFC after: 1 month
operates in the common memory mode and use polling mode to control
the status of operations as I don't have any board with interrupt
line routed yet. I'll add the GPIO interrupt driven mode as soon
as I get one.
respectivly. This will allow one to have a kernel with both devices
present and use it for multiple boards with different types of RTC
sitting on a bus.
Discussed with: imp
a fair number of static data structures, making this an unlikely
option to try to change without also changing source code. [1]
Change default cache line size on ia64, sparc64, and sun4v to 128
bytes, as this was what rtld-elf was already using on those
platforms. [2]
Suggested by: bde [1], jhb [2]
MFC after: 2 weeks
CACHE_LINE_SIZE constant. These constants are intended to
over-estimate the cache line size, and be used at compile-time
when a run-time tuning alternative isn't appropriate or
available.
Defaults for all architectures are 64 bytes, except powerpc
where it is 128 bytes (used on G5 systems).
MFC after: 2 weeks
Discussed on: arch@
a tag that has BUS_DMA_KEEP_PG_OFFSET set. Otherwise the page could be
reused with a non-zero offset by a tag that doesn't have
BUS_DMA_KEEP_PG_OFFSET leading to data corruption.
Sleuthing by: avg
Reviewed by: scottl
at91_udp.c does not exist anymore, it is now replaced by at91dci in
src/sys/dev/usb/controller. Also remove the ohci_atmelarm.c because it is also
included in src/sys/conf/files
Submitted by: Sylvestre Gallon
1) Move the new field (brand_note) to the end of the Brandinfo structure.
2) Add a new flag BI_BRAND_NOTE that indicates that the brand_note pointer
is valid.
3) Use the brand_note field if the flag BI_BRAND_NOTE is set and as old
modules won't have the flag set, so the new field brand_note would be
ignored.
Suggested by: jhb
Reviewed by: jhb
Approved by: kib (mentor)
MFC after: 6 days
but I see no benefit from it today.
VM_PROT_READ_IS_EXEC was only intended for use on processors that do not
distinguish between read and execute permission. On an mmap(2) or
mprotect(2), it automatically added execute permission if the caller
specified permissions included read permission. The hope was that this
would reduce the number of vm map entries needed to implement an address
space because there would be fewer neighboring vm map entries that differed
only in the presence or absence of VM_PROT_EXECUTE. (See vm/vm_mmap.c
revision 1.56.)
Today, I don't see any real applications that benefit from
VM_PROT_READ_IS_EXEC. In any case, vm map entries are now organized
as a self-adjusting binary search tree instead of an ordered list. So,
the need for coalescing vm map entries is not as great as it once was.
to the virtual one. I may had a reason at some point to use the later, but
can't remember which, and it can leads to issues.
Reported by: Guillaume Ballet <gballet gmail com>
o call ieee80211_encap in ieee80211_start so frames passed down to drivers
are already encapsulated
o remove ieee80211_encap calls in drivers
o fixup wi so it recreates the 802.3 head it requires from the 802.11
header contents
o move fast-frame aggregation from ath to net80211 (conditional on
IEEE80211_SUPPORT_SUPERG):
- aggregation is now done in ieee80211_start; it is enabled when the
packets/sec exceeds ieee80211_ffppsmin (net.wlan.ffppsmin) and frames
are held on a staging queue according to ieee80211_ffagemax
(net.wlan.ffagemax) to wait for a frame to combine with
- drivers must call back to age/flush the staging queue (ath does this
on tx done, at swba, and on rx according to the state of the tx queues
and/or the contents of the staging queue)
- remove fast-frame-related data structures from ath
- add ieee80211_ff_node_init and ieee80211_ff_node_cleanup to handle
per-node fast-frames state (we reuse 11n tx ampdu state)
o change ieee80211_encap calling convention to include an explicit vap
so frames coming through a WDS vap are recognized w/o setting M_WDS
With these changes any device able to tx/rx 3Kbyte+ frames can use fast-frames.
Reviewed by: thompsa, rpaulo, avatar, imp, sephe
driver in Linux 2.6. uscanner was just a simple wrapper around a fifo and
contained no logic, the default interface is now libusb (supported by sane).
Reviewed by: HPS
to the full path of the image that is being executed.
Increase AT_COUNT.
Remove no longer true comment about types used in Linux ELF binaries,
listed types contain FreeBSD-specific entries.
Reviewed by: kan
".note.ABI-tag" section.
The search order of a brand is changed, now first of all the
".note.ABI-tag" is looked through.
Move code which fetch osreldate for ELF binary to check_note() handler.
PR: 118473
Approved by: kib (mentor)
operate on the resource (we have no local resources to manage); this
fixes drivers that alloc/release resources in their probe method and
then do it again in attach
o while here add some prints to catch failures and massage style a bit
o encode need for A4 bus space tag hackery according to the memory
address; checking for "uart" breaks down with the GPS chip support
which is also a uart but does not require the same hackery
o encode the correct memory window instead of carving up all of i/o
space, potentially with a larger window than a device should have;
this likely should be handled in the drivers by using a proper bus
alloc call but since some drivers depend on the bus support to figure
this out we cannot simply mod them
o add optional GPS and RS485 support (conditionally as the support
isn't ready yet)
o improves understandability by replacing numerous relative address
calculations with fixed addresses; everything should now match up
more easily with the vm layout shown at the top of the file
o move the expansion bus chip select regions to be contiguous with
the expansion bus configuration area; this is not exploited right
now but allows map consolidation in the future
o leave a gap between the expansion bus regions and the pci config
space in case we want to map more exp bus cs regions
Reviewed by: imp, thompsa
usb stack rather than with the rest of the processor support code.
Not sure that's a good idea, as we were moving away from it, but this
fixes the build in the mean time so we can have that discussion.
the same dma tag. However, it can happen multiple dma tags share the same
bounce zone too, so add a per-bounce zone map counter, and check it instead of
the dma tag map counter, to know if we have to alloc more pages.
Reported by: miwi
Reviewed by: scottl
offset. This is needed for the ehci hardware buffer rings that assume
this behavior.
This is an interim solution, and a more general one is being worked
on. This solution doesn't break anything that doesn't ask for it
directly. The mbuf and uio variants with this flag likely don't work
and haven't been tested.
Universe builds with these changes. I don't have a huge-memory
machine to test these changes with, but will be happy to work with
folks that do and hps if this changes turns out not to be sufficient.
Submitted by: alfred@ from Hans Peter Selasky's original
o add bus shim for cfi driver
o add static mapping for CS0 (we map all 16M as the cfi driver doesn't
support demand mapping)
Note this needs some tweaking to work for 2358 boards which is why the
CAMBRIA config is not touched.
rather than a fixed 512... This fixes the mount root problem on at91.
Prior to the SD card reorg, all data transfers were 512 bytes, so we
didn't notice.
the serial port class when we set the devclass since it is now
no-longer a compile time constant. Eliminate the pci include, as it
isn't relevant or necessary.
time constant. This allows us to potentially change it at runtime or
autodetect it early in the boot (the latter being much more likely to
have a good outcome).
o Only set 4-bit caps on those boards that have 4-bit caps (this means that
because we don't set wire4 yet, this forces us to always use 1-bit bus).
o Don't test wire4 when setting up the bus width, since bad things will
happen if we do.
# This likely won't fix the busted at91 sd card support, but these are
# needful changes for correctness.
- The contents of 'feroceon_cpufuncs' dispatch table was really dedicated for the
new Sheeva CPU (in 88F6xxx and MV-78xxx SOCs), and NOT Feroceon.
- Feroceon CPU (in 88F5xxx SOCs) appears as a regular ARM926EJ-S core and does
not require dedicated routines.
This will be accompanied by a file rename commit.
- Provide dedicated rmans for MEM and IO resources.
- Convert PCI IRQ routing info into a table (from callback approach), provide
config data for alternative DB- boards.
- Fix a wrong boundary check error in pcib_mbus_init_bar()
Obtained from: Semihalf
- Allow for setting per platform MPP/GPIO configuration in the kernel, so
that we can override all settings firmware might set.
- Set decode windows for the remaining on-chip peripherals: CESA, SATA and XOR.
- Improve handling of USB controllers so that all port are available on the
given SOC/platform (e.g. up to three on DB-78xxx), this includes rework of
USB decode windows set-up.
- Other minor fixes and cosmetics.
Obtained from: Semihalf
- Clean up TCLK handling so that it's dynamically recognized depending on
registers settings or chip version/revision. Update registers definitions.
- Teach SOC ident routine about A0 (initial silicon version for general
audience)
Obtained from: Marvell, Semihalf
options. Using the already included std.avila is not considered
to be entirely right (and the options slightly differ) but the best
match we currently have. Upcoming work should fit better.
Reorder another variable to match the layout of other configs.
Reviewed by: sam, warner (earlier version with options removed)
FPA floating-point format is identical to the VFP format,
but is always stored in big-endian.
Introduce _IEEE_WORD_ORDER to describe the byte-order of
the FP representation.
Obtained from: Juniper Networks, Inc
o check feature bits when probing NPE ethernet support
o move firmware loading logic from if_npe to core npe support
o allow multiple refs to core NPE driver
o while here fix hw.npe.debug tunable path
o add definitions for more bits, for masking out IXP465-specific bits,
and %b format string
o add ixp4xx_read_feature_bits to retrieve the mask of valid features
(aka fuse bits)
o add cpu_is_ixp42x() macro
o print feature bits at boot
o add support for IXP435 cpu's (e.g. 64 irq's)
o add support for Cambria-specific devices: npe, led's (front panel and
octal latch), ehci, mcu, ide cf
o redo memory mapping for xscale/ixp4xx boards: previously memory
was assumed aliased to 0x10000000 but this appears to be true only
for ixp425 systems and breaks operation on others; rework so memory
is assumed to start at 0
o rework NPE configuration support to use NPE id's instead of port #'s;
these changes also rename the associated MAC's to follow the NPE's
they are attached to
o update npe firmware to latest rev (same license) and update default fw
imageid's to match; in particular this adds NPE-A and crypto support
o re-style NPE fw handling code and add a console msg identifying the
attributes of the loaded fw
o fix numerous problems with handling failures during npe setup
o fix npe rx q setup; need to spin waiting for mailbox responses during
early boot stages as qmgr interrupts are not delivered; this fixes
the problem where all 8 traffic classifications were not tied to the
rx q (and eliminates the console msg "remember to fix rx q setup")
o add DELAY to npe MII wait logic for IXP435
o strip down builtin phys->virt address translation table in resource
handling to just those resources that require it and add a console msg
to alert people when this (kludge) table needs to be extended
o purge a bunch of dead netbsd-ism's
o cleanup avila led driver
o add Cambria support to boot2 and rework code for better multi-board support
Notes:
1. NPE-A doesn't work and causes NPE-C to stop working; it is disabled
in the hints
2. USB isn't working yet; controller communicates ok but device
discovery fails
3. Cambria support must be configured separately from IXP425 boards;
multi-board support is TBD
Sponsored by: Hobnob, Gateworks (board donation)
Reviewed by: imp
o recognize ixp435 cpu
o change memory layout for for ixp4xx to not assume memory is aliases
to 0x10000000 (Cambria/ixp435 memory starts at zero)
o handle 64 irqs for ixp435
o dual EHCI USB 2.0 controller integral to ixp435
o overhaul NPE code for ixp435 and better MAC+MII naming
o updated NPE firmware (including NPE-A image for ixp435/ixp465)
o Gateworks Cambria board support:
- IDE compact flash
- MCU
- front panel LED on i2c bus
- Octal LED latch
Sanity-tested with NFS-root on Avila and Cambria boards. Requires
pending boot2 mods for CF-boot on Cambria.
module; the ath module now brings in the hal support. Kernel
config files are almost backwards compatible; supplying
device ath_hal
gives you the same chip support that the binary hal did but you
must also include
options AH_SUPPORT_AR5416
to enable the extended format descriptors used by 11n parts.
It is now possible to control the chip support included in a
build by specifying exactly which chips are to be supported
in the config file; consult ath_hal(4) for information.
contents.
- It is possible to override the dynamic configuration by using
AT91C_MAIN_CLOCK option in kernel config.
PR: arm/128961 (based on)
Submitted by: Bjorn Konig <bkoenig@alpha-tierchen.de>
Reviewed by: imp
Approved by: kib (mentor, implicit)
o Copy kb920x_machdep.c to at91_machdep.c
o Move board_init to new board_kb920x.c
o rename ramsize to at91_ramsize and make it accessible to board_* files.
o Delete files.kb920x. We can do this selection with the new boards.
o Add a stub for the tsc4370 board init, which will be added in
a future commit.
o Add new 'devices' at91_board_kb920x and at91_board_tsc4370. More are
needed and will be added in future commits.
Reviewed by: stass, cognet
of the ABI of the currently executing image. Change some places to test
the flags instead of explicit comparing with address of known sysentvec
structures to determine ABI features.
Discussed with: dchagin, imp, jhb, peter
and ifnet functions
- add memory barriers to <machine/atomic.h>
- update drivers to only conditionally define their own
- add lockless producer / consumer ring buffer
- remove ring buffer implementation from cxgb and update its callers
- add if_transmit(struct ifnet *ifp, struct mbuf *m) to ifnet to
allow drivers to efficiently manage multiple hardware queues
(i.e. not serialize all packets through one ifq)
- expose if_qflush to allow drivers to flush any driver managed queues
This work was supported by Bitgravity Inc. and Chelsio Inc.
sdhci supports up to 65535 blocks transfers, at91_mci - one block.
Enable multiblock operations disabled before to follow at91_mci driver
limitations.
Reviewed by: imp@
machine arm
device mem
options GEOM_BSD
options GEOM_MBR
Remove the first two from all kernel configuration files and
change geom_bsd and geom_mbr from standard to optional.
This uses the common U-Boot support lib (sys/boot/uboot, already used on
FreeBSD/powerpc), and assumes the underlying firmware has the modern API for
stand-alone apps enabled in the config (CONFIG_API).
Only netbooting is supported at the moment.
Obtained from: Marvell, Semihalf
FreeBSD 8-CURRENT was tested and run successfully on the following eval
boards and devices :
* DB-88F5182, DB-88F5281 (Orion based)
* DB-88F6281, RD-88F6281 (Kirkwood based)
* DB-78100 (Discovery based)
For more detailed info on build instructions and other examples please refer
to http://wiki.freebsd.org/FreeBSDMarvell
Obtained from: Marvell, Semihalf
* Orion
- 88F5181
- 88F5182
- 88F5281
* Kirkwood
- 88F6281
* Discovery
- MV78100
The above families of SOCs are built around CPU cores compliant with ARMv5TE
instruction set architecture definition. They share a number of integrated
peripherals. This commit brings support for the following basic elements:
* GPIO
* Interrupt controller
* L1, L2 cache
* Timers, watchdog, RTC
* TWSI (I2C)
* UART
Other peripherals drivers will be introduced separately.
Reviewed by: imp, marcel, stass (Thanks guys!)
Obtained from: Marvell, Semihalf
The physical page which we clear is accessed via additional temp kernel
mapping for the period of zeroing operation. However in systems with virtual
d-cache (most ARMs) when write-allocate feature is enabled, we can have
modified but unflushed content pertaining to this physical page still in the
d-cache due to its primary (pre-existing) mapping. In such scenario that
cached content upon flush is likely to overwrite [portions of] the physical
page we want to zero here..
This is a general problem with multiple virtual mappings covering the same
physical page with write-allocate and virtual d-cache: there is inherent
potential for corruptions of this kind, which are not easily resolved; it is
best policy that such multiple mappings be not allowed.
Obtained from: Marvell, Semihalf
