Commit Graph

865 Commits

Author SHA1 Message Date
rwatson
bdee30611d Add a new 'why' argument to kdb_enter(), and a set of constants to use
for that argument.  This will allow DDB to detect the broad category of
reason why the debugger has been entered, which it can use for the
purposes of deciding which DDB script to run.

Assign approximate why values to all current consumers of the
kdb_enter() interface.
2007-12-25 17:52:02 +00:00
stas
cf2788b769 - Fix a typo in comments.
MFC after:	1 week
Approved by:	cognet
2007-12-23 23:31:27 +00:00
imp
93ea7f3594 Actually program the interrupt controller for priorities. As we
support more AT91 platforms, we'll need to move this into some
platform init routine.
2007-12-19 17:34:17 +00:00
kevlo
f3f1d0b3a5 Use M_NOWAIT instead of M_WAITOK to cause malloc() to return NULL
Reviewed by: imp
2007-12-17 05:08:54 +00:00
stas
10ac9b50a2 - Don't return 0xffff if PHY id isn't equal 0. This allows PHYs with
non-zero addresses to be used.

Approved by:	cognet
MFC after:	2 weeks
2007-12-16 12:57:12 +00:00
cognet
eb33bdbe0e There's no need to call pmap_vac_me_harder() in pmap_protect(), as it
already happened in pmap_modify_pv().

Submitted by:	Mark Tinguely <tinguely AT casselton DOT net>
2007-12-11 20:35:44 +00:00
jkoshy
39d4b4accf Add stubs to unbreak LINT. 2007-12-07 13:45:47 +00:00
cognet
b76f135a28 Fix style in previous commit.
Pointed out by:	njl
2007-12-07 10:42:11 +00:00
cognet
f919b8c32d Erm, add a missing else, we do not want to increase the mapping counters for
both kernel and userland when we create a pv for pmap_kernel.

Reported by:	Mark Tinguely <tinguely AT casselton DOT net>
MFC After:	3 days
2007-12-06 23:17:24 +00:00
rwatson
99285f7544 Break out stack(9) from ddb(4):
- Introduce per-architecture stack_machdep.c to hold stack_save(9).
- Introduce per-architecture machine/stack.h to capture any common
  definitions required between db_trace.c and stack_machdep.c.
- Add new kernel option "options STACK"; we will build in stack(9) if it is
  defined, or also if "options DDB" is defined to provide compatibility
  with existing users of stack(9).

Add new stack_save_td(9) function, which allows the capture of a stacktrace
of another thread rather than the current thread, which the existing
stack_save(9) was limited to.  It requires that the thread be neither
swapped out nor running, which is the responsibility of the consumer to
enforce.

Update stack(9) man page.

Build tested:	amd64, arm, i386, ia64, powerpc, sparc64, sun4v
Runtime tested:	amd64 (rwatson), arm (cognet), i386 (rwatson)
2007-12-02 20:40:35 +00:00
cognet
9e1fb6a88b Fix a potential bug in pmap :
We used to allocate the domains 0-14 for userland, and leave the domain 15
for the kernel. Now supersections requires the use of domain 0, so we
switched the kernel domain to 0, and use 1-15 for userland.
How it's done currently, the kernel domain could be allocated for a
userland process.
So switch back to the previous way we did things, set the first available
domain to 0, and just add 1 to get the real domain number in the struct pmap.

Reported by:	Mark Tinguely <tinguely AT casselton DOT net>
MFC After:	3 days
2007-12-02 15:26:30 +00:00
cognet
375dcebc07 Move the strongarm-specific files from conf/files.arm to sa11x0/files.sa11xO.
Submitted by:	Rafal Jaworowski <raj AT semihalf DOT com>
2007-12-02 13:12:21 +00:00
cognet
507e28d936 Cleanup : make nexus standard, as it is mandatory anyway.
Garbage-collect unused nexus_io.c and nexus_io_asm.S

Submitted by:	Rafal Jaworowski <raj AT semihalf DOT com>
2007-12-02 13:10:42 +00:00
cognet
db18da5d15 Close a race.
The RAS implementation would set the end address, then the start
address.  These were used by the kernel to restart a RAS sequence if
it was interrupted.  When the thread switching code ran, it would
check these values and adjust the PC and clear them if it did.

However, there's a small flaw in this scheme.  Thread T1, sets the end
address and gets preempted.  Thread T2 runs and also does a RAS
operation.  This resets end to zero.  Thread T1 now runs again and
sets start and then begins the RAS sequence, but is preempted before
the RAS sequence executes its last instruction.  The kernel code that
would ordinarily restart the RAS sequence doesn't because the PC isn't
between start and 0, so the PC isn't set to the start of the sequence.
So when T1 is resumed again, it is at the wrong location for RAS to
produce the correct results.  This causes the wrong results for the
atomic sequence.

The window for the first race is 3 instructions.  The window for the
second race is 5-10 instructions depending on the atomic operation.
This makes this failure fairly rare and hard to reproduce.

Mutexs are implemented in libthr using atomic operations.  When the
above race would occur, a lock could get stuck locked, causing many
downstream problems, as you might expect.

Also, make sure to reset the start and end address when doing a syscall, or
a malicious process could set them before doing a syscall.

Reviewed by: imp, ups (thanks guys)
Pointy hat to:	cognet
MFC After:	3 days
2007-12-02 12:49:28 +00:00
cognet
55fd7467ec Fixes for ARM9/ARM10 :
Call uma_sel_align() there at well.
Set CPU_CONTROL_VECRELOC if we're using the high vectors page.

Submitted by:	Rafal Jaworowski <raj AT semihalf DOT com>
MFC After:	1 week
2007-11-28 22:55:55 +00:00
cognet
77643d0653 Correct the logic : we can just invalidate the cache lines, and not
write-back them, only if PREWRITE is not set, and if the buffer is
cache-line aligned.

MFC After:	1 week
2007-11-28 22:21:17 +00:00
cognet
8ee5104341 In atomic_fetchadd_32(), do not blindly increase the value of %3.
It should just contain the value we want to add, as if we're interrupted
between the add and the str, we will restart from the beginning. Just use
a register we can scratch instead.

MFC After:	1 week
2007-11-27 22:12:05 +00:00
jhb
7fe785218b Remove the 'needbounce' variable from the _bus_dmamap_load_buffer()
routine.  It is not needed as the existing tests for segment coalescing
already handle bounced addresses and it prevents legal segment coalescing
in certain edge cases.

MFC after:	1 week
Reviewed by:	scottl
2007-11-27 17:28:12 +00:00
alc
d1ab859bdc Prevent the leakage of wired pages in the following circumstances:
First, a file is mmap(2)ed and then mlock(2)ed.  Later, it is truncated.
Under "normal" circumstances, i.e., when the file is not mlock(2)ed, the
pages beyond the EOF are unmapped and freed.  However, when the file is
mlock(2)ed, the pages beyond the EOF are unmapped but not freed because
they have a non-zero wire count.  This can be a mistake.  Specifically,
it is a mistake if the sole reason why the pages are wired is because of
wired, managed mappings.  Previously, unmapping the pages destroys these
wired, managed mappings, but does not reduce the pages' wire count.
Consequently, when the file is unmapped, the pages are not unwired
because the wired mapping has been destroyed.  Moreover, when the vm
object is finally destroyed, the pages are leaked because they are still
wired.  The fix is to reduce the pages' wired count by the number of
wired, managed mappings destroyed.  To do this, I introduce a new pmap
function pmap_page_wired_mappings() that returns the number of managed
mappings to the given physical page that are wired, and I use this
function in vm_object_page_remove().

Reviewed by: tegge
MFC after: 6 weeks
2007-11-17 22:52:29 +00:00
cognet
5d2d26ed5f Add a kernel config file for the Hot-e HL200 (AT91RM92 based).
Many thanks to John Nicholls from Thinklinx for sending sample hardware.
2007-11-17 17:25:22 +00:00
marcel
1e7c4f0a3f o Rename cpu_thread_setup() to cpu_thread_alloc() to better
communicate that it relates to (is called by) thread_alloc()
o  Add cpu_thread_free() which is called from thread_free()
   to counter-act cpu_thread_alloc().

i386:	Have cpu_thread_free() call cpu_thread_clean() to
	preserve behaviour.
ia64:	Have cpu_thread_free() call mtx_destroy() for the
	mutex initialized in cpu_thread_alloc().

PR: ia64/118024
2007-11-14 20:21:54 +00:00
julian
b2732e0c22 generally we are interested in what thread did something as
opposed to what process. Since threads by default have teh name of the
process unless over-written with more useful information, just print the
thread name instead.
2007-11-14 06:21:24 +00:00
cognet
6d7755ffed Add entries for the L2 cache-related functions for armv5.
Spotted out by: Rafal Jaworowski
2007-11-08 13:19:08 +00:00
kib
9ae733819b Fix for the panic("vm_thread_new: kstack allocation failed") and
silent NULL pointer dereference in the i386 and sparc64 pmap_pinit()
when the kmem_alloc_nofault() failed to allocate address space. Both
functions now return error instead of panicing or dereferencing NULL.

As consequence, vmspace_exec() and vmspace_unshare() returns the errno
int. struct vmspace arg was added to vm_forkproc() to avoid dealing
with failed allocation when most of the fork1() job is already done.

The kernel stack for the thread is now set up in the thread_alloc(),
that itself may return NULL. Also, allocation of the first process
thread is performed in the fork1() to properly deal with stack
allocation failure. proc_linkup() is separated into proc_linkup()
called from fork1(), and proc_linkup0(), that is used to set up the
kernel process (was known as swapper).

In collaboration with:	Peter Holm
Reviewed by:	jhb
2007-11-05 11:36:16 +00:00
cognet
39bac9265d Remove a staled comment, NPE-C should work fine.
Reviewed by:	sam
2007-11-04 21:54:52 +00:00
kevlo
ad6bad8ed6 __CPU_XSCALE_PXA2XX -> CPU_XSCALE_PXA2X0 2007-11-01 10:01:15 +00:00
kevlo
be94908799 Don't define get_cachetype() for CPU_ARM9E unless it's going to be used. 2007-10-31 07:27:31 +00:00
imp
b1a850ab26 kill commented out line of code. 2007-10-29 21:01:50 +00:00
cognet
bf5c2ef02d Add an option to be able to override the value of the AT91 master clock
frequency. It'd be better to be able to calculate it at runtime, but we need
the information very early, to setup the uart.
2007-10-25 23:02:42 +00:00
cognet
5ddc0ba134 Move some KB920x-specific options into the KB920x file. 2007-10-25 22:57:19 +00:00
cognet
638dd6acb3 Oooops, get the end of the memory right. 2007-10-25 22:43:17 +00:00
cognet
721d638714 KERNBASE should really be KERNVIRTADDR there too.
MFC after:	1 week
2007-10-24 23:41:46 +00:00
cognet
bdb3b0ffe4 In ate_get_mac(), try to get the mac address in the right order, at least
in the same order as it's set in ate_set_mac.
I remember a discussion about this on -arm, but apparently nothing was done.
Warner, is this wrong ?

X-MFC After:	proper review
2007-10-24 23:12:19 +00:00
cognet
bd28207484 Handle the case where PHYSADDR != KERNPHYSADDR (ie we do not load the kernel
at the beginning of the RAM).

MFC After:	1 week
2007-10-24 22:26:54 +00:00
cognet
b1ea6b3ec3 Correct a comment, this was not true anymore. 2007-10-24 22:24:32 +00:00
imp
31191feb7a correct guard variable names. 2007-10-18 05:43:44 +00:00
imp
003f26732c Merge support from p4 (from NetBSD) for arm9e and arm10, arm11 cores. Not
yet connected to the build, but reduces diffs to p4 repo.

Obtained from: NetBSD
2007-10-18 05:33:06 +00:00
imp
7df4171529 Merge definitions for ARM9E, ARM10 and ARM11 processors from p4 (which
got them from NetBSD).
2007-10-18 05:06:58 +00:00
cognet
6d62ad229e Use the direct mapping, if available, for pmap_zero_page_xscale() as well. 2007-10-16 20:40:04 +00:00
cognet
23ec7d7ba3 Do not use __XSCALE__ to detect if pld/strd/ldrd is available, use
_ARM_ARCH_5E instead.

MFC After:	3 days
2007-10-13 12:05:03 +00:00
cognet
66c3bb340b Define _ARM_ARCH_5E too, so that we know if pld/strd/ldrd are available.
MFC After:	3 days
2007-10-13 12:04:10 +00:00
kevlo
7a9f1e285b Spelling fix for interupt -> interrupt 2007-10-12 06:03:46 +00:00
marius
d60b8a3096 Make the PCI code aware of PCI domains (aka PCI segments) so we can
support machines having multiple independently numbered PCI domains
and don't support reenumeration without ambiguity amongst the
devices as seen by the OS and represented by PCI location strings.
This includes introducing a function pci_find_dbsf(9) which works
like pci_find_bsf(9) but additionally takes a domain number argument
and limiting pci_find_bsf(9) to only search devices in domain 0 (the
only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are
changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order
to no longer report false positives when searching for siblings and
dupe devices in the same domain respectively.
Along with this change the sole host-PCI bridge driver converted to
actually make use of PCI domain support is uninorth(4), the others
continue to use domain 0 only for now and need to be converted as
appropriate later on.
Note that this means that the format of the location strings as used
by pciconf(8) has been changed and that consumers of <sys/pciio.h>
potentially need to be recompiled.

Suggested by:	jhb
Reviewed by:	grehan, jhb, marcel
Approved by:	re (kensmith), jhb (PCI maintainer hat)
2007-09-30 11:05:18 +00:00
cognet
63a24fc32d Ok I hope I got it right this time.
After discussion with Sam, switch back to use firmware(9) instead of
having the firmware in hex format.
Put the binary firmware uuencoded into sys/contrib/dev/npe, and slap a
LICENSE file, as found on the Intel website.

Approved by:	re (blanket), mux (mentor)
MFC After:	1 week
2007-09-27 22:39:49 +00:00
cognet
a4964f6cfa Now that Intel changed the license for the NPE firmware, import it directly
hexed into our tree, instead of requiring the user to download it.

Approved by:	re (blanket)
MFC after:	1 week
2007-09-27 21:18:34 +00:00
cognet
8ce3a406bc Fix a comment to reflect the truth.
Spotted out by:	Marius Nuennerich <marius.nuennerich AT gmx D0T de>
Approved by:	re (blanket)
2007-09-27 20:52:17 +00:00
alc
d1bce06c64 Change the management of cached pages (PQ_CACHE) in two fundamental
ways:

(1) Cached pages are no longer kept in the object's resident page
splay tree and memq.  Instead, they are kept in a separate per-object
splay tree of cached pages.  However, access to this new per-object
splay tree is synchronized by the _free_ page queues lock, not to be
confused with the heavily contended page queues lock.  Consequently, a
cached page can be reclaimed by vm_page_alloc(9) without acquiring the
object's lock or the page queues lock.

This solves a problem independently reported by tegge@ and Isilon.
Specifically, they observed the page daemon consuming a great deal of
CPU time because of pages bouncing back and forth between the cache
queue (PQ_CACHE) and the inactive queue (PQ_INACTIVE).  The source of
this problem turned out to be a deadlock avoidance strategy employed
when selecting a cached page to reclaim in vm_page_select_cache().
However, the root cause was really that reclaiming a cached page
required the acquisition of an object lock while the page queues lock
was already held.  Thus, this change addresses the problem at its
root, by eliminating the need to acquire the object's lock.

Moreover, keeping cached pages in the object's primary splay tree and
memq was, in effect, optimizing for the uncommon case.  Cached pages
are reclaimed far, far more often than they are reactivated.  Instead,
this change makes reclamation cheaper, especially in terms of
synchronization overhead, and reactivation more expensive, because
reactivated pages will have to be reentered into the object's primary
splay tree and memq.

(2) Cached pages are now stored alongside free pages in the physical
memory allocator's buddy queues, increasing the likelihood that large
allocations of contiguous physical memory (i.e., superpages) will
succeed.

Finally, as a result of this change long-standing restrictions on when
and where a cached page can be reclaimed and returned by
vm_page_alloc(9) are eliminated.  Specifically, calls to
vm_page_alloc(9) specifying VM_ALLOC_INTERRUPT can now reclaim and
return a formerly cached page.  Consequently, a call to malloc(9)
specifying M_NOWAIT is less likely to fail.

Discussed with: many over the course of the summer, including jeff@,
   Justin Husted @ Isilon, peter@, tegge@
Tested by: an earlier version by kris@
Approved by: re (kensmith)
2007-09-25 06:25:06 +00:00
cognet
6055cf1f83 Make sure we do not call _arm_bzero() or _arm_memcpy() if the size is not at
least the minimum asked by the driver.

Approved by:	re (blanket)
2007-09-22 22:47:48 +00:00
cognet
20a45c5c15 Add various macros for the ADMA unit.
Approved by:	re (blanket)
2007-09-22 22:25:24 +00:00
cognet
6b6ebc8c90 Add a driver for the 7seg found on the CRB board, largely based on the
IQ31244 version.

Approved by:	re (blanket)
2007-09-22 16:25:43 +00:00
cognet
910d500785 Twist the RAS logic a bit to avoid branching.
MFC After:	1 week
Approved by:	re (blanket)
2007-09-22 14:23:52 +00:00
cognet
1c8ede1513 Remove dead code.
Approved by:	re (blanket)
Beer from:	jadawin
2007-09-19 15:30:25 +00:00
imp
cf6bc93f9b Kill bogus printf debugs.
Approved by: re@ (blanket)
2007-09-16 07:51:02 +00:00
imp
3bac12ad89 Kill overly verbose messages about setting bus width.
Approved by: re@ (blanket)
2007-09-16 07:48:58 +00:00
alc
20b10da706 It has been observed on the mailing lists that the different categories
of pages don't sum to anywhere near the total number of pages on amd64.
This is for the most part because uma_small_alloc() pages have never been
counted as wired pages, like their kmem_malloc() brethren.  They should
be.  This changes fixes that.

It is no longer necessary for the page queues lock to be held to free
pages allocated by uma_small_alloc().  I removed the acquisition and
release of the page queues lock from uma_small_free() on amd64 and ia64
weeks ago.  This patch updates the other architectures that have
uma_small_alloc() and uma_small_free().

Approved by: re (kensmith)
2007-09-15 18:47:02 +00:00
cognet
4e0d648ec9 It's probably time I learn C.
Fix a few while (!uart_getreg() & SR1_TNF) when
while (!(uart_getreg() & SR18TNF)) was really meant.
This driver should die anyway, it's awful, and uart_ns8250 should be fine
for the StrongArm 1110. I'll kill it later.

Submitted by:	Mikhael Skvorts
Approved by:	re (blanket)
2007-09-12 18:28:09 +00:00
cognet
31dec38dbc In __bswap16_var(), make sure the 16 upper bits are cleared; while
optimizing, gcc4 doesn't always do so.

Reported by:	Nathan Whitehorn
Approved by:	re (blanket)
2007-09-09 11:58:38 +00:00
cognet
79e92ec4ea There's no need to re-read PCIR_COMMAND once we set it.
Approved by:	re (blanket)
2007-09-04 18:45:27 +00:00
cognet
fad9eb8cfe Just wbinv if both PREREAD and PREWRITE are set.
In PREREAD, just invalidate the cache lines, and do not write back them, if
the buffer is properly aligned.

Approved by:	re (blanket)
2007-08-18 16:47:28 +00:00
cognet
1b5640bcfb Ooops, we need to define TD_LOCK here.
Approved by:	re (blanket)
Pointy hat to:	cognet
2007-08-08 09:27:52 +00:00
cognet
d893d60b08 Add cast to silent gcc warnings.
Approved by:	re (blanket)
2007-08-07 18:37:21 +00:00
cognet
14a1146e27 Use the third argument of cpu_switch(), as done for i386/amd63, as it is
required for ULE.

Approved by:	re (blanket)
2007-08-07 18:20:55 +00:00
imp
7e771d27fb Add in all the USB devices and all the wireless goo. The KB9202 has
only USB 1.1 speeds available, but this shouldn't hurt.  Now that we have
working usb support for this board, this is a natural followup.

Approved by: re (kensmith)
2007-07-31 17:45:54 +00:00
imp
4d0d4dac14 Make USB work on the KB9202{,A,B} boards. This has been in p4 for about
7 months.  You must have JP6 in the 1-2 position to supply power to the
USB devices, but I've used uftdi, uplcom and umass successfully.  If you
have it in 2-3, then nothing will show up.  Also, if you have the FQPA
packaging for the AT91RM9200 (like the KN9202 boards have), you will get
the following message

uhub0: device problem (IOERROR), disabling port 2

due to a hardware erratum.  It is safe to ignore as it is about pins that
aren't brought out on the FQPA package and aren't proeprly terminated either.
Alas, there's no register to read to tell the FQPA from the BGA versions.

Submitted by: Daan Vreeken
Approved by: re (kensmith)
2007-07-31 17:43:18 +00:00
cognet
99641742c6 MFppc:
revision 1.66
date: 2007/07/31 06:23:26;  author: marcel;  state: Exp;  lines: +2 -2
Fix backward compatibility of the "old" (i.e. FreeBSD6) lseek
syscall. It was broken when a new lseek syscall was introduced.
The problem is that we need to swap the 32-bit td_retval values
for the __syscall indirect syscall when the actual syscall has
a 32-bit return value. Hence, we need to exclude lseek(2). And
this means the "old" lseek(2) as well -- which we didn't.

Based on a patch from: grehan@

Approved by:	re (blanket)
2007-07-31 17:09:05 +00:00
cognet
d6b34bbb69 CRB config file.
Approved by:	re (blanket)
2007-07-27 14:57:03 +00:00
cognet
477cdd4e83 XScale core 3 definitions.
Approved by:	re (blanket)
2007-07-27 14:54:27 +00:00
cognet
a00e73f4ad Cleanup
Approved by:	re (blanket)
2007-07-27 14:53:42 +00:00
cognet
5d0ddbc52f Do not define NIRQ, it is already defined in include/intr.h
Approved by:	re (blanket)
2007-07-27 14:53:06 +00:00
cognet
fb0b75d6c4 Share the timer and watchdog drivers with the i81342. It's the same,
except it uses different registers.

Approved by:	re (blanket)
2007-07-27 14:52:04 +00:00
cognet
31da325f5f Add initial IOP342 support.
Thanks to Intel for providing sample hardware.

Approved by:	re (blanket)
2007-07-27 14:50:57 +00:00
cognet
1ee793cfc2 Say if the L2 cache is enabled or disabled as well.
Approved by:	re (blanket)
2007-07-27 14:49:11 +00:00
cognet
72f29f4f32 Handle supersections and L2 cache.
Approved by:	re (blanket)
2007-07-27 14:46:43 +00:00
cognet
70e7077c96 Use supersection instead of standard sections to map the whole memory
when available.

Approved by:	re (blanket)
2007-07-27 14:46:15 +00:00
cognet
123f2b86f7 Fix the cache mode description.
Approved by:	re (blanket)
2007-07-27 14:45:33 +00:00
cognet
8b22cea67f Properly handle supersections.
Make sure we cache entries in the L2 cache.

Approved by:	re (blanket)
2007-07-27 14:45:04 +00:00
cognet
d9f013dcfb Bring in two bandaids to get the elf trampoline to work again, until I find
a proper solution.
- Add a dummy entry point which just calls the C entry points, and try to make
sure it's the first code in the binary.
- Copy a bit more than func_end to try to copy the whole load_kernel()
function. gcc4 puts code behind the func_end symbol.

Approved by:	re (blanket)
2007-07-27 14:42:25 +00:00
cognet
30161fe629 Add a new set of functions to handle L2 cache. Make them no-op for every
CPU except Xscale core 3.

Approved by:	re (blanket)
2007-07-27 14:39:41 +00:00
cognet
22beec041a Import xscale core 3 cache management functions.
Approved by:	re (blanket)
2007-07-27 14:28:15 +00:00
cognet
b1d9735f04 INTR_FILTER bits for arm
Approved by:	re (blanket)
2007-07-27 14:26:42 +00:00
cognet
25994fd742 The iop34x has 128 interrupts. 2007-06-16 15:03:33 +00:00
cognet
2349f48ce0 Introduce pmap_kenter_supersection(), which maps 16MB super-sections into
the kernel pmap.
Document a bit more the behavior of the xscale core 3.
2007-06-11 21:29:26 +00:00
imp
eed16ca559 Fix a spacing nit. 2007-06-11 19:36:37 +00:00
cognet
4042d45aba Initialize the dma tag's bounce_zone to NULL if we didn't allocate it. 2007-06-10 12:33:01 +00:00
marcel
75588c5a15 Add kdb_cpu_sync_icache(), intended to synchronize instruction
caches with data caches after writing to memory. This typically
is required to make breakpoints work on ia64 and powerpc. For
those architectures the function is implemented.
2007-06-09 21:55:17 +00:00
cognet
1f72bba084 There's no nobounce_dmamap on arm. 2007-06-07 21:51:09 +00:00
jeff
fe66d0ac91 - PCPU_ADD is no longer spelled with LAZY_ in the middle.
Submitted by:	attilio
2007-06-06 23:23:47 +00:00
jeff
be3241715a - Change comments and asserts to reflect the removal of the global
scheduler lock.

Tested by:      kris, current@
Tested on:      i386, amd64, ULE, 4BSD, libthr, libkse, PREEMPTION, etc.
Discussed with: kris, attilio, kmacy, jhb, julian, bde (small parts each)
2007-06-04 23:57:32 +00:00
attilio
e333d0ff0e Rework the PCPU_* (MD) interface:
- Rename PCPU_LAZY_INC into PCPU_INC
- Add the PCPU_ADD interface which just does an add on the pcpu member
  given a specific value.

Note that for most architectures PCPU_INC and PCPU_ADD are not safe.
This is a point that needs some discussions/work in the next days.

Reviewed by: alc, bde
Approved by: jeff (mentor)
2007-06-04 21:38:48 +00:00
marcel
c118c8a64b Revert to the previous version where the return value of uart_getenv()
is being ignored. It's optional and the lack of environment variable
is not an error condition.
2007-06-04 17:53:42 +00:00
alc
ccfe66d477 Add the machine-specific definitions for configuring the new physical
memory allocator.

Approved by:	re
2007-06-04 08:02:22 +00:00
attilio
7dd8ed88a9 Revert VMCNT_* operations introduction.
Probabilly, a general approach is not the better solution here, so we should
solve the sched_lock protection problems separately.

Requested by: alc
Approved by: jeff (mentor)
2007-05-31 22:52:15 +00:00
piso
42dfc78150 In some particular cases (like in pccard and pccbb), the real device
handler is wrapped in a couple of functions - a filter wrapper and an
ithread wrapper. In this case (and just in this case), the filter
wrapper could ask the system to schedule the ithread and mask the
interrupt source if the wrapped handler is composed of just an ithread
handler: modify the "old" interrupt code to make it support
this situation, while the "new" interrupt code is already ok.

Discussed with: jhb
2007-05-31 19:25:35 +00:00
jhay
410f244e4f Remove the hardcoded IXP425_UART?_VBASE values in the
uart_ixp425_probe() and uart_cpu_getdev(). Change
uart_cpu_getdev() to use hints to find the console.

Reviewed by:	marcel
2007-05-29 18:10:42 +00:00
yongari
f53195d29a Honor maxsegsz of less than a page size in a DMA tag. Previously it
used to return PAGE_SIZE without respect to restrictions of a DMA tag.
This affected all of the busdma load functions that use
_bus_dmamap_loader_buffer() as their back-end.

Reviewed by:	scottl
2007-05-29 06:30:26 +00:00
alc
1dfb7ec904 Eliminate some unused definitions that came from NetBSD. 2007-05-28 21:04:22 +00:00
jhay
069f479480 We do not need to get the irq out of ivars in ixp425_setup_intr(). By
this time they have already been set. In fact trying to set it here too
breaks irqs for pci devices.
2007-05-28 18:54:08 +00:00
jhay
87f87ebe96 Optimize a bit more, both the Avila and Pronghorn Metro boards work with
GPIO_TYPE_EDG_RISING.

Reviewed by:	sam
2007-05-28 18:45:16 +00:00
sam
fb9dbcd056 Search for a proper ucode image to use by incrementing the minor
release number up to the max.  This should eliminate the need to
tweak the default imageid define for later releases that are found
on the Intel web site.

MFC after:	1 month
2007-05-24 16:31:22 +00:00
sam
daab632c06 o add hints for avila boards; brings back i2c devices lost when iicbus
started using hints instead of wired down device enumeration
o add usb commented out; will enable when support works

MFC after:	1 month
2007-05-24 16:27:48 +00:00