into the kernel, which is used mostly on early development stages.
On RPI(2) the DTB is loaded and modified by firmware and then handed to
kernel via U-Boot and ubldr.
The RPI firmware adds (or modify) a few valuable data to the in memory
DTB, like:
- System memory;
- Ethernet MAC address;
- framebuffer settings;
- Board serial and revision;
- clock-frequency for most of devices.
Each TX queue can hold one packet (yes, if_emac can send only two(!)
packets at a time).
Even with this change the very limited FIFO buffer (3 KiB for TX and 13 KiB
for RX) fill up too quick to sustain higher throughput.
For the TCP case it turns out that TX isn't the limiting factor, but the RX
side is (the FIFO fill up and starts to discard packets, so the sender has
to slow down).
Do not strip the ethernet CRC until we read all data from FIFO, otherwise
the CRC bytes would be left in FIFO causing the failure of next packet
(wrong packet header).
When this error happens the receiver has to be disabled and the RX FIFO
flushed, discarding valid packets.
With this fix if_emac behaves a lot better.
There are a few differences between the two. On arm we need to provide a
list of addresses we may be mapping before we have initialised the virtual
memory subsystem, however on arm64 we allocate a small (2MiB for a 4k
granule) range to be used for such purposes.
Differential Revision: https://reviews.freebsd.org/D2249
Sponsored by: The FreeBSD Foundation
handles versions 0.1 and 0.2 of the standard on 32-bit ARM.
With this driver we can shutdown in QEMU. Further work is needed to
turn secondary cores on on boot and to support later revisions of the
specification.
Submitted by: Robin Randhawa <Robin.Randhawa at ARM.com>
Sponsored by: The FreeBSD Foundation
This is needed with the pl011 driver. Before this change it would default
to a shift of 0, however the hardware places the registers at 4-byte
addresses meaning the value should be 2.
This patch fixes this for the pl011 when configured using the fdt. The
other drivers have a default value of 0 to keep this a no-op.
MFC after: 1 week
supply clk81 information. It also changes the hardware strings
in some of the drivers to match what's present in the GNU files.
Submitted by: John Wehle
Reviewed by: imp
Previously we used pmap_kremove(), but with ARM_NEW_PMAP it does the remove
in a way that isn't SMP-coherent (which is appropriate in some circumstances
such as mapping/unmapping sf buffers). With matching enter/remove routines
for device mappings, each low-level implementation can do the right thing.
Reviewed by: Svatopluk Kraus <onwahe@gmail.com>
- Add macros to handle the differences in accessing these registers on arm
and arm64.
- Use the fdt data to detect if we are on an ARMv7 or ARMv8.
- Use the virtual timer by default on arm64, we may not have access to
the physical timer.
Differential Revision: https://reviews.freebsd.org/D2208
Reviewed by: emaste
Sponsored by: The FreeBSD Foundation
not have interupt property in pl310 node. Interrupt is used only to
detect cache activity when L2 cache is disabled, it's not vital for
normal operations.
- Fix intrhook allocation/initialization
specially aml8726-m6 and aml8726-m8b SoC based devices.
aml8726-m6 SoC exist in devices such as Visson ATV-102.
Hardkernel ODROID-C1 board has aml8726-m8b SoC.
The following support is included:
Basic machdep code
SMP
Interrupt controller
Clock control driver (aka gate)
Pinctrl
Timer
Real time clock
UART
GPIO
I2C
SD controller
SDXC controller
USB
Watchdog
Random number generator
PLL / Clock frequency measurement
Frame buffer
Submitted by: John Wehle
Approved by: stas (mentor)
the PMC_IN_KERNEL() macro definition.
Add missing macros to extract the return address (LR) from the trapframe.
Discussed with: andrew
Obtained from: Cambridge/L41
Sponsored by: DARPA, AFRL
MFC after: 2 weeks
This is pretty much a complete rewrite based on the existing i386 code. The
patches have been circulating for a couple years and have been looked at by
plenty of people, but I'm not putting anybody on the hook as having reviewed
this in any formal sense except myself.
After this has gotten wider testing from the user community, ARM_NEW_PMAP
will become the default and various dregs of the old pmap code will be
removed.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>,
Michal Meloun <meloun@miracle.cz>
the startup trampoline code. The old code allocated a kva page, mapped it
using using pmap_kenter_nocache(), then freed the kva without destroying
the mapping. This is the only use of pmap_kenter_nocache() in the system,
so redoing this one use of allows it to be garbage collected in the
near future.
the Raspberry Pi B we support most of the devices are already supported,
however the base address has changed.
A few items are not working, or missing. The main ones are:
* DMA doesn't work in the sdhci driver.
* Enabling vchiq halts the boot, may be interrupt related.
* There is no U-Boot port yet so the DTB is embedded in the kernel.
The last point will make it difficult to boot FreeBSD, however there is
support for the Raspberry Pi 2 in the U-Boot git repo. As I have not tested
this it is left as an open task to create a port to build.
X-MFC: When the above issues are fixed
Sponsored by: ABT Systems Ltd
we're not looking at it.
Fix this by increasing l2->l2_occupancy before we try to alloc (and decrease
it if the allocation failed, or if another thread did a similar allocation).
Submitted by: Kohji Okuno <okuno.kohji@jp.panasonic.com>
MFC after: 1 week
to get the default frequency of the sdhci device.
While here use a u_int to hold the frequency as it may be too large to fit
in a 32-bit signed integer. This is the case when we have a 250MHz clock.
Each plaform performs virtual memory split between kernel and user space
and assigns kernel certain amount of memory space. However, is is sometimes
reasonable to change the default values. Such situation may happen on
systems where the demand for kernel buffers is high, many devices occupying
memory etc. This of course comes with the cost of decreasing user space
memory range so shall be used with care. Most embedded systems will not
suffer from this limtation but rather take advantage of this potential
since default behavior is left unchanged.
Submitted by: Wojciech Macek <wma@semihalf.com>
Reviewed by: imp
Obtained from: Semihalf
These are left over from long ago when there was no way to load modules
on early armv6 platforms, and when there was a build problem with ahc
that has long since been fixed, and they just keep getting copy-pasted
into new configs.
ntpd is hard-coded to use /dev/ppsN, and typically when multiple PPS sources
are available the sysadmin will symlink the right one(s) to /dev/ppsN, so
it's best to not usurp those names directly.
Also ensure dsb precedes isb in all icache maintenance routines (first
do a data sync, then stall the instruction stream until it finishes).
Submitted by: Michal Meloun
been done by U-Boot. This allows the USB to work when we load the kernel
directly.
No dma sync is performed after these operations as the data we read/write
is not used by the cpu after the calls to the maimbox driver.
Differential Revision: https://reviews.freebsd.org/D1940
Reviewed by: imp, Michal Meloun (meloun AT miracle.cz)
MFC after: 1 Week
Sponsored by: ABT Systems Ltd
both the post-filter and post-thread callbacks.
Also eliminate a completely unecessary write to INTC_ISR_CLEAR register,
which clears a software-generated interrupt that can only happen with a
write to INTC_ISR_SET (which nothing does).
uart implementations, and export them using the new linker-set mechanism.
Differential Revision: https://reviews.freebsd.org/D1993
Submitted by: Michal Meloun
PL (programmable logic) uses FCLK0..FCLK3 as a clock sources.
Normally they're configured by first stage boot loader (FSBL)
and normal user never has to touch them. These sysctls may come
useful for hardware developers
hw.fpga.fclk.N.source: clock source (IO, DDR, ARM)
hw.fpga.fclk.N.freq: requested frequency in Hz
hw.fpga.fclk.N.actual_freq: actual frequency in Hz (R/O)
hw.fgpa.level_shifters: 0/1 to enable/disable PS-PL level shifters,
normally they're enabled either by FSBL or after programming
FPGA through devcfg(4)
emulate the instructions used in function entry and exit.
For function entry ARM will use a push instruction to push up to 16
registers to the stack. While we don't expect all 16 to be used we need to
handle any combination the compiler may generate, even if it doesn't make
sense (e.g. pushing the program counter).
On function return we will either have a pop or branch instruction. The
former is similar to the push instruction, but with care to make sure we
update the stack pointer and program counter correctly in the cases they
are either in the list of registers or not. For branch we need to take the
24-bit offset, sign-extend it, and add that number of 4-byte words to the
program counter. Care needs to be taken as, due to historical reasons, the
address the branch is relative to is not the current instruction, but 8
bytes later.
This allows us to use the following probes on ARM boards:
dtrace -n 'fbt::malloc:entry { stack() }'
and
dtrace -n 'fbt:🆓return { stack() }'
Differential Revision: https://reviews.freebsd.org/D2007
Reviewed by: gnn, rpaulo
Sponsored by: ABT Systems Ltd
the translation table (this may be left over from armv5 days). It's
especially bad to do so using a cache operation that isn't coherent on
SMP systems.
Submitted by: Michal Meloun
