2017-12-19 15:49:01 +00:00
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2010-2016 Intel Corporation
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2012-12-19 23:00:00 +00:00
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*/
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#include <sys/queue.h>
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#include <stdio.h>
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#include <errno.h>
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#include <stdint.h>
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#include <stdarg.h>
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#include <rte_common.h>
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#include <rte_interrupts.h>
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#include <rte_byteorder.h>
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#include <rte_debug.h>
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#include <rte_pci.h>
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2017-10-26 10:06:08 +00:00
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#include <rte_bus_pci.h>
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2012-12-19 23:00:00 +00:00
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#include <rte_ether.h>
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2021-01-29 16:48:19 +00:00
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#include <ethdev_driver.h>
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#include <ethdev_pci.h>
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2012-12-19 23:00:00 +00:00
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#include <rte_memory.h>
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#include <rte_eal.h>
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#include <rte_malloc.h>
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2014-04-21 14:59:34 +00:00
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#include <rte_dev.h>
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2012-12-19 23:00:00 +00:00
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#include "e1000_logs.h"
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2015-05-15 15:56:49 +00:00
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#include "base/e1000_api.h"
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2012-12-19 23:00:00 +00:00
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#include "e1000_ethdev.h"
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#define EM_EIAC 0x000DC
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#define PMD_ROUNDUP(x,y) (((x) + (y) - 1)/(y) * (y))
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static int eth_em_configure(struct rte_eth_dev *dev);
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static int eth_em_start(struct rte_eth_dev *dev);
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2020-10-15 13:30:45 +00:00
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static int eth_em_stop(struct rte_eth_dev *dev);
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2020-09-28 23:14:10 +00:00
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static int eth_em_close(struct rte_eth_dev *dev);
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2019-09-14 11:37:24 +00:00
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static int eth_em_promiscuous_enable(struct rte_eth_dev *dev);
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static int eth_em_promiscuous_disable(struct rte_eth_dev *dev);
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2019-09-24 12:56:10 +00:00
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static int eth_em_allmulticast_enable(struct rte_eth_dev *dev);
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static int eth_em_allmulticast_disable(struct rte_eth_dev *dev);
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2012-12-19 23:00:00 +00:00
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static int eth_em_link_update(struct rte_eth_dev *dev,
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int wait_to_complete);
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2017-10-10 20:20:18 +00:00
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static int eth_em_stats_get(struct rte_eth_dev *dev,
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2012-12-19 23:00:00 +00:00
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struct rte_eth_stats *rte_stats);
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2019-09-06 14:34:54 +00:00
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static int eth_em_stats_reset(struct rte_eth_dev *dev);
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2019-09-12 16:42:28 +00:00
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static int eth_em_infos_get(struct rte_eth_dev *dev,
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2012-12-19 23:00:00 +00:00
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struct rte_eth_dev_info *dev_info);
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2014-06-17 18:09:26 +00:00
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static int eth_em_flow_ctrl_get(struct rte_eth_dev *dev,
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struct rte_eth_fc_conf *fc_conf);
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2012-12-19 23:00:00 +00:00
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static int eth_em_flow_ctrl_set(struct rte_eth_dev *dev,
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struct rte_eth_fc_conf *fc_conf);
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static int eth_em_interrupt_setup(struct rte_eth_dev *dev);
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2015-10-29 09:18:38 +00:00
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static int eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev);
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2012-12-19 23:00:00 +00:00
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static int eth_em_interrupt_get_status(struct rte_eth_dev *dev);
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2016-12-23 15:57:56 +00:00
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static int eth_em_interrupt_action(struct rte_eth_dev *dev,
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struct rte_intr_handle *handle);
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2017-04-06 12:42:22 +00:00
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static void eth_em_interrupt_handler(void *param);
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2012-12-19 23:00:00 +00:00
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static int em_hw_init(struct e1000_hw *hw);
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static int em_hardware_init(struct e1000_hw *hw);
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static void em_hw_control_acquire(struct e1000_hw *hw);
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static void em_hw_control_release(struct e1000_hw *hw);
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static void em_init_manageability(struct e1000_hw *hw);
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static void em_release_manageability(struct e1000_hw *hw);
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2014-06-17 18:09:30 +00:00
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static int eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
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2012-12-19 23:00:00 +00:00
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static int eth_em_vlan_filter_set(struct rte_eth_dev *dev,
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uint16_t vlan_id, int on);
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2017-09-01 02:36:28 +00:00
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static int eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask);
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2012-12-19 23:00:00 +00:00
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static void em_vlan_hw_filter_enable(struct rte_eth_dev *dev);
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static void em_vlan_hw_filter_disable(struct rte_eth_dev *dev);
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static void em_vlan_hw_strip_enable(struct rte_eth_dev *dev);
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static void em_vlan_hw_strip_disable(struct rte_eth_dev *dev);
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/*
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static void eth_em_vlan_filter_set(struct rte_eth_dev *dev,
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uint16_t vlan_id, int on);
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*/
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2015-10-29 09:18:38 +00:00
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static int eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
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static int eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
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2015-10-29 09:18:39 +00:00
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static void em_lsc_intr_disable(struct e1000_hw *hw);
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2015-10-29 09:18:38 +00:00
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static void em_rxq_intr_enable(struct e1000_hw *hw);
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2015-10-29 09:18:39 +00:00
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static void em_rxq_intr_disable(struct e1000_hw *hw);
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2015-10-29 09:18:38 +00:00
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2012-12-19 23:00:00 +00:00
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static int eth_em_led_on(struct rte_eth_dev *dev);
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static int eth_em_led_off(struct rte_eth_dev *dev);
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static int em_get_rx_buffer_size(struct e1000_hw *hw);
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2019-05-21 16:13:03 +00:00
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static int eth_em_rar_set(struct rte_eth_dev *dev,
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struct rte_ether_addr *mac_addr,
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uint32_t index, uint32_t pool);
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2012-12-19 23:00:00 +00:00
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static void eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index);
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2018-04-11 16:32:51 +00:00
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static int eth_em_default_mac_addr_set(struct rte_eth_dev *dev,
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2019-05-21 16:13:03 +00:00
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struct rte_ether_addr *addr);
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2012-12-19 23:00:00 +00:00
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2015-05-28 15:05:21 +00:00
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static int eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
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2019-05-21 16:13:03 +00:00
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struct rte_ether_addr *mc_addr_set,
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2015-05-28 15:05:21 +00:00
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uint32_t nb_mc_addr);
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2012-12-19 23:00:00 +00:00
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#define EM_FC_PAUSE_TIME 0x0680
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#define EM_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
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#define EM_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
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static enum e1000_fc_mode em_fc_setting = e1000_fc_full;
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/*
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* The set of PCI devices this driver supports
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*/
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2015-04-16 23:23:39 +00:00
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static const struct rte_pci_id pci_id_em_map[] = {
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2016-07-11 14:40:37 +00:00
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82540EM) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_COPPER) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82545EM_FIBER) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_COPPER) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_FIBER) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82546EB_QUAD_COPPER) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_COPPER) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_FIBER) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_DUAL) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_SERDES_QUAD) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571PT_QUAD_COPPER) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_FIBER) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82571EB_QUAD_COPPER_LP) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_COPPER) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_FIBER) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI_SERDES) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82572EI) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82573L) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574L) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82574LA) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_82583V) },
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2017-10-13 16:32:18 +00:00
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH2_LV_LM) },
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2016-07-11 14:40:37 +00:00
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_LM) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPT_I217_V) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_LM) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LPTLP_I218_V) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM2) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V2) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_LM3) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_I218_V3) },
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2016-11-23 17:23:00 +00:00
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM2) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V2) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_LBG_I219_LM3) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM4) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V4) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_LM5) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_SPT_I219_V5) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM6) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V6) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_LM7) },
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{ RTE_PCI_DEVICE(E1000_INTEL_VENDOR_ID, E1000_DEV_ID_PCH_CNP_I219_V7) },
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2016-07-11 14:40:37 +00:00
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{ .vendor_id = 0, /* sentinel */ },
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2012-12-19 23:00:00 +00:00
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};
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2015-04-07 21:21:03 +00:00
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static const struct eth_dev_ops eth_em_ops = {
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2012-12-19 23:00:00 +00:00
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.dev_configure = eth_em_configure,
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.dev_start = eth_em_start,
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.dev_stop = eth_em_stop,
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.dev_close = eth_em_close,
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.promiscuous_enable = eth_em_promiscuous_enable,
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.promiscuous_disable = eth_em_promiscuous_disable,
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.allmulticast_enable = eth_em_allmulticast_enable,
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.allmulticast_disable = eth_em_allmulticast_disable,
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.link_update = eth_em_link_update,
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.stats_get = eth_em_stats_get,
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.stats_reset = eth_em_stats_reset,
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.dev_infos_get = eth_em_infos_get,
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2014-06-17 18:09:30 +00:00
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.mtu_set = eth_em_mtu_set,
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2012-12-19 23:00:00 +00:00
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.vlan_filter_set = eth_em_vlan_filter_set,
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.vlan_offload_set = eth_em_vlan_offload_set,
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.rx_queue_setup = eth_em_rx_queue_setup,
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.rx_queue_release = eth_em_rx_queue_release,
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.tx_queue_setup = eth_em_tx_queue_setup,
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.tx_queue_release = eth_em_tx_queue_release,
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2015-10-29 09:18:38 +00:00
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.rx_queue_intr_enable = eth_em_rx_queue_intr_enable,
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.rx_queue_intr_disable = eth_em_rx_queue_intr_disable,
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2012-12-19 23:00:00 +00:00
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.dev_led_on = eth_em_led_on,
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.dev_led_off = eth_em_led_off,
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2014-06-17 18:09:26 +00:00
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.flow_ctrl_get = eth_em_flow_ctrl_get,
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2012-12-19 23:00:00 +00:00
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.flow_ctrl_set = eth_em_flow_ctrl_set,
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2018-02-19 00:39:55 +00:00
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.mac_addr_set = eth_em_default_mac_addr_set,
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2012-12-19 23:00:00 +00:00
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.mac_addr_add = eth_em_rar_set,
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.mac_addr_remove = eth_em_rar_clear,
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2015-05-28 15:05:21 +00:00
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.set_mc_addr_list = eth_em_set_mc_addr_list,
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2015-10-27 12:51:46 +00:00
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.rxq_info_get = em_rxq_info_get,
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.txq_info_get = em_txq_info_get,
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2012-12-19 23:00:00 +00:00
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};
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2016-03-02 13:59:34 +00:00
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/**
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* eth_em_dev_is_ich8 - Check for ICH8 device
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* @hw: pointer to the HW structure
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*
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* return TRUE for ICH8, otherwise FALSE
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**/
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static bool
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eth_em_dev_is_ich8(struct e1000_hw *hw)
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{
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DEBUGFUNC("eth_em_dev_is_ich8");
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switch (hw->device_id) {
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2017-10-13 16:32:18 +00:00
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case E1000_DEV_ID_PCH2_LV_LM:
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2016-03-02 13:59:34 +00:00
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case E1000_DEV_ID_PCH_LPT_I217_LM:
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case E1000_DEV_ID_PCH_LPT_I217_V:
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case E1000_DEV_ID_PCH_LPTLP_I218_LM:
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case E1000_DEV_ID_PCH_LPTLP_I218_V:
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case E1000_DEV_ID_PCH_I218_V2:
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case E1000_DEV_ID_PCH_I218_LM2:
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case E1000_DEV_ID_PCH_I218_V3:
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case E1000_DEV_ID_PCH_I218_LM3:
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2016-11-23 17:23:00 +00:00
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case E1000_DEV_ID_PCH_SPT_I219_LM:
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case E1000_DEV_ID_PCH_SPT_I219_V:
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case E1000_DEV_ID_PCH_SPT_I219_LM2:
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case E1000_DEV_ID_PCH_SPT_I219_V2:
|
|
|
|
case E1000_DEV_ID_PCH_LBG_I219_LM3:
|
|
|
|
case E1000_DEV_ID_PCH_SPT_I219_LM4:
|
|
|
|
case E1000_DEV_ID_PCH_SPT_I219_V4:
|
|
|
|
case E1000_DEV_ID_PCH_SPT_I219_LM5:
|
|
|
|
case E1000_DEV_ID_PCH_SPT_I219_V5:
|
|
|
|
case E1000_DEV_ID_PCH_CNP_I219_LM6:
|
|
|
|
case E1000_DEV_ID_PCH_CNP_I219_V6:
|
|
|
|
case E1000_DEV_ID_PCH_CNP_I219_LM7:
|
|
|
|
case E1000_DEV_ID_PCH_CNP_I219_V7:
|
2016-03-02 13:59:34 +00:00
|
|
|
return 1;
|
|
|
|
default:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-12-19 23:00:00 +00:00
|
|
|
static int
|
2015-03-05 18:24:59 +00:00
|
|
|
eth_em_dev_init(struct rte_eth_dev *eth_dev)
|
2012-12-19 23:00:00 +00:00
|
|
|
{
|
2017-05-15 10:24:03 +00:00
|
|
|
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
|
2016-12-23 15:57:56 +00:00
|
|
|
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
|
2015-07-03 14:38:26 +00:00
|
|
|
struct e1000_adapter *adapter =
|
|
|
|
E1000_DEV_PRIVATE(eth_dev->data->dev_private);
|
2012-12-19 23:00:00 +00:00
|
|
|
struct e1000_hw *hw =
|
|
|
|
E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
|
|
|
|
struct e1000_vfta * shadow_vfta =
|
|
|
|
E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
|
|
|
|
|
|
|
|
eth_dev->dev_ops = ð_em_ops;
|
2020-09-09 13:01:43 +00:00
|
|
|
eth_dev->rx_queue_count = eth_em_rx_queue_count;
|
|
|
|
eth_dev->rx_descriptor_done = eth_em_rx_descriptor_done;
|
|
|
|
eth_dev->rx_descriptor_status = eth_em_rx_descriptor_status;
|
|
|
|
eth_dev->tx_descriptor_status = eth_em_tx_descriptor_status;
|
2012-12-19 23:00:00 +00:00
|
|
|
eth_dev->rx_pkt_burst = (eth_rx_burst_t)ð_em_recv_pkts;
|
|
|
|
eth_dev->tx_pkt_burst = (eth_tx_burst_t)ð_em_xmit_pkts;
|
2016-12-23 18:40:48 +00:00
|
|
|
eth_dev->tx_pkt_prepare = (eth_tx_prep_t)ð_em_prep_pkts;
|
2012-12-19 23:00:00 +00:00
|
|
|
|
|
|
|
/* for secondary processes, we don't initialise any further as primary
|
|
|
|
* has already done this work. Only check we don't need a different
|
|
|
|
* RX function */
|
|
|
|
if (rte_eal_process_type() != RTE_PROC_PRIMARY){
|
|
|
|
if (eth_dev->data->scattered_rx)
|
|
|
|
eth_dev->rx_pkt_burst =
|
|
|
|
(eth_rx_burst_t)ð_em_recv_scattered_pkts;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-11-23 15:13:53 +00:00
|
|
|
rte_eth_copy_pci_info(eth_dev, pci_dev);
|
2020-10-14 02:26:47 +00:00
|
|
|
eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
|
2015-11-23 15:13:53 +00:00
|
|
|
|
2013-05-30 17:12:39 +00:00
|
|
|
hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
|
2012-12-19 23:00:00 +00:00
|
|
|
hw->device_id = pci_dev->id.device_id;
|
2015-07-03 14:38:26 +00:00
|
|
|
adapter->stopped = 0;
|
2012-12-19 23:00:00 +00:00
|
|
|
|
|
|
|
/* For ICH8 support we'll need to map the flash memory BAR */
|
2016-03-02 13:59:34 +00:00
|
|
|
if (eth_em_dev_is_ich8(hw))
|
|
|
|
hw->flash_address = (void *)pci_dev->mem_resource[1].addr;
|
2012-12-19 23:00:00 +00:00
|
|
|
|
|
|
|
if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS ||
|
|
|
|
em_hw_init(hw) != 0) {
|
|
|
|
PMD_INIT_LOG(ERR, "port_id %d vendorID=0x%x deviceID=0x%x: "
|
|
|
|
"failed to init HW",
|
|
|
|
eth_dev->data->port_id, pci_dev->id.vendor_id,
|
|
|
|
pci_dev->id.device_id);
|
2016-01-27 13:58:30 +00:00
|
|
|
return -ENODEV;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Allocate memory for storing MAC addresses */
|
2019-05-21 16:13:05 +00:00
|
|
|
eth_dev->data->mac_addrs = rte_zmalloc("e1000", RTE_ETHER_ADDR_LEN *
|
2012-12-19 23:00:00 +00:00
|
|
|
hw->mac.rar_entry_count, 0);
|
|
|
|
if (eth_dev->data->mac_addrs == NULL) {
|
|
|
|
PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
|
|
|
|
"store MAC addresses",
|
2019-05-21 16:13:05 +00:00
|
|
|
RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
|
2016-01-27 13:58:30 +00:00
|
|
|
return -ENOMEM;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Copy the permanent MAC address */
|
2019-05-21 16:13:04 +00:00
|
|
|
rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
|
2012-12-19 23:00:00 +00:00
|
|
|
eth_dev->data->mac_addrs);
|
|
|
|
|
|
|
|
/* initialize the vfta */
|
|
|
|
memset(shadow_vfta, 0, sizeof(*shadow_vfta));
|
|
|
|
|
2015-07-09 23:01:07 +00:00
|
|
|
PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
|
2014-09-17 13:46:48 +00:00
|
|
|
eth_dev->data->port_id, pci_dev->id.vendor_id,
|
|
|
|
pci_dev->id.device_id);
|
2012-12-19 23:00:00 +00:00
|
|
|
|
2016-12-23 15:57:56 +00:00
|
|
|
rte_intr_callback_register(intr_handle,
|
|
|
|
eth_em_interrupt_handler, eth_dev);
|
2012-12-19 23:00:00 +00:00
|
|
|
|
2016-01-27 13:58:30 +00:00
|
|
|
return 0;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
2015-07-03 14:38:26 +00:00
|
|
|
static int
|
|
|
|
eth_em_dev_uninit(struct rte_eth_dev *eth_dev)
|
|
|
|
{
|
|
|
|
PMD_INIT_FUNC_TRACE();
|
|
|
|
|
|
|
|
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
|
2020-04-29 06:37:24 +00:00
|
|
|
return 0;
|
2015-07-03 14:38:26 +00:00
|
|
|
|
2019-09-27 09:09:44 +00:00
|
|
|
eth_em_close(eth_dev);
|
2015-07-03 14:38:26 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-04-11 15:44:24 +00:00
|
|
|
static int eth_em_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
|
|
|
|
struct rte_pci_device *pci_dev)
|
|
|
|
{
|
|
|
|
return rte_eth_dev_pci_generic_probe(pci_dev,
|
|
|
|
sizeof(struct e1000_adapter), eth_em_dev_init);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int eth_em_pci_remove(struct rte_pci_device *pci_dev)
|
|
|
|
{
|
|
|
|
return rte_eth_dev_pci_generic_remove(pci_dev, eth_em_dev_uninit);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct rte_pci_driver rte_em_pmd = {
|
|
|
|
.id_table = pci_id_em_map,
|
2019-07-22 12:56:51 +00:00
|
|
|
.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
|
2017-04-11 15:44:24 +00:00
|
|
|
.probe = eth_em_pci_probe,
|
|
|
|
.remove = eth_em_pci_remove,
|
2012-12-19 23:00:00 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
static int
|
|
|
|
em_hw_init(struct e1000_hw *hw)
|
|
|
|
{
|
|
|
|
int diag;
|
|
|
|
|
|
|
|
diag = hw->mac.ops.init_params(hw);
|
|
|
|
if (diag != 0) {
|
2014-09-17 13:46:49 +00:00
|
|
|
PMD_INIT_LOG(ERR, "MAC Initialization Error");
|
2012-12-19 23:00:00 +00:00
|
|
|
return diag;
|
|
|
|
}
|
|
|
|
diag = hw->nvm.ops.init_params(hw);
|
|
|
|
if (diag != 0) {
|
2014-09-17 13:46:49 +00:00
|
|
|
PMD_INIT_LOG(ERR, "NVM Initialization Error");
|
2012-12-19 23:00:00 +00:00
|
|
|
return diag;
|
|
|
|
}
|
|
|
|
diag = hw->phy.ops.init_params(hw);
|
|
|
|
if (diag != 0) {
|
2014-09-17 13:46:49 +00:00
|
|
|
PMD_INIT_LOG(ERR, "PHY Initialization Error");
|
2012-12-19 23:00:00 +00:00
|
|
|
return diag;
|
|
|
|
}
|
|
|
|
(void) e1000_get_bus_info(hw);
|
|
|
|
|
|
|
|
hw->mac.autoneg = 1;
|
|
|
|
hw->phy.autoneg_wait_to_complete = 0;
|
|
|
|
hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
|
|
|
|
|
|
|
|
e1000_init_script_state_82541(hw, TRUE);
|
|
|
|
e1000_set_tbi_compatibility_82543(hw, TRUE);
|
|
|
|
|
|
|
|
/* Copper options */
|
|
|
|
if (hw->phy.media_type == e1000_media_type_copper) {
|
|
|
|
hw->phy.mdix = 0; /* AUTO_ALL_MODES */
|
|
|
|
hw->phy.disable_polarity_correction = 0;
|
|
|
|
hw->phy.ms_type = e1000_ms_hw_default;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Start from a known state, this is important in reading the nvm
|
|
|
|
* and mac from that.
|
|
|
|
*/
|
|
|
|
e1000_reset_hw(hw);
|
|
|
|
|
|
|
|
/* Make sure we have a good EEPROM before we read from it */
|
|
|
|
if (e1000_validate_nvm_checksum(hw) < 0) {
|
|
|
|
/*
|
|
|
|
* Some PCI-E parts fail the first check due to
|
|
|
|
* the link being in sleep state, call it again,
|
|
|
|
* if it fails a second time its a real issue.
|
|
|
|
*/
|
|
|
|
diag = e1000_validate_nvm_checksum(hw);
|
|
|
|
if (diag < 0) {
|
|
|
|
PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Read the permanent MAC address out of the EEPROM */
|
|
|
|
diag = e1000_read_mac_addr(hw);
|
|
|
|
if (diag != 0) {
|
|
|
|
PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Now initialize the hardware */
|
|
|
|
diag = em_hardware_init(hw);
|
|
|
|
if (diag != 0) {
|
|
|
|
PMD_INIT_LOG(ERR, "Hardware initialization failed");
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
hw->mac.get_link_status = 1;
|
|
|
|
|
|
|
|
/* Indicate SOL/IDER usage */
|
|
|
|
diag = e1000_check_reset_block(hw);
|
|
|
|
if (diag < 0) {
|
|
|
|
PMD_INIT_LOG(ERR, "PHY reset is blocked due to "
|
|
|
|
"SOL/IDER session");
|
|
|
|
}
|
2016-01-27 13:58:30 +00:00
|
|
|
return 0;
|
2012-12-19 23:00:00 +00:00
|
|
|
|
|
|
|
error:
|
|
|
|
em_hw_control_release(hw);
|
2016-01-27 13:58:30 +00:00
|
|
|
return diag;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
eth_em_configure(struct rte_eth_dev *dev)
|
|
|
|
{
|
|
|
|
struct e1000_interrupt *intr =
|
|
|
|
E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
|
|
|
|
|
2014-09-17 13:46:49 +00:00
|
|
|
PMD_INIT_FUNC_TRACE();
|
2012-12-19 23:00:00 +00:00
|
|
|
intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
|
2018-04-03 02:54:55 +00:00
|
|
|
|
2014-09-17 13:46:49 +00:00
|
|
|
PMD_INIT_FUNC_TRACE();
|
2012-12-19 23:00:00 +00:00
|
|
|
|
2016-01-27 13:58:30 +00:00
|
|
|
return 0;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
em_set_pba(struct e1000_hw *hw)
|
|
|
|
{
|
|
|
|
uint32_t pba;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Packet Buffer Allocation (PBA)
|
|
|
|
* Writing PBA sets the receive portion of the buffer
|
|
|
|
* the remainder is used for the transmit buffer.
|
|
|
|
* Devices before the 82547 had a Packet Buffer of 64K.
|
|
|
|
* After the 82547 the buffer was reduced to 40K.
|
|
|
|
*/
|
|
|
|
switch (hw->mac.type) {
|
|
|
|
case e1000_82547:
|
|
|
|
case e1000_82547_rev_2:
|
|
|
|
/* 82547: Total Packet Buffer is 40K */
|
|
|
|
pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
|
|
|
|
break;
|
|
|
|
case e1000_82571:
|
|
|
|
case e1000_82572:
|
|
|
|
case e1000_80003es2lan:
|
|
|
|
pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
|
|
|
|
break;
|
|
|
|
case e1000_82573: /* 82573: Total Packet Buffer is 32K */
|
|
|
|
pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
|
|
|
|
break;
|
|
|
|
case e1000_82574:
|
|
|
|
case e1000_82583:
|
|
|
|
pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
|
|
|
|
break;
|
|
|
|
case e1000_ich8lan:
|
|
|
|
pba = E1000_PBA_8K;
|
|
|
|
break;
|
|
|
|
case e1000_ich9lan:
|
|
|
|
case e1000_ich10lan:
|
|
|
|
pba = E1000_PBA_10K;
|
|
|
|
break;
|
|
|
|
case e1000_pchlan:
|
|
|
|
case e1000_pch2lan:
|
2016-03-02 13:59:34 +00:00
|
|
|
case e1000_pch_lpt:
|
2016-11-23 17:23:00 +00:00
|
|
|
case e1000_pch_spt:
|
|
|
|
case e1000_pch_cnp:
|
2012-12-19 23:00:00 +00:00
|
|
|
pba = E1000_PBA_26K;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
|
|
|
|
}
|
|
|
|
|
|
|
|
E1000_WRITE_REG(hw, E1000_PBA, pba);
|
|
|
|
}
|
|
|
|
|
2017-10-20 03:23:39 +00:00
|
|
|
static void
|
|
|
|
eth_em_rxtx_control(struct rte_eth_dev *dev,
|
|
|
|
bool enable)
|
|
|
|
{
|
|
|
|
struct e1000_hw *hw =
|
|
|
|
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
|
|
uint32_t tctl, rctl;
|
|
|
|
|
|
|
|
tctl = E1000_READ_REG(hw, E1000_TCTL);
|
|
|
|
rctl = E1000_READ_REG(hw, E1000_RCTL);
|
|
|
|
if (enable) {
|
|
|
|
/* enable Tx/Rx */
|
|
|
|
tctl |= E1000_TCTL_EN;
|
|
|
|
rctl |= E1000_RCTL_EN;
|
|
|
|
} else {
|
|
|
|
/* disable Tx/Rx */
|
|
|
|
tctl &= ~E1000_TCTL_EN;
|
|
|
|
rctl &= ~E1000_RCTL_EN;
|
|
|
|
}
|
|
|
|
E1000_WRITE_REG(hw, E1000_TCTL, tctl);
|
|
|
|
E1000_WRITE_REG(hw, E1000_RCTL, rctl);
|
|
|
|
E1000_WRITE_FLUSH(hw);
|
|
|
|
}
|
|
|
|
|
2012-12-19 23:00:00 +00:00
|
|
|
static int
|
|
|
|
eth_em_start(struct rte_eth_dev *dev)
|
|
|
|
{
|
2015-07-03 14:38:26 +00:00
|
|
|
struct e1000_adapter *adapter =
|
|
|
|
E1000_DEV_PRIVATE(dev->data->dev_private);
|
2012-12-19 23:00:00 +00:00
|
|
|
struct e1000_hw *hw =
|
|
|
|
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
2017-05-15 10:24:03 +00:00
|
|
|
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
|
2016-12-23 15:57:56 +00:00
|
|
|
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
|
2012-12-19 23:00:00 +00:00
|
|
|
int ret, mask;
|
2015-10-29 09:18:41 +00:00
|
|
|
uint32_t intr_vector = 0;
|
2016-03-31 22:12:29 +00:00
|
|
|
uint32_t *speeds;
|
|
|
|
int num_speeds;
|
|
|
|
bool autoneg;
|
2012-12-19 23:00:00 +00:00
|
|
|
|
2014-09-17 13:46:49 +00:00
|
|
|
PMD_INIT_FUNC_TRACE();
|
2012-12-19 23:00:00 +00:00
|
|
|
|
2020-10-15 13:30:45 +00:00
|
|
|
ret = eth_em_stop(dev);
|
|
|
|
if (ret != 0)
|
|
|
|
return ret;
|
2012-12-19 23:00:00 +00:00
|
|
|
|
|
|
|
e1000_power_up_phy(hw);
|
|
|
|
|
|
|
|
/* Set default PBA value */
|
|
|
|
em_set_pba(hw);
|
|
|
|
|
|
|
|
/* Put the address into the Receive Address Array */
|
|
|
|
e1000_rar_set(hw, hw->mac.addr, 0);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* With the 82571 adapter, RAR[0] may be overwritten
|
|
|
|
* when the other port is reset, we make a duplicate
|
|
|
|
* in RAR[14] for that eventuality, this assures
|
|
|
|
* the interface continues to function.
|
|
|
|
*/
|
|
|
|
if (hw->mac.type == e1000_82571) {
|
|
|
|
e1000_set_laa_state_82571(hw, TRUE);
|
|
|
|
e1000_rar_set(hw, hw->mac.addr, E1000_RAR_ENTRIES - 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Initialize the hardware */
|
|
|
|
if (em_hardware_init(hw)) {
|
|
|
|
PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
|
2016-01-27 13:58:30 +00:00
|
|
|
return -EIO;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
2019-05-21 16:13:05 +00:00
|
|
|
E1000_WRITE_REG(hw, E1000_VET, RTE_ETHER_TYPE_VLAN);
|
2012-12-19 23:00:00 +00:00
|
|
|
|
|
|
|
/* Configure for OS presence */
|
|
|
|
em_init_manageability(hw);
|
|
|
|
|
2015-10-29 09:18:41 +00:00
|
|
|
if (dev->data->dev_conf.intr_conf.rxq != 0) {
|
|
|
|
intr_vector = dev->data->nb_rx_queues;
|
|
|
|
if (rte_intr_efd_enable(intr_handle, intr_vector))
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (rte_intr_dp_is_en(intr_handle)) {
|
|
|
|
intr_handle->intr_vec =
|
|
|
|
rte_zmalloc("intr_vec",
|
|
|
|
dev->data->nb_rx_queues * sizeof(int), 0);
|
|
|
|
if (intr_handle->intr_vec == NULL) {
|
|
|
|
PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
|
2017-01-27 15:16:32 +00:00
|
|
|
" intr_vec", dev->data->nb_rx_queues);
|
2015-10-29 09:18:41 +00:00
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* enable rx interrupt */
|
|
|
|
em_rxq_intr_enable(hw);
|
|
|
|
}
|
|
|
|
|
2012-12-19 23:00:00 +00:00
|
|
|
eth_em_tx_init(dev);
|
|
|
|
|
|
|
|
ret = eth_em_rx_init(dev);
|
|
|
|
if (ret) {
|
|
|
|
PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
|
|
|
|
em_dev_clear_queues(dev);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
e1000_clear_hw_cntrs_base_generic(hw);
|
|
|
|
|
|
|
|
mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK | \
|
|
|
|
ETH_VLAN_EXTEND_MASK;
|
2017-09-01 02:36:28 +00:00
|
|
|
ret = eth_em_vlan_offload_set(dev, mask);
|
|
|
|
if (ret) {
|
|
|
|
PMD_INIT_LOG(ERR, "Unable to update vlan offload");
|
|
|
|
em_dev_clear_queues(dev);
|
|
|
|
return ret;
|
|
|
|
}
|
2012-12-19 23:00:00 +00:00
|
|
|
|
|
|
|
/* Set Interrupt Throttling Rate to maximum allowed value. */
|
|
|
|
E1000_WRITE_REG(hw, E1000_ITR, UINT16_MAX);
|
|
|
|
|
|
|
|
/* Setup link speed and duplex */
|
2016-03-31 22:12:29 +00:00
|
|
|
speeds = &dev->data->dev_conf.link_speeds;
|
|
|
|
if (*speeds == ETH_LINK_SPEED_AUTONEG) {
|
|
|
|
hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
|
2016-11-02 23:36:55 +00:00
|
|
|
hw->mac.autoneg = 1;
|
2016-03-31 22:12:29 +00:00
|
|
|
} else {
|
|
|
|
num_speeds = 0;
|
|
|
|
autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
|
|
|
|
|
|
|
|
/* Reset */
|
|
|
|
hw->phy.autoneg_advertised = 0;
|
|
|
|
|
|
|
|
if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
|
|
|
|
ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
|
|
|
|
ETH_LINK_SPEED_1G | ETH_LINK_SPEED_FIXED)) {
|
|
|
|
num_speeds = -1;
|
2012-12-19 23:00:00 +00:00
|
|
|
goto error_invalid_config;
|
2016-03-31 22:12:29 +00:00
|
|
|
}
|
|
|
|
if (*speeds & ETH_LINK_SPEED_10M_HD) {
|
|
|
|
hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
|
|
|
|
num_speeds++;
|
|
|
|
}
|
|
|
|
if (*speeds & ETH_LINK_SPEED_10M) {
|
|
|
|
hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
|
|
|
|
num_speeds++;
|
|
|
|
}
|
|
|
|
if (*speeds & ETH_LINK_SPEED_100M_HD) {
|
|
|
|
hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
|
|
|
|
num_speeds++;
|
|
|
|
}
|
|
|
|
if (*speeds & ETH_LINK_SPEED_100M) {
|
|
|
|
hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
|
|
|
|
num_speeds++;
|
|
|
|
}
|
|
|
|
if (*speeds & ETH_LINK_SPEED_1G) {
|
|
|
|
hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
|
|
|
|
num_speeds++;
|
|
|
|
}
|
|
|
|
if (num_speeds == 0 || (!autoneg && (num_speeds > 1)))
|
2012-12-19 23:00:00 +00:00
|
|
|
goto error_invalid_config;
|
2016-11-02 23:36:55 +00:00
|
|
|
|
|
|
|
/* Set/reset the mac.autoneg based on the link speed,
|
|
|
|
* fixed or not
|
|
|
|
*/
|
|
|
|
if (!autoneg) {
|
|
|
|
hw->mac.autoneg = 0;
|
|
|
|
hw->mac.forced_speed_duplex =
|
|
|
|
hw->phy.autoneg_advertised;
|
|
|
|
} else {
|
|
|
|
hw->mac.autoneg = 1;
|
|
|
|
}
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
2016-03-31 22:12:29 +00:00
|
|
|
|
2012-12-19 23:00:00 +00:00
|
|
|
e1000_setup_link(hw);
|
|
|
|
|
2015-10-29 09:18:41 +00:00
|
|
|
if (rte_intr_allow_others(intr_handle)) {
|
|
|
|
/* check if lsc interrupt is enabled */
|
2016-03-22 21:37:14 +00:00
|
|
|
if (dev->data->dev_conf.intr_conf.lsc != 0) {
|
2015-10-29 09:18:41 +00:00
|
|
|
ret = eth_em_interrupt_setup(dev);
|
|
|
|
if (ret) {
|
|
|
|
PMD_INIT_LOG(ERR, "Unable to setup interrupts");
|
|
|
|
em_dev_clear_queues(dev);
|
|
|
|
return ret;
|
|
|
|
}
|
2016-03-22 21:37:14 +00:00
|
|
|
}
|
2015-10-29 09:18:41 +00:00
|
|
|
} else {
|
|
|
|
rte_intr_callback_unregister(intr_handle,
|
|
|
|
eth_em_interrupt_handler,
|
|
|
|
(void *)dev);
|
|
|
|
if (dev->data->dev_conf.intr_conf.lsc != 0)
|
|
|
|
PMD_INIT_LOG(INFO, "lsc won't enable because of"
|
2017-01-27 15:16:32 +00:00
|
|
|
" no intr multiplexn");
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
2015-10-29 09:18:38 +00:00
|
|
|
/* check if rxq interrupt is enabled */
|
|
|
|
if (dev->data->dev_conf.intr_conf.rxq != 0)
|
|
|
|
eth_em_rxq_interrupt_setup(dev);
|
2012-12-19 23:00:00 +00:00
|
|
|
|
2015-10-29 09:18:41 +00:00
|
|
|
rte_intr_enable(intr_handle);
|
|
|
|
|
2015-07-03 14:38:26 +00:00
|
|
|
adapter->stopped = 0;
|
|
|
|
|
2017-10-20 03:23:39 +00:00
|
|
|
eth_em_rxtx_control(dev, true);
|
|
|
|
eth_em_link_update(dev, 0);
|
|
|
|
|
2012-12-19 23:00:00 +00:00
|
|
|
PMD_INIT_LOG(DEBUG, "<<");
|
|
|
|
|
2016-01-27 13:58:30 +00:00
|
|
|
return 0;
|
2012-12-19 23:00:00 +00:00
|
|
|
|
|
|
|
error_invalid_config:
|
2016-03-31 22:12:29 +00:00
|
|
|
PMD_INIT_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
|
|
|
|
dev->data->dev_conf.link_speeds, dev->data->port_id);
|
2012-12-19 23:00:00 +00:00
|
|
|
em_dev_clear_queues(dev);
|
2016-01-27 13:58:30 +00:00
|
|
|
return -EINVAL;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*********************************************************************
|
|
|
|
*
|
|
|
|
* This routine disables all traffic on the adapter by issuing a
|
|
|
|
* global reset on the MAC.
|
|
|
|
*
|
|
|
|
**********************************************************************/
|
2020-10-15 13:30:45 +00:00
|
|
|
static int
|
2012-12-19 23:00:00 +00:00
|
|
|
eth_em_stop(struct rte_eth_dev *dev)
|
|
|
|
{
|
|
|
|
struct rte_eth_link link;
|
|
|
|
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
2017-05-15 10:24:03 +00:00
|
|
|
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
|
2016-12-23 15:57:56 +00:00
|
|
|
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
|
2012-12-19 23:00:00 +00:00
|
|
|
|
2020-10-16 13:32:57 +00:00
|
|
|
dev->data->dev_started = 0;
|
|
|
|
|
2017-10-20 03:23:39 +00:00
|
|
|
eth_em_rxtx_control(dev, false);
|
2015-10-29 09:18:39 +00:00
|
|
|
em_rxq_intr_disable(hw);
|
|
|
|
em_lsc_intr_disable(hw);
|
|
|
|
|
2012-12-19 23:00:00 +00:00
|
|
|
e1000_reset_hw(hw);
|
2019-07-22 15:11:52 +00:00
|
|
|
|
|
|
|
/* Flush desc rings for i219 */
|
2019-09-10 17:40:55 +00:00
|
|
|
if (hw->mac.type == e1000_pch_spt || hw->mac.type == e1000_pch_cnp)
|
2019-07-22 15:11:52 +00:00
|
|
|
em_flush_desc_rings(dev);
|
|
|
|
|
2012-12-19 23:00:00 +00:00
|
|
|
if (hw->mac.type >= e1000_82544)
|
|
|
|
E1000_WRITE_REG(hw, E1000_WUC, 0);
|
|
|
|
|
|
|
|
/* Power down the phy. Needed to make the link go down */
|
|
|
|
e1000_power_down_phy(hw);
|
|
|
|
|
|
|
|
em_dev_clear_queues(dev);
|
|
|
|
|
|
|
|
/* clear the recorded link status */
|
|
|
|
memset(&link, 0, sizeof(link));
|
2018-01-26 02:01:43 +00:00
|
|
|
rte_eth_linkstatus_set(dev, &link);
|
2015-10-29 09:18:41 +00:00
|
|
|
|
|
|
|
if (!rte_intr_allow_others(intr_handle))
|
|
|
|
/* resume to the default handler */
|
|
|
|
rte_intr_callback_register(intr_handle,
|
|
|
|
eth_em_interrupt_handler,
|
|
|
|
(void *)dev);
|
|
|
|
|
|
|
|
/* Clean datapath event and queue/vec mapping */
|
|
|
|
rte_intr_efd_disable(intr_handle);
|
|
|
|
if (intr_handle->intr_vec != NULL) {
|
|
|
|
rte_free(intr_handle->intr_vec);
|
|
|
|
intr_handle->intr_vec = NULL;
|
|
|
|
}
|
2020-10-15 13:30:45 +00:00
|
|
|
|
|
|
|
return 0;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
2020-09-28 23:14:10 +00:00
|
|
|
static int
|
2012-12-19 23:00:00 +00:00
|
|
|
eth_em_close(struct rte_eth_dev *dev)
|
|
|
|
{
|
|
|
|
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
2015-07-03 14:38:26 +00:00
|
|
|
struct e1000_adapter *adapter =
|
|
|
|
E1000_DEV_PRIVATE(dev->data->dev_private);
|
2019-09-27 09:09:44 +00:00
|
|
|
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
|
|
|
|
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
|
2020-10-15 13:30:45 +00:00
|
|
|
int ret;
|
2012-12-19 23:00:00 +00:00
|
|
|
|
2020-09-28 23:14:31 +00:00
|
|
|
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
|
|
|
|
return 0;
|
|
|
|
|
2020-10-15 13:30:45 +00:00
|
|
|
ret = eth_em_stop(dev);
|
2015-07-03 14:38:26 +00:00
|
|
|
adapter->stopped = 1;
|
2015-07-03 14:38:27 +00:00
|
|
|
em_dev_free_queues(dev);
|
2012-12-19 23:00:00 +00:00
|
|
|
e1000_phy_hw_reset(hw);
|
|
|
|
em_release_manageability(hw);
|
|
|
|
em_hw_control_release(hw);
|
2019-09-27 09:09:44 +00:00
|
|
|
|
|
|
|
/* disable uio intr before callback unregister */
|
|
|
|
rte_intr_disable(intr_handle);
|
|
|
|
rte_intr_callback_unregister(intr_handle,
|
|
|
|
eth_em_interrupt_handler, dev);
|
2020-09-28 23:14:10 +00:00
|
|
|
|
2020-10-15 13:30:45 +00:00
|
|
|
return ret;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
em_get_rx_buffer_size(struct e1000_hw *hw)
|
|
|
|
{
|
|
|
|
uint32_t rx_buf_size;
|
|
|
|
|
|
|
|
rx_buf_size = ((E1000_READ_REG(hw, E1000_PBA) & UINT16_MAX) << 10);
|
|
|
|
return rx_buf_size;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*********************************************************************
|
|
|
|
*
|
|
|
|
* Initialize the hardware
|
|
|
|
*
|
|
|
|
**********************************************************************/
|
|
|
|
static int
|
|
|
|
em_hardware_init(struct e1000_hw *hw)
|
|
|
|
{
|
|
|
|
uint32_t rx_buf_size;
|
|
|
|
int diag;
|
|
|
|
|
|
|
|
/* Issue a global reset */
|
|
|
|
e1000_reset_hw(hw);
|
|
|
|
|
|
|
|
/* Let the firmware know the OS is in control */
|
|
|
|
em_hw_control_acquire(hw);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* These parameters control the automatic generation (Tx) and
|
|
|
|
* response (Rx) to Ethernet PAUSE frames.
|
|
|
|
* - High water mark should allow for at least two standard size (1518)
|
|
|
|
* frames to be received after sending an XOFF.
|
|
|
|
* - Low water mark works best when it is very near the high water mark.
|
|
|
|
* This allows the receiver to restart by sending XON when it has
|
2014-05-02 23:42:52 +00:00
|
|
|
* drained a bit. Here we use an arbitrary value of 1500 which will
|
2012-12-19 23:00:00 +00:00
|
|
|
* restart after one full frame is pulled from the buffer. There
|
|
|
|
* could be several smaller frames in the buffer and if so they will
|
|
|
|
* not trigger the XON until their total number reduces the buffer
|
|
|
|
* by 1500.
|
|
|
|
* - The pause time is fairly large at 1000 x 512ns = 512 usec.
|
|
|
|
*/
|
|
|
|
rx_buf_size = em_get_rx_buffer_size(hw);
|
|
|
|
|
2019-05-21 16:13:05 +00:00
|
|
|
hw->fc.high_water = rx_buf_size -
|
|
|
|
PMD_ROUNDUP(RTE_ETHER_MAX_LEN * 2, 1024);
|
2012-12-19 23:00:00 +00:00
|
|
|
hw->fc.low_water = hw->fc.high_water - 1500;
|
|
|
|
|
|
|
|
if (hw->mac.type == e1000_80003es2lan)
|
|
|
|
hw->fc.pause_time = UINT16_MAX;
|
|
|
|
else
|
|
|
|
hw->fc.pause_time = EM_FC_PAUSE_TIME;
|
|
|
|
|
|
|
|
hw->fc.send_xon = 1;
|
|
|
|
|
|
|
|
/* Set Flow control, use the tunable location if sane */
|
|
|
|
if (em_fc_setting <= e1000_fc_full)
|
|
|
|
hw->fc.requested_mode = em_fc_setting;
|
|
|
|
else
|
|
|
|
hw->fc.requested_mode = e1000_fc_none;
|
|
|
|
|
|
|
|
/* Workaround: no TX flow ctrl for PCH */
|
|
|
|
if (hw->mac.type == e1000_pchlan)
|
|
|
|
hw->fc.requested_mode = e1000_fc_rx_pause;
|
|
|
|
|
|
|
|
/* Override - settings for PCH2LAN, ya its magic :) */
|
|
|
|
if (hw->mac.type == e1000_pch2lan) {
|
|
|
|
hw->fc.high_water = 0x5C20;
|
|
|
|
hw->fc.low_water = 0x5048;
|
|
|
|
hw->fc.pause_time = 0x0650;
|
|
|
|
hw->fc.refresh_time = 0x0400;
|
2016-11-23 17:23:00 +00:00
|
|
|
} else if (hw->mac.type == e1000_pch_lpt ||
|
|
|
|
hw->mac.type == e1000_pch_spt ||
|
|
|
|
hw->mac.type == e1000_pch_cnp) {
|
2016-03-02 13:59:34 +00:00
|
|
|
hw->fc.requested_mode = e1000_fc_full;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
diag = e1000_init_hw(hw);
|
|
|
|
if (diag < 0)
|
2016-01-27 13:58:30 +00:00
|
|
|
return diag;
|
2012-12-19 23:00:00 +00:00
|
|
|
e1000_check_for_link(hw);
|
2016-01-27 13:58:30 +00:00
|
|
|
return 0;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* This function is based on em_update_stats_counters() in e1000/if_em.c */
|
2017-10-10 20:20:18 +00:00
|
|
|
static int
|
2012-12-19 23:00:00 +00:00
|
|
|
eth_em_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
|
|
|
|
{
|
|
|
|
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
|
|
struct e1000_hw_stats *stats =
|
|
|
|
E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
|
|
|
|
int pause_frames;
|
|
|
|
|
|
|
|
if(hw->phy.media_type == e1000_media_type_copper ||
|
|
|
|
(E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
|
|
|
|
stats->symerrs += E1000_READ_REG(hw,E1000_SYMERRS);
|
|
|
|
stats->sec += E1000_READ_REG(hw, E1000_SEC);
|
|
|
|
}
|
|
|
|
|
|
|
|
stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
|
|
|
|
stats->mpc += E1000_READ_REG(hw, E1000_MPC);
|
|
|
|
stats->scc += E1000_READ_REG(hw, E1000_SCC);
|
|
|
|
stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
|
|
|
|
|
|
|
|
stats->mcc += E1000_READ_REG(hw, E1000_MCC);
|
|
|
|
stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
|
|
|
|
stats->colc += E1000_READ_REG(hw, E1000_COLC);
|
|
|
|
stats->dc += E1000_READ_REG(hw, E1000_DC);
|
|
|
|
stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
|
|
|
|
stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
|
|
|
|
stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* For watchdog management we need to know if we have been
|
|
|
|
* paused during the last interval, so capture that here.
|
|
|
|
*/
|
|
|
|
pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
|
|
|
|
stats->xoffrxc += pause_frames;
|
|
|
|
stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
|
|
|
|
stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
|
|
|
|
stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
|
|
|
|
stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
|
|
|
|
stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
|
|
|
|
stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
|
|
|
|
stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
|
|
|
|
stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
|
|
|
|
stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
|
|
|
|
stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
|
|
|
|
stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
|
|
|
|
stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* For the 64-bit byte counters the low dword must be read first.
|
|
|
|
* Both registers clear on the read of the high dword.
|
|
|
|
*/
|
|
|
|
|
|
|
|
stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
|
|
|
|
stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
|
|
|
|
stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
|
|
|
|
stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
|
|
|
|
|
|
|
|
stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
|
|
|
|
stats->ruc += E1000_READ_REG(hw, E1000_RUC);
|
|
|
|
stats->rfc += E1000_READ_REG(hw, E1000_RFC);
|
|
|
|
stats->roc += E1000_READ_REG(hw, E1000_ROC);
|
|
|
|
stats->rjc += E1000_READ_REG(hw, E1000_RJC);
|
|
|
|
|
|
|
|
stats->tor += E1000_READ_REG(hw, E1000_TORH);
|
|
|
|
stats->tot += E1000_READ_REG(hw, E1000_TOTH);
|
|
|
|
|
|
|
|
stats->tpr += E1000_READ_REG(hw, E1000_TPR);
|
|
|
|
stats->tpt += E1000_READ_REG(hw, E1000_TPT);
|
|
|
|
stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
|
|
|
|
stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
|
|
|
|
stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
|
|
|
|
stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
|
|
|
|
stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
|
|
|
|
stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
|
|
|
|
stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
|
|
|
|
stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
|
|
|
|
|
|
|
|
/* Interrupt Counts */
|
|
|
|
|
|
|
|
if (hw->mac.type >= e1000_82571) {
|
|
|
|
stats->iac += E1000_READ_REG(hw, E1000_IAC);
|
|
|
|
stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
|
|
|
|
stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
|
|
|
|
stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
|
|
|
|
stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
|
|
|
|
stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
|
|
|
|
stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
|
|
|
|
stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
|
|
|
|
stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (hw->mac.type >= e1000_82543) {
|
|
|
|
stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
|
|
|
|
stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
|
|
|
|
stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
|
|
|
|
stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
|
|
|
|
stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
|
|
|
|
stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (rte_stats == NULL)
|
2017-10-10 20:20:18 +00:00
|
|
|
return -EINVAL;
|
2012-12-19 23:00:00 +00:00
|
|
|
|
|
|
|
/* Rx Errors */
|
2014-06-12 21:55:41 +00:00
|
|
|
rte_stats->imissed = stats->mpc;
|
2021-04-01 05:21:32 +00:00
|
|
|
rte_stats->ierrors = stats->crcerrs + stats->rlec +
|
2014-06-12 21:55:41 +00:00
|
|
|
stats->rxerrc + stats->algnerrc + stats->cexterr;
|
2012-12-19 23:00:00 +00:00
|
|
|
|
|
|
|
/* Tx Errors */
|
|
|
|
rte_stats->oerrors = stats->ecol + stats->latecol;
|
|
|
|
|
|
|
|
rte_stats->ipackets = stats->gprc;
|
|
|
|
rte_stats->opackets = stats->gptc;
|
|
|
|
rte_stats->ibytes = stats->gorc;
|
|
|
|
rte_stats->obytes = stats->gotc;
|
2017-10-10 20:20:18 +00:00
|
|
|
return 0;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
2019-09-06 14:34:54 +00:00
|
|
|
static int
|
2012-12-19 23:00:00 +00:00
|
|
|
eth_em_stats_reset(struct rte_eth_dev *dev)
|
|
|
|
{
|
|
|
|
struct e1000_hw_stats *hw_stats =
|
|
|
|
E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
|
|
|
|
|
|
|
|
/* HW registers are cleared on read */
|
|
|
|
eth_em_stats_get(dev, NULL);
|
|
|
|
|
|
|
|
/* Reset software totals */
|
|
|
|
memset(hw_stats, 0, sizeof(*hw_stats));
|
2019-09-06 14:34:54 +00:00
|
|
|
|
|
|
|
return 0;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
2015-10-29 09:18:38 +00:00
|
|
|
static int
|
|
|
|
eth_em_rx_queue_intr_enable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
|
|
|
|
{
|
|
|
|
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
2017-05-15 10:24:03 +00:00
|
|
|
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
|
2016-12-23 15:57:56 +00:00
|
|
|
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
|
2015-10-29 09:18:38 +00:00
|
|
|
|
|
|
|
em_rxq_intr_enable(hw);
|
2019-07-23 08:04:19 +00:00
|
|
|
rte_intr_ack(intr_handle);
|
2015-10-29 09:18:38 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
eth_em_rx_queue_intr_disable(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id)
|
|
|
|
{
|
|
|
|
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
|
|
|
|
|
|
em_rxq_intr_disable(hw);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-04-03 02:54:55 +00:00
|
|
|
uint32_t
|
|
|
|
em_get_max_pktlen(struct rte_eth_dev *dev)
|
2012-12-19 23:00:00 +00:00
|
|
|
{
|
2018-04-03 02:54:55 +00:00
|
|
|
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
|
|
|
2012-12-19 23:00:00 +00:00
|
|
|
switch (hw->mac.type) {
|
|
|
|
case e1000_82571:
|
|
|
|
case e1000_82572:
|
|
|
|
case e1000_ich9lan:
|
|
|
|
case e1000_ich10lan:
|
|
|
|
case e1000_pch2lan:
|
2016-03-02 13:59:34 +00:00
|
|
|
case e1000_pch_lpt:
|
2016-11-23 17:23:00 +00:00
|
|
|
case e1000_pch_spt:
|
|
|
|
case e1000_pch_cnp:
|
2012-12-19 23:00:00 +00:00
|
|
|
case e1000_82574:
|
|
|
|
case e1000_80003es2lan: /* 9K Jumbo Frame size */
|
2015-07-22 09:07:43 +00:00
|
|
|
case e1000_82583:
|
2016-01-27 13:58:30 +00:00
|
|
|
return 0x2412;
|
2012-12-19 23:00:00 +00:00
|
|
|
case e1000_pchlan:
|
2016-01-27 13:58:30 +00:00
|
|
|
return 0x1000;
|
2012-12-19 23:00:00 +00:00
|
|
|
/* Adapters that do not support jumbo frames */
|
|
|
|
case e1000_ich8lan:
|
2019-05-21 16:13:05 +00:00
|
|
|
return RTE_ETHER_MAX_LEN;
|
2012-12-19 23:00:00 +00:00
|
|
|
default:
|
2016-01-27 13:58:30 +00:00
|
|
|
return MAX_JUMBO_FRAME_SIZE;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-09-12 16:42:28 +00:00
|
|
|
static int
|
2012-12-19 23:00:00 +00:00
|
|
|
eth_em_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
|
|
|
|
{
|
|
|
|
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
|
|
|
|
|
|
dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
|
2018-04-03 02:54:55 +00:00
|
|
|
dev_info->max_rx_pktlen = em_get_max_pktlen(dev);
|
2012-12-19 23:00:00 +00:00
|
|
|
dev_info->max_mac_addrs = hw->mac.rar_entry_count;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Starting with 631xESB hw supports 2 TX/RX queues per port.
|
|
|
|
* Unfortunatelly, all these nics have just one TX context.
|
|
|
|
* So we have few choises for TX:
|
|
|
|
* - Use just one TX queue.
|
|
|
|
* - Allow cksum offload only for one TX queue.
|
|
|
|
* - Don't allow TX cksum offload at all.
|
|
|
|
* For now, option #1 was chosen.
|
|
|
|
* To use second RX queue we have to use extended RX descriptor
|
|
|
|
* (Multiple Receive Queues are mutually exclusive with UDP
|
|
|
|
* fragmentation and are not supported when a legacy receive
|
|
|
|
* descriptor format is used).
|
|
|
|
* Which means separate RX routinies - as legacy nics (82540, 82545)
|
|
|
|
* don't support extended RXD.
|
|
|
|
* To avoid it we support just one RX queue for now (no RSS).
|
|
|
|
*/
|
|
|
|
|
|
|
|
dev_info->max_rx_queues = 1;
|
|
|
|
dev_info->max_tx_queues = 1;
|
2015-10-27 12:51:46 +00:00
|
|
|
|
2018-04-03 02:54:55 +00:00
|
|
|
dev_info->rx_queue_offload_capa = em_get_rx_queue_offloads_capa(dev);
|
|
|
|
dev_info->rx_offload_capa = em_get_rx_port_offloads_capa(dev) |
|
|
|
|
dev_info->rx_queue_offload_capa;
|
2018-04-03 02:54:56 +00:00
|
|
|
dev_info->tx_queue_offload_capa = em_get_tx_queue_offloads_capa(dev);
|
|
|
|
dev_info->tx_offload_capa = em_get_tx_port_offloads_capa(dev) |
|
|
|
|
dev_info->tx_queue_offload_capa;
|
2018-04-03 02:54:55 +00:00
|
|
|
|
2015-10-27 12:51:46 +00:00
|
|
|
dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
|
|
|
|
.nb_max = E1000_MAX_RING_DESC,
|
|
|
|
.nb_min = E1000_MIN_RING_DESC,
|
|
|
|
.nb_align = EM_RXD_ALIGN,
|
|
|
|
};
|
|
|
|
|
|
|
|
dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
|
|
|
|
.nb_max = E1000_MAX_RING_DESC,
|
|
|
|
.nb_min = E1000_MIN_RING_DESC,
|
|
|
|
.nb_align = EM_TXD_ALIGN,
|
2016-12-23 18:40:48 +00:00
|
|
|
.nb_seg_max = EM_TX_MAX_SEG,
|
|
|
|
.nb_mtu_seg_max = EM_TX_MAX_MTU_SEG,
|
2015-10-27 12:51:46 +00:00
|
|
|
};
|
2016-03-31 22:12:28 +00:00
|
|
|
|
|
|
|
dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
|
|
|
|
ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
|
|
|
|
ETH_LINK_SPEED_1G;
|
2018-04-10 09:43:17 +00:00
|
|
|
|
|
|
|
/* Preferred queue parameters */
|
|
|
|
dev_info->default_rxportconf.nb_queues = 1;
|
|
|
|
dev_info->default_txportconf.nb_queues = 1;
|
|
|
|
dev_info->default_txportconf.ring_size = 256;
|
|
|
|
dev_info->default_rxportconf.ring_size = 256;
|
2019-09-12 16:42:28 +00:00
|
|
|
|
|
|
|
return 0;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* return 0 means link status changed, -1 means not changed */
|
|
|
|
static int
|
|
|
|
eth_em_link_update(struct rte_eth_dev *dev, int wait_to_complete)
|
|
|
|
{
|
|
|
|
struct e1000_hw *hw =
|
|
|
|
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
2018-01-26 02:01:43 +00:00
|
|
|
struct rte_eth_link link;
|
2019-11-20 09:22:03 +00:00
|
|
|
int link_up, count;
|
2012-12-19 23:00:00 +00:00
|
|
|
|
2019-11-20 09:22:03 +00:00
|
|
|
link_up = 0;
|
2012-12-19 23:00:00 +00:00
|
|
|
hw->mac.get_link_status = 1;
|
|
|
|
|
|
|
|
/* possible wait-to-complete in up to 9 seconds */
|
|
|
|
for (count = 0; count < EM_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
|
|
|
|
/* Read the real link status */
|
|
|
|
switch (hw->phy.media_type) {
|
|
|
|
case e1000_media_type_copper:
|
|
|
|
/* Do the work to read phy */
|
|
|
|
e1000_check_for_link(hw);
|
2019-11-20 09:22:03 +00:00
|
|
|
link_up = !hw->mac.get_link_status;
|
2012-12-19 23:00:00 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case e1000_media_type_fiber:
|
|
|
|
e1000_check_for_link(hw);
|
2019-11-20 09:22:03 +00:00
|
|
|
link_up = (E1000_READ_REG(hw, E1000_STATUS) &
|
2012-12-19 23:00:00 +00:00
|
|
|
E1000_STATUS_LU);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case e1000_media_type_internal_serdes:
|
|
|
|
e1000_check_for_link(hw);
|
2019-11-20 09:22:03 +00:00
|
|
|
link_up = hw->mac.serdes_has_link;
|
2012-12-19 23:00:00 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2019-11-20 09:22:03 +00:00
|
|
|
if (link_up || wait_to_complete == 0)
|
2012-12-19 23:00:00 +00:00
|
|
|
break;
|
|
|
|
rte_delay_ms(EM_LINK_UPDATE_CHECK_INTERVAL);
|
|
|
|
}
|
|
|
|
memset(&link, 0, sizeof(link));
|
|
|
|
|
|
|
|
/* Now we check if a transition has happened */
|
2019-11-20 09:22:03 +00:00
|
|
|
if (link_up) {
|
2016-03-31 22:12:29 +00:00
|
|
|
uint16_t duplex, speed;
|
|
|
|
hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
|
|
|
|
link.link_duplex = (duplex == FULL_DUPLEX) ?
|
|
|
|
ETH_LINK_FULL_DUPLEX :
|
|
|
|
ETH_LINK_HALF_DUPLEX;
|
|
|
|
link.link_speed = speed;
|
2016-03-31 22:12:24 +00:00
|
|
|
link.link_status = ETH_LINK_UP;
|
2016-03-31 22:12:29 +00:00
|
|
|
link.link_autoneg = !(dev->data->dev_conf.link_speeds &
|
|
|
|
ETH_LINK_SPEED_FIXED);
|
2019-11-20 09:22:03 +00:00
|
|
|
} else {
|
2018-04-17 11:30:35 +00:00
|
|
|
link.link_speed = ETH_SPEED_NUM_NONE;
|
2016-03-31 22:12:25 +00:00
|
|
|
link.link_duplex = ETH_LINK_HALF_DUPLEX;
|
2016-03-31 22:12:24 +00:00
|
|
|
link.link_status = ETH_LINK_DOWN;
|
2018-01-05 17:38:55 +00:00
|
|
|
link.link_autoneg = ETH_LINK_FIXED;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
2018-01-26 02:01:43 +00:00
|
|
|
return rte_eth_linkstatus_set(dev, &link);
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* em_hw_control_acquire sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
|
|
|
|
* For ASF and Pass Through versions of f/w this means
|
|
|
|
* that the driver is loaded. For AMT version type f/w
|
|
|
|
* this means that the network i/f is open.
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
em_hw_control_acquire(struct e1000_hw *hw)
|
|
|
|
{
|
|
|
|
uint32_t ctrl_ext, swsm;
|
|
|
|
|
|
|
|
/* Let firmware know the driver has taken over */
|
|
|
|
if (hw->mac.type == e1000_82573) {
|
|
|
|
swsm = E1000_READ_REG(hw, E1000_SWSM);
|
|
|
|
E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD);
|
|
|
|
|
|
|
|
} else {
|
|
|
|
ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
|
|
|
|
E1000_WRITE_REG(hw, E1000_CTRL_EXT,
|
|
|
|
ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* em_hw_control_release resets {CTRL_EXTT|FWSM}:DRV_LOAD bit.
|
|
|
|
* For ASF and Pass Through versions of f/w this means that the
|
|
|
|
* driver is no longer loaded. For AMT versions of the
|
|
|
|
* f/w this means that the network i/f is closed.
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
em_hw_control_release(struct e1000_hw *hw)
|
|
|
|
{
|
|
|
|
uint32_t ctrl_ext, swsm;
|
|
|
|
|
|
|
|
/* Let firmware taken over control of h/w */
|
|
|
|
if (hw->mac.type == e1000_82573) {
|
|
|
|
swsm = E1000_READ_REG(hw, E1000_SWSM);
|
|
|
|
E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
|
|
|
|
} else {
|
|
|
|
ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
|
|
|
|
E1000_WRITE_REG(hw, E1000_CTRL_EXT,
|
|
|
|
ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Bit of a misnomer, what this really means is
|
|
|
|
* to enable OS management of the system... aka
|
|
|
|
* to disable special hardware management features.
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
em_init_manageability(struct e1000_hw *hw)
|
|
|
|
{
|
|
|
|
if (e1000_enable_mng_pass_thru(hw)) {
|
|
|
|
uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
|
|
|
|
uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
|
|
|
|
|
|
|
|
/* disable hardware interception of ARP */
|
|
|
|
manc &= ~(E1000_MANC_ARP_EN);
|
|
|
|
|
|
|
|
/* enable receiving management packets to the host */
|
|
|
|
manc |= E1000_MANC_EN_MNG2HOST;
|
|
|
|
manc2h |= 1 << 5; /* Mng Port 623 */
|
|
|
|
manc2h |= 1 << 6; /* Mng Port 664 */
|
|
|
|
E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
|
|
|
|
E1000_WRITE_REG(hw, E1000_MANC, manc);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Give control back to hardware management
|
|
|
|
* controller if there is one.
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
em_release_manageability(struct e1000_hw *hw)
|
|
|
|
{
|
|
|
|
uint32_t manc;
|
|
|
|
|
|
|
|
if (e1000_enable_mng_pass_thru(hw)) {
|
|
|
|
manc = E1000_READ_REG(hw, E1000_MANC);
|
|
|
|
|
|
|
|
/* re-enable hardware interception of ARP */
|
|
|
|
manc |= E1000_MANC_ARP_EN;
|
|
|
|
manc &= ~E1000_MANC_EN_MNG2HOST;
|
|
|
|
|
|
|
|
E1000_WRITE_REG(hw, E1000_MANC, manc);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-09-14 11:37:24 +00:00
|
|
|
static int
|
2012-12-19 23:00:00 +00:00
|
|
|
eth_em_promiscuous_enable(struct rte_eth_dev *dev)
|
|
|
|
{
|
|
|
|
struct e1000_hw *hw =
|
|
|
|
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
|
|
uint32_t rctl;
|
|
|
|
|
|
|
|
rctl = E1000_READ_REG(hw, E1000_RCTL);
|
|
|
|
rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
|
|
|
|
E1000_WRITE_REG(hw, E1000_RCTL, rctl);
|
2019-09-14 11:37:24 +00:00
|
|
|
|
|
|
|
return 0;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
2019-09-14 11:37:24 +00:00
|
|
|
static int
|
2012-12-19 23:00:00 +00:00
|
|
|
eth_em_promiscuous_disable(struct rte_eth_dev *dev)
|
|
|
|
{
|
|
|
|
struct e1000_hw *hw =
|
|
|
|
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
|
|
uint32_t rctl;
|
|
|
|
|
|
|
|
rctl = E1000_READ_REG(hw, E1000_RCTL);
|
|
|
|
rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_SBP);
|
|
|
|
if (dev->data->all_multicast == 1)
|
|
|
|
rctl |= E1000_RCTL_MPE;
|
|
|
|
else
|
|
|
|
rctl &= (~E1000_RCTL_MPE);
|
|
|
|
E1000_WRITE_REG(hw, E1000_RCTL, rctl);
|
2019-09-14 11:37:24 +00:00
|
|
|
|
|
|
|
return 0;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
2019-09-24 12:56:10 +00:00
|
|
|
static int
|
2012-12-19 23:00:00 +00:00
|
|
|
eth_em_allmulticast_enable(struct rte_eth_dev *dev)
|
|
|
|
{
|
|
|
|
struct e1000_hw *hw =
|
|
|
|
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
|
|
uint32_t rctl;
|
|
|
|
|
|
|
|
rctl = E1000_READ_REG(hw, E1000_RCTL);
|
|
|
|
rctl |= E1000_RCTL_MPE;
|
|
|
|
E1000_WRITE_REG(hw, E1000_RCTL, rctl);
|
2019-09-24 12:56:10 +00:00
|
|
|
|
|
|
|
return 0;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
2019-09-24 12:56:10 +00:00
|
|
|
static int
|
2012-12-19 23:00:00 +00:00
|
|
|
eth_em_allmulticast_disable(struct rte_eth_dev *dev)
|
|
|
|
{
|
|
|
|
struct e1000_hw *hw =
|
|
|
|
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
|
|
uint32_t rctl;
|
|
|
|
|
|
|
|
if (dev->data->promiscuous == 1)
|
2019-09-24 12:56:10 +00:00
|
|
|
return 0; /* must remain in all_multicast mode */
|
2012-12-19 23:00:00 +00:00
|
|
|
rctl = E1000_READ_REG(hw, E1000_RCTL);
|
|
|
|
rctl &= (~E1000_RCTL_MPE);
|
|
|
|
E1000_WRITE_REG(hw, E1000_RCTL, rctl);
|
2019-09-24 12:56:10 +00:00
|
|
|
|
|
|
|
return 0;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
eth_em_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
|
|
|
|
{
|
|
|
|
struct e1000_hw *hw =
|
|
|
|
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
|
|
struct e1000_vfta * shadow_vfta =
|
|
|
|
E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
|
|
|
|
uint32_t vfta;
|
|
|
|
uint32_t vid_idx;
|
|
|
|
uint32_t vid_bit;
|
|
|
|
|
|
|
|
vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
|
|
|
|
E1000_VFTA_ENTRY_MASK);
|
|
|
|
vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
|
|
|
|
vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
|
|
|
|
if (on)
|
|
|
|
vfta |= vid_bit;
|
|
|
|
else
|
|
|
|
vfta &= ~vid_bit;
|
|
|
|
E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
|
|
|
|
|
|
|
|
/* update local VFTA copy */
|
|
|
|
shadow_vfta->vfta[vid_idx] = vfta;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
em_vlan_hw_filter_disable(struct rte_eth_dev *dev)
|
|
|
|
{
|
|
|
|
struct e1000_hw *hw =
|
|
|
|
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
|
|
uint32_t reg;
|
|
|
|
|
|
|
|
/* Filter Table Disable */
|
|
|
|
reg = E1000_READ_REG(hw, E1000_RCTL);
|
|
|
|
reg &= ~E1000_RCTL_CFIEN;
|
|
|
|
reg &= ~E1000_RCTL_VFE;
|
|
|
|
E1000_WRITE_REG(hw, E1000_RCTL, reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
em_vlan_hw_filter_enable(struct rte_eth_dev *dev)
|
|
|
|
{
|
|
|
|
struct e1000_hw *hw =
|
|
|
|
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
|
|
struct e1000_vfta * shadow_vfta =
|
|
|
|
E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
|
|
|
|
uint32_t reg;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* Filter Table Enable, CFI not used for packet acceptance */
|
|
|
|
reg = E1000_READ_REG(hw, E1000_RCTL);
|
|
|
|
reg &= ~E1000_RCTL_CFIEN;
|
|
|
|
reg |= E1000_RCTL_VFE;
|
|
|
|
E1000_WRITE_REG(hw, E1000_RCTL, reg);
|
|
|
|
|
|
|
|
/* restore vfta from local copy */
|
|
|
|
for (i = 0; i < IGB_VFTA_SIZE; i++)
|
|
|
|
E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
em_vlan_hw_strip_disable(struct rte_eth_dev *dev)
|
|
|
|
{
|
|
|
|
struct e1000_hw *hw =
|
|
|
|
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
|
|
uint32_t reg;
|
|
|
|
|
|
|
|
/* VLAN Mode Disable */
|
|
|
|
reg = E1000_READ_REG(hw, E1000_CTRL);
|
|
|
|
reg &= ~E1000_CTRL_VME;
|
|
|
|
E1000_WRITE_REG(hw, E1000_CTRL, reg);
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
em_vlan_hw_strip_enable(struct rte_eth_dev *dev)
|
|
|
|
{
|
|
|
|
struct e1000_hw *hw =
|
|
|
|
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
|
|
uint32_t reg;
|
|
|
|
|
|
|
|
/* VLAN Mode Enable */
|
|
|
|
reg = E1000_READ_REG(hw, E1000_CTRL);
|
|
|
|
reg |= E1000_CTRL_VME;
|
|
|
|
E1000_WRITE_REG(hw, E1000_CTRL, reg);
|
|
|
|
}
|
|
|
|
|
2017-09-01 02:36:28 +00:00
|
|
|
static int
|
2012-12-19 23:00:00 +00:00
|
|
|
eth_em_vlan_offload_set(struct rte_eth_dev *dev, int mask)
|
|
|
|
{
|
2018-04-03 02:54:55 +00:00
|
|
|
struct rte_eth_rxmode *rxmode;
|
|
|
|
|
|
|
|
rxmode = &dev->data->dev_conf.rxmode;
|
2012-12-19 23:00:00 +00:00
|
|
|
if(mask & ETH_VLAN_STRIP_MASK){
|
2018-04-03 02:54:55 +00:00
|
|
|
if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
|
2012-12-19 23:00:00 +00:00
|
|
|
em_vlan_hw_strip_enable(dev);
|
|
|
|
else
|
|
|
|
em_vlan_hw_strip_disable(dev);
|
|
|
|
}
|
2014-06-03 23:42:50 +00:00
|
|
|
|
2012-12-19 23:00:00 +00:00
|
|
|
if(mask & ETH_VLAN_FILTER_MASK){
|
2018-04-03 02:54:55 +00:00
|
|
|
if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
|
2012-12-19 23:00:00 +00:00
|
|
|
em_vlan_hw_filter_enable(dev);
|
|
|
|
else
|
|
|
|
em_vlan_hw_filter_disable(dev);
|
|
|
|
}
|
2017-09-01 02:36:28 +00:00
|
|
|
|
|
|
|
return 0;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
2015-10-29 09:18:39 +00:00
|
|
|
/*
|
2012-12-19 23:00:00 +00:00
|
|
|
* It enables the interrupt mask and then enable the interrupt.
|
|
|
|
*
|
|
|
|
* @param dev
|
|
|
|
* Pointer to struct rte_eth_dev.
|
|
|
|
*
|
|
|
|
* @return
|
|
|
|
* - On success, zero.
|
|
|
|
* - On failure, a negative value.
|
|
|
|
*/
|
|
|
|
static int
|
|
|
|
eth_em_interrupt_setup(struct rte_eth_dev *dev)
|
|
|
|
{
|
2015-10-29 09:18:43 +00:00
|
|
|
uint32_t regval;
|
2012-12-19 23:00:00 +00:00
|
|
|
struct e1000_hw *hw =
|
|
|
|
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
|
|
|
2015-10-29 09:18:43 +00:00
|
|
|
/* clear interrupt */
|
|
|
|
E1000_READ_REG(hw, E1000_ICR);
|
|
|
|
regval = E1000_READ_REG(hw, E1000_IMS);
|
2018-07-27 18:13:17 +00:00
|
|
|
E1000_WRITE_REG(hw, E1000_IMS,
|
|
|
|
regval | E1000_ICR_LSC | E1000_ICR_OTHER);
|
2016-01-27 13:58:30 +00:00
|
|
|
return 0;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
2015-10-29 09:18:38 +00:00
|
|
|
/*
|
|
|
|
* It clears the interrupt causes and enables the interrupt.
|
|
|
|
* It will be called once only during nic initialized.
|
|
|
|
*
|
|
|
|
* @param dev
|
|
|
|
* Pointer to struct rte_eth_dev.
|
|
|
|
*
|
|
|
|
* @return
|
|
|
|
* - On success, zero.
|
|
|
|
* - On failure, a negative value.
|
|
|
|
*/
|
|
|
|
static int
|
|
|
|
eth_em_rxq_interrupt_setup(struct rte_eth_dev *dev)
|
|
|
|
{
|
|
|
|
struct e1000_hw *hw =
|
|
|
|
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
|
|
|
|
|
|
E1000_READ_REG(hw, E1000_ICR);
|
|
|
|
em_rxq_intr_enable(hw);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* It enable receive packet interrupt.
|
|
|
|
* @param hw
|
|
|
|
* Pointer to struct e1000_hw
|
|
|
|
*
|
|
|
|
* @return
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
em_rxq_intr_enable(struct e1000_hw *hw)
|
|
|
|
{
|
|
|
|
E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_RXT0);
|
|
|
|
E1000_WRITE_FLUSH(hw);
|
|
|
|
}
|
|
|
|
|
2015-10-29 09:18:39 +00:00
|
|
|
/*
|
|
|
|
* It disabled lsc interrupt.
|
|
|
|
* @param hw
|
|
|
|
* Pointer to struct e1000_hw
|
|
|
|
*
|
|
|
|
* @return
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
em_lsc_intr_disable(struct e1000_hw *hw)
|
|
|
|
{
|
2018-07-27 18:13:17 +00:00
|
|
|
E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_LSC | E1000_IMS_OTHER);
|
2015-10-29 09:18:39 +00:00
|
|
|
E1000_WRITE_FLUSH(hw);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* It disabled receive packet interrupt.
|
|
|
|
* @param hw
|
|
|
|
* Pointer to struct e1000_hw
|
|
|
|
*
|
|
|
|
* @return
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
em_rxq_intr_disable(struct e1000_hw *hw)
|
|
|
|
{
|
|
|
|
E1000_READ_REG(hw, E1000_ICR);
|
|
|
|
E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0);
|
|
|
|
E1000_WRITE_FLUSH(hw);
|
|
|
|
}
|
|
|
|
|
2012-12-19 23:00:00 +00:00
|
|
|
/*
|
|
|
|
* It reads ICR and gets interrupt causes, check it and set a bit flag
|
|
|
|
* to update link status.
|
|
|
|
*
|
|
|
|
* @param dev
|
|
|
|
* Pointer to struct rte_eth_dev.
|
|
|
|
*
|
|
|
|
* @return
|
|
|
|
* - On success, zero.
|
|
|
|
* - On failure, a negative value.
|
|
|
|
*/
|
|
|
|
static int
|
|
|
|
eth_em_interrupt_get_status(struct rte_eth_dev *dev)
|
|
|
|
{
|
|
|
|
uint32_t icr;
|
|
|
|
struct e1000_hw *hw =
|
|
|
|
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
|
|
struct e1000_interrupt *intr =
|
|
|
|
E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
|
|
|
|
|
|
|
|
/* read-on-clear nic registers here */
|
|
|
|
icr = E1000_READ_REG(hw, E1000_ICR);
|
|
|
|
if (icr & E1000_ICR_LSC) {
|
|
|
|
intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* It executes link_update after knowing an interrupt is prsent.
|
|
|
|
*
|
|
|
|
* @param dev
|
|
|
|
* Pointer to struct rte_eth_dev.
|
|
|
|
*
|
|
|
|
* @return
|
|
|
|
* - On success, zero.
|
|
|
|
* - On failure, a negative value.
|
|
|
|
*/
|
|
|
|
static int
|
2016-12-23 15:57:56 +00:00
|
|
|
eth_em_interrupt_action(struct rte_eth_dev *dev,
|
|
|
|
struct rte_intr_handle *intr_handle)
|
2012-12-19 23:00:00 +00:00
|
|
|
{
|
2017-05-15 10:24:03 +00:00
|
|
|
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
|
2012-12-19 23:00:00 +00:00
|
|
|
struct e1000_hw *hw =
|
|
|
|
E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
|
|
struct e1000_interrupt *intr =
|
|
|
|
E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
|
|
|
|
struct rte_eth_link link;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
|
2019-07-23 08:04:19 +00:00
|
|
|
rte_intr_ack(intr_handle);
|
2012-12-19 23:00:00 +00:00
|
|
|
|
|
|
|
/* set get_link_status to check register later */
|
|
|
|
hw->mac.get_link_status = 1;
|
|
|
|
ret = eth_em_link_update(dev, 0);
|
|
|
|
|
|
|
|
/* check if link has changed */
|
|
|
|
if (ret < 0)
|
|
|
|
return 0;
|
|
|
|
|
2018-01-26 02:01:43 +00:00
|
|
|
rte_eth_linkstatus_get(dev, &link);
|
|
|
|
|
2012-12-19 23:00:00 +00:00
|
|
|
if (link.link_status) {
|
2014-09-17 13:46:49 +00:00
|
|
|
PMD_INIT_LOG(INFO, " Port %d: Link Up - speed %u Mbps - %s",
|
2017-09-29 07:17:24 +00:00
|
|
|
dev->data->port_id, link.link_speed,
|
2014-09-17 13:46:48 +00:00
|
|
|
link.link_duplex == ETH_LINK_FULL_DUPLEX ?
|
|
|
|
"full-duplex" : "half-duplex");
|
2012-12-19 23:00:00 +00:00
|
|
|
} else {
|
2014-09-17 13:46:49 +00:00
|
|
|
PMD_INIT_LOG(INFO, " Port %d: Link Down", dev->data->port_id);
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
2020-01-13 12:20:28 +00:00
|
|
|
PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
|
2016-12-23 15:57:56 +00:00
|
|
|
pci_dev->addr.domain, pci_dev->addr.bus,
|
|
|
|
pci_dev->addr.devid, pci_dev->addr.function);
|
2015-07-09 23:01:07 +00:00
|
|
|
|
2012-12-19 23:00:00 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Interrupt handler which shall be registered at first.
|
|
|
|
*
|
|
|
|
* @param handle
|
|
|
|
* Pointer to interrupt handle.
|
|
|
|
* @param param
|
|
|
|
* The address of parameter (struct rte_eth_dev *) regsitered before.
|
|
|
|
*
|
|
|
|
* @return
|
|
|
|
* void
|
|
|
|
*/
|
|
|
|
static void
|
2017-04-06 12:42:22 +00:00
|
|
|
eth_em_interrupt_handler(void *param)
|
2012-12-19 23:00:00 +00:00
|
|
|
{
|
|
|
|
struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
|
|
|
|
|
|
|
|
eth_em_interrupt_get_status(dev);
|
2017-04-06 12:42:22 +00:00
|
|
|
eth_em_interrupt_action(dev, dev->intr_handle);
|
2020-09-09 13:01:48 +00:00
|
|
|
rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
eth_em_led_on(struct rte_eth_dev *dev)
|
|
|
|
{
|
|
|
|
struct e1000_hw *hw;
|
|
|
|
|
|
|
|
hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
2016-01-27 13:58:30 +00:00
|
|
|
return e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
eth_em_led_off(struct rte_eth_dev *dev)
|
|
|
|
{
|
|
|
|
struct e1000_hw *hw;
|
|
|
|
|
|
|
|
hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
2016-01-27 13:58:30 +00:00
|
|
|
return e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
2014-06-17 18:09:26 +00:00
|
|
|
static int
|
|
|
|
eth_em_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
|
|
|
|
{
|
|
|
|
struct e1000_hw *hw;
|
|
|
|
uint32_t ctrl;
|
|
|
|
int tx_pause;
|
|
|
|
int rx_pause;
|
|
|
|
|
|
|
|
hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
|
|
fc_conf->pause_time = hw->fc.pause_time;
|
|
|
|
fc_conf->high_water = hw->fc.high_water;
|
|
|
|
fc_conf->low_water = hw->fc.low_water;
|
|
|
|
fc_conf->send_xon = hw->fc.send_xon;
|
2014-06-17 18:09:27 +00:00
|
|
|
fc_conf->autoneg = hw->mac.autoneg;
|
2014-06-17 18:09:26 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Return rx_pause and tx_pause status according to actual setting of
|
|
|
|
* the TFCE and RFCE bits in the CTRL register.
|
|
|
|
*/
|
|
|
|
ctrl = E1000_READ_REG(hw, E1000_CTRL);
|
|
|
|
if (ctrl & E1000_CTRL_TFCE)
|
|
|
|
tx_pause = 1;
|
|
|
|
else
|
|
|
|
tx_pause = 0;
|
|
|
|
|
|
|
|
if (ctrl & E1000_CTRL_RFCE)
|
|
|
|
rx_pause = 1;
|
|
|
|
else
|
|
|
|
rx_pause = 0;
|
|
|
|
|
|
|
|
if (rx_pause && tx_pause)
|
|
|
|
fc_conf->mode = RTE_FC_FULL;
|
|
|
|
else if (rx_pause)
|
|
|
|
fc_conf->mode = RTE_FC_RX_PAUSE;
|
|
|
|
else if (tx_pause)
|
|
|
|
fc_conf->mode = RTE_FC_TX_PAUSE;
|
|
|
|
else
|
|
|
|
fc_conf->mode = RTE_FC_NONE;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-12-19 23:00:00 +00:00
|
|
|
static int
|
|
|
|
eth_em_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
|
|
|
|
{
|
|
|
|
struct e1000_hw *hw;
|
|
|
|
int err;
|
|
|
|
enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
|
|
|
|
e1000_fc_none,
|
|
|
|
e1000_fc_rx_pause,
|
|
|
|
e1000_fc_tx_pause,
|
|
|
|
e1000_fc_full
|
|
|
|
};
|
|
|
|
uint32_t rx_buf_size;
|
|
|
|
uint32_t max_high_water;
|
2013-11-08 02:00:00 +00:00
|
|
|
uint32_t rctl;
|
2012-12-19 23:00:00 +00:00
|
|
|
|
|
|
|
hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
2014-06-17 18:09:27 +00:00
|
|
|
if (fc_conf->autoneg != hw->mac.autoneg)
|
|
|
|
return -ENOTSUP;
|
2012-12-19 23:00:00 +00:00
|
|
|
rx_buf_size = em_get_rx_buffer_size(hw);
|
2014-09-17 13:46:49 +00:00
|
|
|
PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
|
2012-12-19 23:00:00 +00:00
|
|
|
|
|
|
|
/* At least reserve one Ethernet frame for watermark */
|
2019-05-21 16:13:05 +00:00
|
|
|
max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
|
2012-12-19 23:00:00 +00:00
|
|
|
if ((fc_conf->high_water > max_high_water) ||
|
2014-09-17 13:46:48 +00:00
|
|
|
(fc_conf->high_water < fc_conf->low_water)) {
|
2014-09-17 13:46:49 +00:00
|
|
|
PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value");
|
|
|
|
PMD_INIT_LOG(ERR, "high water must <= 0x%x", max_high_water);
|
2016-01-27 13:58:30 +00:00
|
|
|
return -EINVAL;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
|
|
|
|
hw->fc.pause_time = fc_conf->pause_time;
|
|
|
|
hw->fc.high_water = fc_conf->high_water;
|
|
|
|
hw->fc.low_water = fc_conf->low_water;
|
|
|
|
hw->fc.send_xon = fc_conf->send_xon;
|
|
|
|
|
|
|
|
err = e1000_setup_link_generic(hw);
|
|
|
|
if (err == E1000_SUCCESS) {
|
2013-11-08 02:00:00 +00:00
|
|
|
|
|
|
|
/* check if we want to forward MAC frames - driver doesn't have native
|
|
|
|
* capability to do that, so we'll write the registers ourselves */
|
|
|
|
|
|
|
|
rctl = E1000_READ_REG(hw, E1000_RCTL);
|
|
|
|
|
|
|
|
/* set or clear MFLCN.PMCF bit depending on configuration */
|
|
|
|
if (fc_conf->mac_ctrl_frame_fwd != 0)
|
|
|
|
rctl |= E1000_RCTL_PMCF;
|
|
|
|
else
|
|
|
|
rctl &= ~E1000_RCTL_PMCF;
|
|
|
|
|
|
|
|
E1000_WRITE_REG(hw, E1000_RCTL, rctl);
|
|
|
|
E1000_WRITE_FLUSH(hw);
|
|
|
|
|
2012-12-19 23:00:00 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-09-17 13:46:49 +00:00
|
|
|
PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x", err);
|
2016-01-27 13:58:30 +00:00
|
|
|
return -EIO;
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
2017-05-05 00:40:00 +00:00
|
|
|
static int
|
2019-05-21 16:13:03 +00:00
|
|
|
eth_em_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
|
2012-12-19 23:00:00 +00:00
|
|
|
uint32_t index, __rte_unused uint32_t pool)
|
|
|
|
{
|
|
|
|
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
|
|
|
2017-05-05 00:40:00 +00:00
|
|
|
return e1000_rar_set(hw, mac_addr->addr_bytes, index);
|
2012-12-19 23:00:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
eth_em_rar_clear(struct rte_eth_dev *dev, uint32_t index)
|
|
|
|
{
|
2019-05-21 16:13:05 +00:00
|
|
|
uint8_t addr[RTE_ETHER_ADDR_LEN];
|
2012-12-19 23:00:00 +00:00
|
|
|
struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
|
|
|
|
|
|
memset(addr, 0, sizeof(addr));
|
|
|
|
|
|
|
|
e1000_rar_set(hw, addr, index);
|
|
|
|
}
|
2014-04-21 14:59:34 +00:00
|
|
|
|
2018-04-11 16:32:51 +00:00
|
|
|
static int
|
2018-02-19 00:39:55 +00:00
|
|
|
eth_em_default_mac_addr_set(struct rte_eth_dev *dev,
|
2019-05-21 16:13:03 +00:00
|
|
|
struct rte_ether_addr *addr)
|
2018-02-19 00:39:55 +00:00
|
|
|
{
|
|
|
|
eth_em_rar_clear(dev, 0);
|
|
|
|
|
2018-04-11 16:32:51 +00:00
|
|
|
return eth_em_rar_set(dev, (void *)addr, 0, 0);
|
2018-02-19 00:39:55 +00:00
|
|
|
}
|
|
|
|
|
2014-06-17 18:09:30 +00:00
|
|
|
static int
|
|
|
|
eth_em_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
|
|
|
|
{
|
|
|
|
struct rte_eth_dev_info dev_info;
|
|
|
|
struct e1000_hw *hw;
|
|
|
|
uint32_t frame_size;
|
|
|
|
uint32_t rctl;
|
2019-09-12 16:42:28 +00:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = eth_em_infos_get(dev, &dev_info);
|
|
|
|
if (ret != 0)
|
|
|
|
return ret;
|
2014-06-17 18:09:30 +00:00
|
|
|
|
2021-01-18 07:04:11 +00:00
|
|
|
frame_size = mtu + E1000_ETH_OVERHEAD;
|
2014-06-17 18:09:30 +00:00
|
|
|
|
|
|
|
/* check that mtu is within the allowed range */
|
2019-05-21 16:13:05 +00:00
|
|
|
if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
|
2014-06-17 18:09:30 +00:00
|
|
|
return -EINVAL;
|
|
|
|
|
2021-02-19 10:03:23 +00:00
|
|
|
/*
|
|
|
|
* If device is started, refuse mtu that requires the support of
|
|
|
|
* scattered packets when this feature has not been enabled before.
|
|
|
|
*/
|
|
|
|
if (dev->data->dev_started && !dev->data->scattered_rx &&
|
|
|
|
frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
|
|
|
|
PMD_INIT_LOG(ERR, "Stop port first.");
|
2014-06-17 18:09:30 +00:00
|
|
|
return -EINVAL;
|
2021-02-19 10:03:23 +00:00
|
|
|
}
|
2014-06-17 18:09:30 +00:00
|
|
|
|
|
|
|
hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
|
|
rctl = E1000_READ_REG(hw, E1000_RCTL);
|
|
|
|
|
|
|
|
/* switch to jumbo mode if needed */
|
2021-01-18 07:04:11 +00:00
|
|
|
if (frame_size > E1000_ETH_MAX_LEN) {
|
2018-04-03 02:54:55 +00:00
|
|
|
dev->data->dev_conf.rxmode.offloads |=
|
|
|
|
DEV_RX_OFFLOAD_JUMBO_FRAME;
|
2014-06-17 18:09:30 +00:00
|
|
|
rctl |= E1000_RCTL_LPE;
|
|
|
|
} else {
|
2018-04-03 02:54:55 +00:00
|
|
|
dev->data->dev_conf.rxmode.offloads &=
|
|
|
|
~DEV_RX_OFFLOAD_JUMBO_FRAME;
|
2014-06-17 18:09:30 +00:00
|
|
|
rctl &= ~E1000_RCTL_LPE;
|
|
|
|
}
|
|
|
|
E1000_WRITE_REG(hw, E1000_RCTL, rctl);
|
|
|
|
|
|
|
|
/* update max frame size */
|
|
|
|
dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-05-28 15:05:21 +00:00
|
|
|
static int
|
|
|
|
eth_em_set_mc_addr_list(struct rte_eth_dev *dev,
|
2019-05-21 16:13:03 +00:00
|
|
|
struct rte_ether_addr *mc_addr_set,
|
2015-05-28 15:05:21 +00:00
|
|
|
uint32_t nb_mc_addr)
|
|
|
|
{
|
|
|
|
struct e1000_hw *hw;
|
|
|
|
|
|
|
|
hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
|
|
|
|
e1000_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-04-11 15:44:24 +00:00
|
|
|
RTE_PMD_REGISTER_PCI(net_e1000_em, rte_em_pmd);
|
2016-10-10 05:43:15 +00:00
|
|
|
RTE_PMD_REGISTER_PCI_TABLE(net_e1000_em, pci_id_em_map);
|
2017-05-20 13:12:37 +00:00
|
|
|
RTE_PMD_REGISTER_KMOD_DEP(net_e1000_em, "* igb_uio | uio_pci_generic | vfio-pci");
|