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numam-dpdk/drivers/net/i40e/i40e_rxtx.h

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drivers: use SPDX tag for Intel copyright files Replace the BSD license header with the SPDX tag for files with only an Intel copyright on them. Signed-off-by: Bruce Richardson <bruce.richardson@intel.com>
2017-12-19 15:49:01 +00:00
/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2010-2015 Intel Corporation
i40e: new poll mode driver Signed-off-by: Helin Zhang <helin.zhang@intel.com> Signed-off-by: Jing Chen <jing.d.chen@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com> Acked-by: Jijiang Liu <jijiang.liu@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com> Acked-by: Heqing Zhu <heqing.zhu@intel.com> Tested-by: Waterman Cao <waterman.cao@intel.com>
2014-06-05 05:08:46 +00:00
*/
#ifndef _I40E_RXTX_H_
#define _I40E_RXTX_H_
#define RTE_PMD_I40E_RX_MAX_BURST 32
i40e: add vector Rx The vPMD RX function uses the multi-buffer and SSE instructions to accelerate the RX speed, but now the pktype cannot be supported by the vPMD RX, because it will decrease the performance heavily. Signed-off-by: Zhe Tao <zhe.tao@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com>
2015-10-30 14:16:35 +00:00
#define RTE_PMD_I40E_TX_MAX_BURST 32
#define RTE_I40E_VPMD_RX_BURST 32
#define RTE_I40E_VPMD_TX_BURST 32
#define RTE_I40E_RXQ_REARM_THRESH 32
#define RTE_I40E_MAX_RX_BURST RTE_I40E_RXQ_REARM_THRESH
#define RTE_I40E_TX_MAX_FREE_BUF_SZ 64
#define RTE_I40E_DESCS_PER_LOOP 4
i40e: new poll mode driver Signed-off-by: Helin Zhang <helin.zhang@intel.com> Signed-off-by: Jing Chen <jing.d.chen@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com> Acked-by: Jijiang Liu <jijiang.liu@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com> Acked-by: Heqing Zhu <heqing.zhu@intel.com> Tested-by: Waterman Cao <waterman.cao@intel.com>
2014-06-05 05:08:46 +00:00
#define I40E_RXBUF_SZ_1024 1024
#define I40E_RXBUF_SZ_2048 2048
i40e: fix alignment of HW descriptors number According to XL710 datasheet: RX QLEN restrictions: When the PXE_MODE flag in the GLLAN_RCTL_0 register is cleared, the QLEN must be whole number of 32 descriptors. TX QLEN restrictions: When the PXE_MODE flag in the GLLAN_RCTL_0 register is cleared, the QLEN must be whole number of 32 descriptors. So make sure that for both RX and TX queues number of HW descriptors is a multiple of 32. Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Acked-by: Remy Horton <remy.horton@intel.com>
2015-09-30 19:04:30 +00:00
/* In none-PXE mode QLEN must be whole number of 32 descriptors. */
#define I40E_ALIGN_RING_DESC 32
#define I40E_MIN_RING_DESC 64
#define I40E_MAX_RING_DESC 4096
net/i40e: optimize flow director update rate This patch optimized the fdir update rate for i40e PF, by tracking whether the fdir rule being inserted into the guaranteed space or shared space. For the flows that are inserted to the guaranteed space, we assume that the insertion will always succeed as the hardware only report the "no enough space left" error. In this case, the software can directly return success and no need to retrieve the result from the hardware. When destroying a flow, we also assume the operation will succeed as the software has checked the flow is indeed in the hardware. See the fdir programming status descriptor format in the datasheet for more details. Signed-off-by: Chenmin Sun <chenmin.sun@intel.com> Reviewed-by: Jingjing Wu <jingjing.wu@intel.com>
2020-07-17 17:36:58 +00:00
#define I40E_FDIR_NUM_TX_DESC (I40E_FDIR_PRG_PKT_CNT << 1)
#define I40E_FDIR_NUM_RX_DESC (I40E_FDIR_PRG_PKT_CNT << 1)
net/i40e: add Tx preparation Signed-off-by: Tomasz Kulasek <tomaszx.kulasek@intel.com> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
2016-12-23 18:40:50 +00:00
#define I40E_MIN_TSO_MSS 256
#define I40E_MAX_TSO_MSS 9674
#define I40E_TX_MAX_SEG UINT8_MAX
#define I40E_TX_MAX_MTU_SEG 8
net/i40e: check illegal packets Some illegal packets will lead to TX/RX hang and can't recover automatically. This patch check those illegal packets and protect TX/RX from hanging. Signed-off-by: Yanglong Wu <yanglong.wu@intel.com> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
2018-06-20 02:12:47 +00:00
#define I40E_TX_MIN_PKT_LEN 17
net/i40e: support flow director on SSE Rx This commit adds an implementation to the SSE vector implementation of RX routine and moves some common defines from a c file to the header file. I40e can have 16 and 32 byte descriptors, and the Flow Director ID data and indication-bit are in different locations for each size descriptor. The support is implemented in two separate functions as they require vastly different operations. The 16B descriptor re-purposes the "filter-status" u32 field to indicate FDIR ID when the FLM bit is set. No extra loads are required, however we do have to store to mbuf->fdir.hi, which is not stored to in the RX path before this patch. The 32B descriptor requires loading the 2nd 16 bytes of each descriptor, to get the FLEXBH_STAT and FD Filter ID from qword3. The resulting data must also be stored to mbuf->fdir.hi, same as the 16B code path. Signed-off-by: Harry van Haaren <harry.van.haaren@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com> Tested-by: Mesut Ali Ergin <mesut.a.ergin@intel.com>
2019-10-09 15:20:05 +00:00
/* Shared FDIR masks between scalar / vector drivers */
#define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03
#define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01
#define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02
#define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03
#define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01
i40e: add vector Rx The vPMD RX function uses the multi-buffer and SSE instructions to accelerate the RX speed, but now the pktype cannot be supported by the vPMD RX, because it will decrease the performance heavily. Signed-off-by: Zhe Tao <zhe.tao@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com>
2015-10-30 14:16:35 +00:00
#undef container_of
#define container_of(ptr, type, member) ({ \
typeof(((type *)0)->member)(*__mptr) = (ptr); \
(type *)((char *)__mptr - offsetof(type, member)); })
#define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\
I40E_TX_DESC_CMD_EOP)
i40e: new poll mode driver Signed-off-by: Helin Zhang <helin.zhang@intel.com> Signed-off-by: Jing Chen <jing.d.chen@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com> Acked-by: Jijiang Liu <jijiang.liu@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com> Acked-by: Heqing Zhu <heqing.zhu@intel.com> Tested-by: Waterman Cao <waterman.cao@intel.com>
2014-06-05 05:08:46 +00:00
enum i40e_header_split_mode {
i40e_header_split_none = 0,
i40e_header_split_enabled = 1,
i40e_header_split_always = 2,
i40e_header_split_reserved
};
#define I40E_HEADER_SPLIT_NONE ((uint8_t)0)
#define I40E_HEADER_SPLIT_L2 ((uint8_t)(1 << 0))
#define I40E_HEADER_SPLIT_IP ((uint8_t)(1 << 1))
#define I40E_HEADER_SPLIT_UDP_TCP ((uint8_t)(1 << 2))
#define I40E_HEADER_SPLIT_SCTP ((uint8_t)(1 << 3))
#define I40E_HEADER_SPLIT_ALL (I40E_HEADER_SPLIT_L2 | \
I40E_HEADER_SPLIT_IP | \
I40E_HEADER_SPLIT_UDP_TCP | \
I40E_HEADER_SPLIT_SCTP)
/* HW desc structure, both 16-byte and 32-byte types are supported */
#ifdef RTE_LIBRTE_I40E_16BYTE_RX_DESC
#define i40e_rx_desc i40e_16byte_rx_desc
#else
#define i40e_rx_desc i40e_32byte_rx_desc
#endif
struct i40e_rx_entry {
struct rte_mbuf *mbuf;
};
/*
* Structure associated with each RX queue.
*/
struct i40e_rx_queue {
struct rte_mempool *mp; /**< mbuf pool to populate RX ring */
volatile union i40e_rx_desc *rx_ring;/**< RX ring virtual address */
uint64_t rx_ring_phys_addr; /**< RX ring DMA address */
struct i40e_rx_entry *sw_ring; /**< address of RX soft ring */
uint16_t nb_rx_desc; /**< number of RX descriptors */
uint16_t rx_free_thresh; /**< max free RX desc to hold */
uint16_t rx_tail; /**< current value of tail */
uint16_t nb_rx_hold; /**< number of held free RX desc */
struct rte_mbuf *pkt_first_seg; /**< first segment of current packet */
struct rte_mbuf *pkt_last_seg; /**< last segment of current packet */
net/i40e: fix compile error Fix the compile error when RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is disabled. Also fake_mbuf is required to be initialized and assigned to additional sw_ring entries for vector PMD independent from RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC config option. Fixes: 4861cde46116 ("i40e: new poll mode driver") Cc: stable@dpdk.org Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
2017-02-20 18:11:56 +00:00
struct rte_mbuf fake_mbuf; /**< dummy mbuf */
i40e: new poll mode driver Signed-off-by: Helin Zhang <helin.zhang@intel.com> Signed-off-by: Jing Chen <jing.d.chen@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com> Acked-by: Jijiang Liu <jijiang.liu@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com> Acked-by: Heqing Zhu <heqing.zhu@intel.com> Tested-by: Waterman Cao <waterman.cao@intel.com>
2014-06-05 05:08:46 +00:00
#ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
uint16_t rx_nb_avail; /**< number of staged packets ready */
uint16_t rx_next_avail; /**< index of next staged packets */
uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
struct rte_mbuf *rx_stage[RTE_PMD_I40E_RX_MAX_BURST * 2];
#endif
i40e: add vector Rx The vPMD RX function uses the multi-buffer and SSE instructions to accelerate the RX speed, but now the pktype cannot be supported by the vPMD RX, because it will decrease the performance heavily. Signed-off-by: Zhe Tao <zhe.tao@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com>
2015-10-30 14:16:35 +00:00
uint16_t rxrearm_nb; /**< number of remaining to be re-armed */
uint16_t rxrearm_start; /**< the idx we start the re-arming from */
uint64_t mbuf_initializer; /**< value to init mbufs */
ethdev: increase port id range Extend port_id definition from uint8_t to uint16_t in lib and drivers data structures, specifically rte_eth_dev_data. Modify the APIs, drivers and app using port_id at the same time. Fix some checkpatch issues from the original code and remove some unnecessary cast operations. release_17_11 and deprecation docs have been updated in this patch. Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com> Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
2017-09-29 07:17:24 +00:00
uint16_t port_id; /**< device port ID */
i40e: new poll mode driver Signed-off-by: Helin Zhang <helin.zhang@intel.com> Signed-off-by: Jing Chen <jing.d.chen@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com> Acked-by: Jijiang Liu <jijiang.liu@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com> Acked-by: Heqing Zhu <heqing.zhu@intel.com> Tested-by: Waterman Cao <waterman.cao@intel.com>
2014-06-05 05:08:46 +00:00
uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise */
net/i40e: cache flow director enable value in Rx queue This commit adds a fdir_enable flag in a uint8_t sized hole the rx queue structure The flag enables the rx code path to easily identify if fdir is active. This can be used to skip fdir id processing when it is not required. The flag is zero by default (as rxq is zmalloc-ed at startup), and the flag is set to 1 on configuration of a flow director rule. Signed-off-by: Harry van Haaren <harry.van.haaren@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com> Tested-by: Mesut Ali Ergin <mesut.a.ergin@intel.com>
2019-10-09 15:20:04 +00:00
uint8_t fdir_enabled; /**< 0 if FDIR disabled, 1 when enabled */
i40e: new poll mode driver Signed-off-by: Helin Zhang <helin.zhang@intel.com> Signed-off-by: Jing Chen <jing.d.chen@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com> Acked-by: Jijiang Liu <jijiang.liu@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com> Acked-by: Heqing Zhu <heqing.zhu@intel.com> Tested-by: Waterman Cao <waterman.cao@intel.com>
2014-06-05 05:08:46 +00:00
uint16_t queue_id; /**< RX queue index */
uint16_t reg_idx; /**< RX queue register index */
uint8_t drop_en; /**< if not 0, set register bit */
volatile uint8_t *qrx_tail; /**< register address of tail */
struct i40e_vsi *vsi; /**< the VSI this queue belongs to */
uint16_t rx_buf_len; /* The packet buffer size */
uint16_t rx_hdr_len; /* The header buffer size */
uint16_t max_pkt_len; /* Maximum packet length */
uint8_t hs_mode; /* Header Split mode */
bool q_set; /**< indicate if rx queue has been configured */
ethdev: rename flag for queue start and stop Rename start_?x_per_q to ?x_deferred_start and add comments. Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com> Acked-by: Thomas Monjalon <thomas.monjalon@6wind.com>
2014-09-26 05:00:53 +00:00
bool rx_deferred_start; /**< don't start this queue in dev start */
i40e: allow vector Rx and Tx usage To support FVL PMD can select which RX and TX function should be used according to the queue config. Signed-off-by: Zhe Tao <zhe.tao@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com>
2015-10-30 14:16:38 +00:00
uint16_t rx_using_sse; /**<flag indicate the usage of vPMD for rx */
i40e: support DCB mode This patch enables DCB feature on Intel XL710/X710 NICs. It includes: Receive queue classification based on traffic class Round Robin ETS schedule (rx and tx) Priority flow control Signed-off-by: Jingjing Wu <jingjing.wu@intel.com> Acked-by: Jijiang Liu <jijiang.liu@intel.com> Acked-by: Helin Zhang <helin.zhang@intel.com>
2015-10-31 15:57:25 +00:00
uint8_t dcb_tc; /**< Traffic class of rx queue */
net/i40e: convert to new Rx offloads API Ethdev Rx offloads API has changed since: commit cba7f53b717d ("ethdev: introduce Rx queue offloads API") This commit support the new Rx offloads API. Signed-off-by: Yanglong Wu <yanglong.wu@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2018-03-30 08:22:11 +00:00
uint64_t offloads; /**< Rx offload flags of DEV_RX_OFFLOAD_* */
i40e: new poll mode driver Signed-off-by: Helin Zhang <helin.zhang@intel.com> Signed-off-by: Jing Chen <jing.d.chen@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com> Acked-by: Jijiang Liu <jijiang.liu@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com> Acked-by: Heqing Zhu <heqing.zhu@intel.com> Tested-by: Waterman Cao <waterman.cao@intel.com>
2014-06-05 05:08:46 +00:00
};
struct i40e_tx_entry {
struct rte_mbuf *mbuf;
uint16_t next_id;
uint16_t last_id;
};
/*
* Structure associated with each TX queue.
*/
struct i40e_tx_queue {
uint16_t nb_tx_desc; /**< number of TX descriptors */
uint64_t tx_ring_phys_addr; /**< TX ring DMA address */
volatile struct i40e_tx_desc *tx_ring; /**< TX ring virtual address */
struct i40e_tx_entry *sw_ring; /**< virtual address of SW ring */
uint16_t tx_tail; /**< current value of tail register */
volatile uint8_t *qtx_tail; /**< register address of tail */
uint16_t nb_tx_used; /**< number of TX desc used since RS bit set */
/**< index to last TX descriptor to have been cleaned */
uint16_t last_desc_cleaned;
/**< Total number of TX descriptors ready to be allocated. */
uint16_t nb_tx_free;
ethdev: fix check of threshold for Tx freeing The parameter tx_free_thresh is not consistent between the drivers: some use it as rte_eth_tx_burst() requires, some release buffers when the number of free descriptors drop below this value. Let's use it as most fast-path code does, which is the latter, and update comments throughout the code to reflect that. Signed-off-by: Zoltan Kiss <zoltan.kiss@linaro.org> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
2015-06-23 18:43:12 +00:00
/**< Start freeing TX buffers if there are less free descriptors than
this value. */
uint16_t tx_free_thresh;
i40e: new poll mode driver Signed-off-by: Helin Zhang <helin.zhang@intel.com> Signed-off-by: Jing Chen <jing.d.chen@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com> Acked-by: Jijiang Liu <jijiang.liu@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com> Acked-by: Heqing Zhu <heqing.zhu@intel.com> Tested-by: Waterman Cao <waterman.cao@intel.com>
2014-06-05 05:08:46 +00:00
/** Number of TX descriptors to use before RS bit is set. */
uint16_t tx_rs_thresh;
uint8_t pthresh; /**< Prefetch threshold register. */
uint8_t hthresh; /**< Host threshold register. */
uint8_t wthresh; /**< Write-back threshold reg. */
ethdev: increase port id range Extend port_id definition from uint8_t to uint16_t in lib and drivers data structures, specifically rte_eth_dev_data. Modify the APIs, drivers and app using port_id at the same time. Fix some checkpatch issues from the original code and remove some unnecessary cast operations. release_17_11 and deprecation docs have been updated in this patch. Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com> Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
2017-09-29 07:17:24 +00:00
uint16_t port_id; /**< Device port identifier. */
i40e: new poll mode driver Signed-off-by: Helin Zhang <helin.zhang@intel.com> Signed-off-by: Jing Chen <jing.d.chen@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com> Acked-by: Jijiang Liu <jijiang.liu@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com> Acked-by: Heqing Zhu <heqing.zhu@intel.com> Tested-by: Waterman Cao <waterman.cao@intel.com>
2014-06-05 05:08:46 +00:00
uint16_t queue_id; /**< TX queue index. */
uint16_t reg_idx;
struct i40e_vsi *vsi; /**< the VSI this queue belongs to */
uint16_t tx_next_dd;
uint16_t tx_next_rs;
bool q_set; /**< indicate if tx queue has been configured */
ethdev: rename flag for queue start and stop Rename start_?x_per_q to ?x_deferred_start and add comments. Signed-off-by: Changchun Ouyang <changchun.ouyang@intel.com> Acked-by: Thomas Monjalon <thomas.monjalon@6wind.com>
2014-09-26 05:00:53 +00:00
bool tx_deferred_start; /**< don't start this queue in dev start */
i40e: support DCB mode This patch enables DCB feature on Intel XL710/X710 NICs. It includes: Receive queue classification based on traffic class Round Robin ETS schedule (rx and tx) Priority flow control Signed-off-by: Jingjing Wu <jingjing.wu@intel.com> Acked-by: Jijiang Liu <jijiang.liu@intel.com> Acked-by: Helin Zhang <helin.zhang@intel.com>
2015-10-31 15:57:25 +00:00
uint8_t dcb_tc; /**< Traffic class of tx queue */
net/i40e: convert to new Tx offloads API Ethdev Tx offloads API has changed since: commit cba7f53b717d ("ethdev: introduce Tx queue offloads API") This commit support the new Tx offloads API. Signed-off-by: Yanglong Wu <yanglong.wu@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2018-03-30 08:22:12 +00:00
uint64_t offloads; /**< Tx offload flags of DEV_RX_OFFLOAD_* */
i40e: new poll mode driver Signed-off-by: Helin Zhang <helin.zhang@intel.com> Signed-off-by: Jing Chen <jing.d.chen@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com> Acked-by: Jijiang Liu <jijiang.liu@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com> Acked-by: Heqing Zhu <heqing.zhu@intel.com> Tested-by: Waterman Cao <waterman.cao@intel.com>
2014-06-05 05:08:46 +00:00
};
i40e: move Tx offloads parameters to separate structure The structure size is u64 so it could be used with single cpu operation. Test report: http://www.dpdk.org/ml/archives/dev/2015-March/014467.html Signed-off-by: Jijiang Liu <jijiang.liu@intel.com> Signed-off-by: Miroslaw Walukiewicz <miroslaw.walukiewicz@intel.com> Signed-off-by: Grzegorz Galkowski <grzegorz.galkowski@intel.com> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Acked-by: Helin Zhang <helin.zhang@intel.com> Tested-by: Min Cao <min.cao@intel.com>
2015-02-26 03:37:22 +00:00
/** Offload features */
union i40e_tx_offload {
uint64_t data;
struct {
uint64_t l2_len:7; /**< L2 (MAC) Header Length. */
uint64_t l3_len:9; /**< L3 (IP) Header Length. */
i40e: enable TSO support This patch enables i40e TSO feature for both non-tunneling packet and tunneling packet. Test report: http://www.dpdk.org/ml/archives/dev/2015-March/014467.html Signed-off-by: Jijiang Liu <jijiang.liu@intel.com> Signed-off-by: Miroslaw Walukiewicz <miroslaw.walukiewicz@intel.com> Signed-off-by: Grzegorz Galkowski <grzegorz.galkowski@intel.com> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Acked-by: Helin Zhang <helin.zhang@intel.com> Tested-by: Min Cao <min.cao@intel.com>
2015-02-26 03:37:23 +00:00
uint64_t l4_len:8; /**< L4 Header Length. */
uint64_t tso_segsz:16; /**< TCP TSO segment size */
i40e: move Tx offloads parameters to separate structure The structure size is u64 so it could be used with single cpu operation. Test report: http://www.dpdk.org/ml/archives/dev/2015-March/014467.html Signed-off-by: Jijiang Liu <jijiang.liu@intel.com> Signed-off-by: Miroslaw Walukiewicz <miroslaw.walukiewicz@intel.com> Signed-off-by: Grzegorz Galkowski <grzegorz.galkowski@intel.com> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Acked-by: Helin Zhang <helin.zhang@intel.com> Tested-by: Min Cao <min.cao@intel.com>
2015-02-26 03:37:22 +00:00
uint64_t outer_l2_len:8; /**< outer L2 Header Length */
uint64_t outer_l3_len:16; /**< outer L3 Header Length */
};
};
i40e: queue start and stop Add functions to start/stop specific RX/TX queue. Support fields start_rx_per_q and start_tx_per_q. In the meanwhile, change dev_start/stop functions to call per-queue functions. Signed-off-by: Chen Jing D(Mark) <jing.d.chen@intel.com> Reviewed-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Reviewed-by: Changchun Ouyang <changchun.ouyang@intel.com> Reviewed-by: Huawei Xie <huawei.xie@intel.com> [Thomas: reword comments and merge 2 patches]
2014-08-14 07:35:01 +00:00
int i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
int i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
int i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
int i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
ethdev: query supported packet types Add a new API rte_eth_dev_get_supported_ptypes to query what packet types can be filled by a given device. The device should be already started or its PMD RX burst function already decided, since the packet types supported may vary depending on RX function. Signed-off-by: Jianfeng Tan <jianfeng.tan@intel.com> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
2016-03-14 20:50:50 +00:00
const uint32_t *i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev);
i40e: new poll mode driver Signed-off-by: Helin Zhang <helin.zhang@intel.com> Signed-off-by: Jing Chen <jing.d.chen@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com> Acked-by: Jijiang Liu <jijiang.liu@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com> Acked-by: Heqing Zhu <heqing.zhu@intel.com> Tested-by: Waterman Cao <waterman.cao@intel.com>
2014-06-05 05:08:46 +00:00
int i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
uint16_t queue_idx,
uint16_t nb_desc,
unsigned int socket_id,
const struct rte_eth_rxconf *rx_conf,
struct rte_mempool *mp);
int i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
uint16_t queue_idx,
uint16_t nb_desc,
unsigned int socket_id,
const struct rte_eth_txconf *tx_conf);
void i40e_dev_rx_queue_release(void *rxq);
void i40e_dev_tx_queue_release(void *txq);
uint16_t i40e_recv_pkts(void *rx_queue,
struct rte_mbuf **rx_pkts,
uint16_t nb_pkts);
uint16_t i40e_recv_scattered_pkts(void *rx_queue,
struct rte_mbuf **rx_pkts,
uint16_t nb_pkts);
uint16_t i40e_xmit_pkts(void *tx_queue,
struct rte_mbuf **tx_pkts,
uint16_t nb_pkts);
net/i40e: add Tx preparation Signed-off-by: Tomasz Kulasek <tomaszx.kulasek@intel.com> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
2016-12-23 18:40:50 +00:00
uint16_t i40e_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
uint16_t nb_pkts);
i40e: new poll mode driver Signed-off-by: Helin Zhang <helin.zhang@intel.com> Signed-off-by: Jing Chen <jing.d.chen@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com> Acked-by: Jijiang Liu <jijiang.liu@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com> Acked-by: Heqing Zhu <heqing.zhu@intel.com> Tested-by: Waterman Cao <waterman.cao@intel.com>
2014-06-05 05:08:46 +00:00
int i40e_tx_queue_init(struct i40e_tx_queue *txq);
int i40e_rx_queue_init(struct i40e_rx_queue *rxq);
void i40e_free_tx_resources(struct i40e_tx_queue *txq);
void i40e_free_rx_resources(struct i40e_rx_queue *rxq);
void i40e_dev_clear_queues(struct rte_eth_dev *dev);
i40e: free queue memory when closing Add i40e_dev_free_queues() function and call it from close() functions. Signed-off-by: Bernard Iremonger <bernard.iremonger@intel.com> Acked-by: Helin Zhang <helin.zhang@intel.com>
2015-07-03 14:04:00 +00:00
void i40e_dev_free_queues(struct rte_eth_dev *dev);
i40e: queue start and stop Add functions to start/stop specific RX/TX queue. Support fields start_rx_per_q and start_tx_per_q. In the meanwhile, change dev_start/stop functions to call per-queue functions. Signed-off-by: Chen Jing D(Mark) <jing.d.chen@intel.com> Reviewed-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Reviewed-by: Changchun Ouyang <changchun.ouyang@intel.com> Reviewed-by: Huawei Xie <huawei.xie@intel.com> [Thomas: reword comments and merge 2 patches]
2014-08-14 07:35:01 +00:00
void i40e_reset_rx_queue(struct i40e_rx_queue *rxq);
void i40e_reset_tx_queue(struct i40e_tx_queue *txq);
void i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq);
net/i40e: cleanup Tx buffers Add support to the i40e driver for the API rte_eth_tx_done_cleanup to force free consumed buffers on Tx ring. Signed-off-by: Chenxu Di <chenxux.di@intel.com> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
2020-01-13 09:57:05 +00:00
int i40e_tx_done_cleanup(void *txq, uint32_t free_cnt);
i40e: new poll mode driver Signed-off-by: Helin Zhang <helin.zhang@intel.com> Signed-off-by: Jing Chen <jing.d.chen@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com> Acked-by: Jijiang Liu <jijiang.liu@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com> Acked-by: Heqing Zhu <heqing.zhu@intel.com> Tested-by: Waterman Cao <waterman.cao@intel.com>
2014-06-05 05:08:46 +00:00
int i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq);
void i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq);
uint32_t i40e_dev_rx_queue_count(struct rte_eth_dev *dev,
uint16_t rx_queue_id);
int i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
net/i40e: implement descriptor status API Signed-off-by: Olivier Matz <olivier.matz@6wind.com> Acked-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
2017-03-29 08:36:33 +00:00
int i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset);
int i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset);
i40e: new poll mode driver Signed-off-by: Helin Zhang <helin.zhang@intel.com> Signed-off-by: Jing Chen <jing.d.chen@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com> Acked-by: Jijiang Liu <jijiang.liu@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com> Acked-by: Heqing Zhu <heqing.zhu@intel.com> Tested-by: Waterman Cao <waterman.cao@intel.com>
2014-06-05 05:08:46 +00:00
i40e: add vector Rx The vPMD RX function uses the multi-buffer and SSE instructions to accelerate the RX speed, but now the pktype cannot be supported by the vPMD RX, because it will decrease the performance heavily. Signed-off-by: Zhe Tao <zhe.tao@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com>
2015-10-30 14:16:35 +00:00
uint16_t i40e_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
uint16_t nb_pkts);
i40e: add vector scatter Rx To support the multiple segments in one packets when the received pkts exceed one buffer size. Signed-off-by: Zhe Tao <zhe.tao@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com>
2015-10-30 14:16:37 +00:00
uint16_t i40e_recv_scattered_pkts_vec(void *rx_queue,
struct rte_mbuf **rx_pkts,
uint16_t nb_pkts);
i40e: allow vector Rx and Tx usage To support FVL PMD can select which RX and TX function should be used according to the queue config. Signed-off-by: Zhe Tao <zhe.tao@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com>
2015-10-30 14:16:38 +00:00
int i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev);
i40e: add vector Rx The vPMD RX function uses the multi-buffer and SSE instructions to accelerate the RX speed, but now the pktype cannot be supported by the vPMD RX, because it will decrease the performance heavily. Signed-off-by: Zhe Tao <zhe.tao@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com>
2015-10-30 14:16:35 +00:00
int i40e_rxq_vec_setup(struct i40e_rx_queue *rxq);
i40e: add vector Tx The way to increase the performance of the vPMD TX is to use some fast mbuf release method compares to the scalar TX. Signed-off-by: Zhe Tao <zhe.tao@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com>
2015-10-30 14:16:36 +00:00
int i40e_txq_vec_setup(struct i40e_tx_queue *txq);
i40e: add vector Rx The vPMD RX function uses the multi-buffer and SSE instructions to accelerate the RX speed, but now the pktype cannot be supported by the vPMD RX, because it will decrease the performance heavily. Signed-off-by: Zhe Tao <zhe.tao@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com>
2015-10-30 14:16:35 +00:00
void i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq);
net/i40e: remove limit of Tx burst size To add a wrapper function to remove the limit of tx burst size. The patch makes i40e vec function an best effort to transmit the pkts in the consistent behavior like i40e_xmit_pkts_simple and i40e_xmit_pkts do that. Cc: Helin Zhang <helin.zhang@intel.com> Cc: Jingjing Wu <jingjing.wu@intel.com> Signed-off-by: Zhiyong Yang <zhiyong.yang@intel.com> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
2017-03-29 07:16:13 +00:00
uint16_t i40e_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
uint16_t nb_pkts);
i40e: allow vector Rx and Tx usage To support FVL PMD can select which RX and TX function should be used according to the queue config. Signed-off-by: Zhe Tao <zhe.tao@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com>
2015-10-30 14:16:38 +00:00
void i40e_set_rx_function(struct rte_eth_dev *dev);
void i40e_set_tx_function_flag(struct rte_eth_dev *dev,
struct i40e_tx_queue *txq);
void i40e_set_tx_function(struct rte_eth_dev *dev);
net/i40e: enable per-device packet type mapping The mapping from hardware defined packet type to software defined packet type is static for i40e device, the patch let each ethdev to to have their own copy of mapping table, this give the possibility that different ethdev can be set different PTYPE mapping rule which is the requirement to support following hardware's dynamic PTYPE feature. Signed-off-by: Qi Zhang <qi.z.zhang@intel.com> Acked-by: Jianbo Liu <jianbo.liu@linaro.org> Acked-by: Chao Zhu <chaozhu@linux.vnet.ibm.com>
2017-04-12 13:55:32 +00:00
void i40e_set_default_ptype_table(struct rte_eth_dev *dev);
net/i40e: add dynamic mapping of SW flow types to HW pctypes Implement dynamic mapping of software flow types to hardware pctypes. This allows to add new flow types and pctypes for DDP without changing API of the driver. The mapping table is located in private data area for particular network adapter and can be individually modified with set of appropriate functions. Signed-off-by: Kirill Rybalchenko <kirill.rybalchenko@intel.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
2017-10-04 12:52:10 +00:00
void i40e_set_default_pctype_table(struct rte_eth_dev *dev);
net/i40e: add AVX2 Rx function Add a new Rx function using AVX2 instructions for higher performance. For now, this functionality is limited to platforms with Intel Xeon Scalable Processor(SP). The function to be used is selected at runtime, not just at compile-time. Signed-off-by: Bruce Richardson <bruce.richardson@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2018-01-09 14:32:54 +00:00
uint16_t i40e_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
uint16_t nb_pkts);
uint16_t i40e_recv_scattered_pkts_vec_avx2(void *rx_queue,
struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
net/i40e: add AVX2 Tx function Add a new Tx function using AVX2 instructions for higher performance. For now, this functionality is limited to platforms with Intel Xeon Scalable Processor(SP). The function to be used is selected at runtime, not just at compile-time. Signed-off-by: Bruce Richardson <bruce.richardson@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2018-01-09 14:32:53 +00:00
uint16_t i40e_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
uint16_t nb_pkts);
net/i40e: implement power management API Implement support for the power management API by implementing a `get_monitor_addr` function that will return an address of an RX ring's status bit. Signed-off-by: Liang Ma <liang.j.ma@intel.com> Signed-off-by: Anatoly Burakov <anatoly.burakov@intel.com> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Acked-by: Jeff Guo <jia.guo@intel.com>
2021-01-14 14:46:11 +00:00
int i40e_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc);
i40e: add vector Rx The vPMD RX function uses the multi-buffer and SSE instructions to accelerate the RX speed, but now the pktype cannot be supported by the vPMD RX, because it will decrease the performance heavily. Signed-off-by: Zhe Tao <zhe.tao@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com>
2015-10-30 14:16:35 +00:00
net/i40e: add packet type metadata in vector Rx The ptype is decoded from the Rx descriptor and stored in the packet type field in the mbuf using the same function in the non-vector driver. Signed-off-by: Damjan Marion <damarion@cisco.com> Signed-off-by: Jeff Shaw <jeffrey.b.shaw@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com> Acked-by: Jing Chen <jing.d.chen@intel.com>
2016-10-06 06:38:09 +00:00
/* For each value it means, datasheet of hardware can tell more details
*
* @note: fix i40e_dev_supported_ptypes_get() if any change here.
*/
static inline uint32_t
net/i40e: enable per-device packet type mapping The mapping from hardware defined packet type to software defined packet type is static for i40e device, the patch let each ethdev to to have their own copy of mapping table, this give the possibility that different ethdev can be set different PTYPE mapping rule which is the requirement to support following hardware's dynamic PTYPE feature. Signed-off-by: Qi Zhang <qi.z.zhang@intel.com> Acked-by: Jianbo Liu <jianbo.liu@linaro.org> Acked-by: Chao Zhu <chaozhu@linux.vnet.ibm.com>
2017-04-12 13:55:32 +00:00
i40e_get_default_pkt_type(uint8_t ptype)
net/i40e: add packet type metadata in vector Rx The ptype is decoded from the Rx descriptor and stored in the packet type field in the mbuf using the same function in the non-vector driver. Signed-off-by: Damjan Marion <damarion@cisco.com> Signed-off-by: Jeff Shaw <jeffrey.b.shaw@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com> Acked-by: Jing Chen <jing.d.chen@intel.com>
2016-10-06 06:38:09 +00:00
{
static const uint32_t type_table[UINT8_MAX + 1] __rte_cache_aligned = {
/* L2 types */
/* [0] reserved */
[1] = RTE_PTYPE_L2_ETHER,
[2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
/* [3] - [5] reserved */
[6] = RTE_PTYPE_L2_ETHER_LLDP,
/* [7] - [10] reserved */
[11] = RTE_PTYPE_L2_ETHER_ARP,
/* [12] - [21] reserved */
/* Non tunneled IPv4 */
[22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_L4_FRAG,
[23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_L4_NONFRAG,
[24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_L4_UDP,
/* [25] reserved */
[26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_L4_TCP,
[27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_L4_SCTP,
[28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_L4_ICMP,
/* IPv4 --> IPv4 */
[29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_IP |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_FRAG,
[30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_IP |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_NONFRAG,
[31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_IP |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_UDP,
/* [32] reserved */
[33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_IP |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_TCP,
[34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_IP |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_SCTP,
[35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_IP |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_ICMP,
/* IPv4 --> IPv6 */
[36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_IP |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_FRAG,
[37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_IP |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_NONFRAG,
[38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_IP |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_UDP,
/* [39] reserved */
[40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_IP |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_TCP,
[41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_IP |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_SCTP,
[42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_IP |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_ICMP,
/* IPv4 --> GRE/Teredo/VXLAN */
[43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT,
/* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
[44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_FRAG,
[45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_NONFRAG,
[46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_UDP,
/* [47] reserved */
[48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_TCP,
[49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_SCTP,
[50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_ICMP,
/* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
[51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_FRAG,
[52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_NONFRAG,
[53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_UDP,
/* [54] reserved */
[55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_TCP,
[56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_SCTP,
[57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_ICMP,
/* IPv4 --> GRE/Teredo/VXLAN --> MAC */
[58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
/* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
[59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_FRAG,
[60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_NONFRAG,
[61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_UDP,
/* [62] reserved */
[63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_TCP,
[64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_SCTP,
[65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_ICMP,
/* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
[66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_FRAG,
[67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_NONFRAG,
[68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_UDP,
/* [69] reserved */
[70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_TCP,
[71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_SCTP,
[72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_ICMP,
/* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
[73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN,
/* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
[74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_FRAG,
[75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_NONFRAG,
[76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_UDP,
/* [77] reserved */
[78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_TCP,
[79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_SCTP,
[80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_ICMP,
/* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
[81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_FRAG,
[82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_NONFRAG,
[83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_UDP,
/* [84] reserved */
[85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_TCP,
[86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_SCTP,
[87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_ICMP,
/* Non tunneled IPv6 */
[88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_L4_FRAG,
[89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_L4_NONFRAG,
[90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_L4_UDP,
/* [91] reserved */
[92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_L4_TCP,
[93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_L4_SCTP,
[94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_L4_ICMP,
/* IPv6 --> IPv4 */
[95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_IP |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_FRAG,
[96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_IP |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_NONFRAG,
[97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_IP |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_UDP,
/* [98] reserved */
[99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_IP |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_TCP,
[100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_IP |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_SCTP,
[101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_IP |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_ICMP,
/* IPv6 --> IPv6 */
[102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_IP |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_FRAG,
[103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_IP |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_NONFRAG,
[104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_IP |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_UDP,
/* [105] reserved */
[106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_IP |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_TCP,
[107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_IP |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_SCTP,
[108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_IP |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_ICMP,
/* IPv6 --> GRE/Teredo/VXLAN */
[109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT,
/* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
[110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_FRAG,
[111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_NONFRAG,
[112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_UDP,
/* [113] reserved */
[114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_TCP,
[115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_SCTP,
[116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_ICMP,
/* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
[117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_FRAG,
[118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_NONFRAG,
[119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_UDP,
/* [120] reserved */
[121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_TCP,
[122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_SCTP,
[123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_ICMP,
/* IPv6 --> GRE/Teredo/VXLAN --> MAC */
[124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
/* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
[125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_FRAG,
[126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_NONFRAG,
[127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_UDP,
/* [128] reserved */
[129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_TCP,
[130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_SCTP,
[131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_ICMP,
/* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
[132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_FRAG,
[133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_NONFRAG,
[134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_UDP,
/* [135] reserved */
[136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_TCP,
[137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_SCTP,
[138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_ICMP,
/* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
[139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN,
/* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
[140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_FRAG,
[141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_NONFRAG,
[142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_UDP,
/* [143] reserved */
[144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_TCP,
[145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_SCTP,
[146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_ICMP,
/* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
[147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_FRAG,
[148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_NONFRAG,
[149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_UDP,
/* [150] reserved */
[151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_TCP,
[152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_SCTP,
[153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_TUNNEL_GRENAT |
RTE_PTYPE_INNER_L2_ETHER_VLAN |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_INNER_L4_ICMP,
/* L2 NSH packet type */
[154] = RTE_PTYPE_L2_ETHER_NSH,
[155] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_L4_FRAG,
[156] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_L4_NONFRAG,
[157] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_L4_UDP,
[158] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_L4_TCP,
[159] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_L4_SCTP,
[160] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
RTE_PTYPE_L4_ICMP,
[161] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_L4_FRAG,
[162] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_L4_NONFRAG,
[163] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_L4_UDP,
[164] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_L4_TCP,
[165] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_L4_SCTP,
[166] = RTE_PTYPE_L2_ETHER_NSH | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
RTE_PTYPE_L4_ICMP,
/* All others reserved */
};
return type_table[ptype];
}
i40e: new poll mode driver Signed-off-by: Helin Zhang <helin.zhang@intel.com> Signed-off-by: Jing Chen <jing.d.chen@intel.com> Acked-by: Cunming Liang <cunming.liang@intel.com> Acked-by: Jijiang Liu <jijiang.liu@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com> Acked-by: Heqing Zhu <heqing.zhu@intel.com> Tested-by: Waterman Cao <waterman.cao@intel.com>
2014-06-05 05:08:46 +00:00
#endif /* _I40E_RXTX_H_ */
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