284 Commits

Author SHA1 Message Date
Adam Dybkowski
7b08003b5d common/qat: support GEN2 device 200xx
This adds pci detection and documentation for Intel GEN2
QuickAssist device 200xx (PF Did 0x18ee, VF Did 0x18ef).

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2020-07-28 22:09:22 +02:00
Adam Dybkowski
1c22df86bb doc: update QAT driver version for D15xx
This patch updates the minimum driver version that supports
Intel QuickAssist device D15xx.

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2020-07-18 23:49:09 +02:00
David Coyle
6b048cdfa2 crypto/qat: check multi-segment buffers for DOCSIS
Multi-segment mbufs are not supported for DOCSIS security protocol.
This patch adds an explicit check for this and returns an op error if
this case is found. This limitation is also added to the QAT cryptodev
documentation.

Fixes: 6f0ef237404b ("crypto/qat: support DOCSIS protocol")

Signed-off-by: David Coyle <david.coyle@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2020-07-18 23:27:31 +02:00
Vamsi Attunuru
fab634eb87 crypto/octeontx2: support security session data path
This patch adds lookaside IPsec enqueue and dequeue routines.

Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-07-18 23:09:03 +02:00
Tejasree Kondoj
b9765e96c2 crypto/octeontx2: register security operations
This patch registers security operations with cryptodev.

Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-07-18 23:09:02 +02:00
Adam Dybkowski
cb440babbd compress/qat: revert change in GEN3 marketing name
The patch reverts the commit that updated Intel QuickAssist GEN3
marketing name. The change was not backported and has to be withdrawn.

This reverts commit 9cd9d3e702fba4700539c1a2eddac13dd14ecf70

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2020-07-18 23:09:02 +02:00
Arek Kusztal
faa57df0b4 crypto/qat: support ChaCha20-Poly1305
This patchset adds ChaCha20-Poly1305 implementation to Intel
QuickAssist Technology pmd.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
2020-07-08 18:16:40 +02:00
Tejasree Kondoj
cb7842f23e crypto/octeontx2: support ChaCha20-Poly1305
Add ChaCha20-Poly1305 AEAD algorithm support in crypto_octeontx2 PMD

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
2020-07-08 18:16:17 +02:00
Ankur Dwivedi
cec2f173a9 crypto/octeontx2: revert non-byte aligned data feature
This reverts commit 51f3e107aca23a1cbc1a5ad9fdce7921340307b5.

For SNOW and ZUC algos the offset value for enryption and decryption
is converted to bytes. Hence RTE_CRYPTODEV_FF_NON_BYTE_ALIGNED_DATA
feature is not supported by the octeontx2 crypto pmd.

Fixes: 51f3e107aca2 ("crypto/octeontx2: enable non-byte aligned data")
Cc: stable@dpdk.org

Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
2020-07-08 18:16:16 +02:00
Ankur Dwivedi
371dbd5751 crypto/octeontx: revert non-byte aligned data feature
This reverts commit 32b8f26adf8b26a55230408ff6adffd4b2327e52.

For SNOW and ZUC algos the offset value for enryption and decryption
is converted to bytes. Hence RTE_CRYPTODEV_FF_NON_BYTE_ALIGNED_DATA
feature is not supported by the octeontx crypto pmd.

Fixes: 32b8f26adf8b ("crypto/octeontx: enable non-byte aligned data")
Cc: stable@dpdk.org

Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
2020-07-08 18:16:16 +02:00
David Coyle
6f0ef23740 crypto/qat: support DOCSIS protocol
Add support to the QAT SYM PMD for the DOCSIS protocol, through the
rte_security API. This, therefore, includes adding support for the
rte_security API to this PMD.

Signed-off-by: David Coyle <david.coyle@intel.com>
Signed-off-by: Mairtin o Loingsigh <mairtin.oloingsigh@intel.com>
2020-07-08 18:16:13 +02:00
David Coyle
fda5216fba crypto/aesni_mb: support DOCSIS protocol
Add support to the AESNI-MB PMD for the DOCSIS protocol, through the
rte_security API. This, therefore, includes adding support for the
rte_security API to this PMD.

Signed-off-by: David Coyle <david.coyle@intel.com>
Signed-off-by: Mairtin o Loingsigh <mairtin.oloingsigh@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2020-07-08 00:15:35 +02:00
Pablo de Lara
cd346367f8 drivers/crypto: add missing OOP feature flag
ZUC, SNOW3G and KASUMI PMDs support Out-of-place operations,
but their feature flags did not reflect this.

Fixes: 2717246ecd7d ("cryptodev: replace mbuf scatter gather flag")
Cc: stable@dpdk.org

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2020-07-08 00:15:35 +02:00
Thomas Monjalon
582e9d7765 doc: remove some build instructions where unneeded
The build should be described only in few places,
in order to maintain up-to-date, accurate and detailed instructions.
This change is removing some of the unneeded repetitions.

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Acked-by: Jay Zhou <jianjay.zhou@huawei.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
Acked-by: David Marchand <david.marchand@redhat.com>
2020-06-29 16:33:39 +02:00
Pablo de Lara
dede694cd5 doc: add NASM installation steps
The intel-ipsec-mb library requires NASM as a dependency.
Steps on how to get and install NASM are added on the documentation
of the crypto PMDs which requires the library.

Bugzilla ID: 417
Cc: stable@dpdk.org

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Kevin Traynor <ktraynor@redhat.com>
2020-05-24 18:55:40 +02:00
Jay Zhou
b7aa3b5b88 crypto/virtio: enable OOP feature flag
Since it will check the feature mask before running out-of-place
test cases and the virtio-crypto device supports OOP_LB_IN_LB_OUT mode.

Signed-off-by: Jay Zhou <jianjay.zhou@huawei.com>
Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-05-17 16:10:44 +02:00
Ankur Dwivedi
32b8f26adf crypto/octeontx: enable non-byte aligned data
The OCTEON TX crypto PMD supports non-byte aligned data as
input for SNOW and ZUC algos. Adding the same to the feature list.

Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
2020-05-17 16:10:44 +02:00
Ankur Dwivedi
51f3e107ac crypto/octeontx2: enable non-byte aligned data
The OCTEON TX2 crypto PMD supports non-byte aligned data as
input for SNOW and ZUC algos. Adding the same to the feature list.

Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
2020-05-17 16:10:44 +02:00
Arek Kusztal
b922dbd38c cryptodev: add ChaCha20-Poly1305 AEAD algorithm
This patch adds Chacha20-Poly1305 AEAD algorithm to Cryptodev.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-05-11 13:17:43 +02:00
Pablo de Lara
43608222a7 doc: support IPsec Multi-buffer lib v0.54
Updated SNOW3G and KASUMI PMD documentation guides
with information about the latest Intel IPSec Multi-buffer
library supported.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2020-05-11 13:17:43 +02:00
Pablo de Lara
0b133c36ad crypto/zuc: support IPsec Multi-buffer lib v0.54
The latest version of the Intel IPSec Multi-buffer library
adds an API to authenticate multiple buffers in parallel.
The PMD is modified to use this API, improving
performance of the ZUC-EIA3 algorithm.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2020-05-11 13:17:43 +02:00
Akhil Goyal
e11bdd3774 cryptodev: add feature flag for non-byte aligned data
Some wireless algos like SNOW, ZUC may support input
data in bits which are not byte aligned. However, not
all PMDs can support this requirement. Hence added a
new feature flag RTE_CRYPTODEV_FF_NON_BYTE_ALIGNED_DATA
to identify which all PMDs can support non-byte aligned
data.

Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
2020-05-11 13:17:43 +02:00
Pablo de Lara
fed5ee5f18 doc: support IPsec Multi-buffer lib v0.54
Updated AESNI MB and AESNI GCM PMD documentation guides
with information about the latest Intel IPSec Multi-buffer
library supported.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2020-04-19 23:00:23 +02:00
Adam Dybkowski
6e21c1a532 crypto/qat: support plain SHA1..SHA512 hashes
This patch adds support for plain SHA-1, SHA-224, SHA-256,
SHA-384 and SHA-512 hashes to QAT PMD.

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2020-04-19 22:45:11 +02:00
Pablo de Lara
b3aaf24de5 cryptodev: add session-less feature flag
Add feature flag for symmetric sessionless support,
so it can be checked by applications.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Tested-by: Ruifeng Wang <ruifeng.wang@arm.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-19 22:45:11 +02:00
Adam Dybkowski
c13cecf60f compress/qat: support IM buffer too small operation
This patch implements a special way of buffer handling when internal
QAT IM buffer is too small for Huffman dynamic compression operation.
Instead of falling back to fixed compression, the operation is now
split into multiple smaller dynamic compression requests (possible to
execute on QAT) and their results are then combined and copied into
the output buffer. This is not possible if any checksum calculation
was requested - in such case the code falls back to fixed compression
as before.

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2020-04-19 17:15:14 +02:00
Konstantin Ananyev
a2c6d3f34f crypto/aesni_mb: support CPU crypto
Add support for CPU crypto mode by introducing required handler.

Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
2020-04-19 17:15:14 +02:00
Nagadheeraj Rottela
2a41db7589 crypto/nitrox: support 3DES-CBC
This patch adds 3DES CBC mode cipher algorithm.

Signed-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>
2020-04-05 18:40:34 +02:00
Adam Dybkowski
a1598e90f3 crypto/qat: handle mixed hash-cipher on GEN2
This patch adds handling of mixed hash-cipher algorithms
available on GEN2 QAT in particular firmware versions.
Also the documentation is updated to show the mixed crypto
algorithms are supported on QAT GEN2.

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2020-04-05 18:30:00 +02:00
Adam Dybkowski
9cd9d3e702 common/qat: fix GEN3 marketing name
This patch fixes the marketing name of the QAT GEN3 to P5xxx.
Updates this name mentioned in the compression PMD as well as
in the documentation.

Fixes: aa983f03ad2e ("crypto/qat: handle Single Pass Crypto Requests on GEN3")
Fixes: a124830a6f00 ("compress/qat: enable dynamic huffman encoding")
Fixes: 1f5e4053f9b4 ("common/qat: support GEN3 devices")
Cc: stable@dpdk.org

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2020-04-05 18:26:04 +02:00
Pablo de Lara
f69ed10442 doc: add build requirement in some crypto PMD guides
The following crypto PMDs use the Intel Multi-buffer library:
- AESNI MB PMD
- AESNI GCM PMD
- ZUC PMD
- KASUMI PMD
- SNOW3G PMD

When this library is built with gcc < 5.0, it might throw
some compilation issues. A workaround has been added in the
repo of this library, so a note on this has been added
to the documentation of these PMDs.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: John McNamara <john.mcnamara@intel.com>
2020-02-21 23:04:15 +01:00
Marcin Smoczynski
d6946fe9d4 crypto/aesni_gcm: support CPU crypto
Add support for CPU crypto mode by introducing required handler.
Authenticated encryption and decryption are supported with tag
generation/verification.

CPU crypto support include both AES-GCM and GMAC algorithms.

Signed-off-by: Marcin Smoczynski <marcinx.smoczynski@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
Tested-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
2020-02-05 15:29:14 +01:00
Marcin Smoczynski
7adf992fb9 cryptodev: introduce CPU crypto API
Add new API allowing to process crypto operations in a synchronous
manner. Operations are performed on a set of SG arrays.

Cryptodevs which allows CPU crypto operation mode have to
use RTE_CRYPTODEV_FF_SYM_CPU_CRYPTO capability.

Add a helper method to easily convert mbufs to a SGL form.

Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Signed-off-by: Marcin Smoczynski <marcinx.smoczynski@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-02-05 15:29:14 +01:00
Ruifeng Wang
bde43e8a77 crypto/armv8: link to library hosted by Arm
Armv8 crypto PMD linked to armv8_crypto library created by Marvell.
Maintenance of armv8_crypto library will be discontinued.
Change Armv8 PMD to link to AArch64 crypto library hosted by Arm.

Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: Ola Liljedahl <ola.liljedahl@arm.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-02-05 15:20:51 +01:00
Pablo de Lara
7c87e2d7b3 crypto/snow3g: use IPsec library
Link against Intel IPsec Multi-buffer library, which
added support for SNOW3G-UEA2 and SNOW3G-UIA2 from version v0.53,
moving from libSSO SNOW3G library.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-02-05 15:17:36 +01:00
Pablo de Lara
bf6eb2c22f crypto/kasumi: use IPsec library
Link against Intel IPsec Multi-buffer library, which
added support for KASUMI-F8 and KASUMI-F9 from version v0.53,
moving from libSSO KASUMI library.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-02-05 15:16:57 +01:00
Pablo de Lara
61f7c988e3 crypto/zuc: use IPsec library
Link against Intel IPsec Multi-buffer library, which
added support for ZUC-EEA3 and ZUC-EIA3 from version v0.53,
moving from libSSO ZUC library.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-02-05 15:15:32 +01:00
Thomas Monjalon
f5862ae99e cryptodev: revert Chacha20-Poly1305 AEAD algorithm
API makes think that rte_cryptodev_info_get() cannot return
a value >= 3 (RTE_CRYPTO_AEAD_LIST_END in 19.11).
20.02-rc1 was returning 3 (RTE_CRYPTO_AEAD_CHACHA20_POLY1305).
So the ABI compatibility contract was broken.

It could be solved with some function versioning,
but because a lack of time, the feature is reverted for now.

This reverts following commits:
- 6c9f3b347e21 ("cryptodev: add Chacha20-Poly1305 AEAD algorithm")
- 2c512e64d600 ("crypto/qat: support Chacha Poly")
- d55e01f579e1 ("test/crypto: add Chacha Poly cases")

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
2020-02-05 15:14:46 +01:00
Arek Kusztal
2c512e64d6 crypto/qat: support Chacha Poly
This patchset adds Chacha20-Poly1305 implementation to Intel
QuickAssist Technology pmd.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2020-01-16 17:10:36 +01:00
Adam Dybkowski
bcd7e3e8e6 crypto/qat: handle mixed hash-cipher requests on GEN3
This patch implements handling mixed encrypted digest hash-cipher
requests (e.g. SNOW3G + ZUC or ZUC + AES CTR) possible when running
on GEN3 QAT. Such algorithm combinations are not supported on
GEN1/GEN2 hardware.

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2020-01-15 16:45:04 +01:00
Arek Kusztal
47c3f7a41a crypto/qat: add minimum enqueue threshold
This patch adds minimum enqueue threshold to Intel
QuickAssist Technology PMD.
It is an optimisation, configured by a command line option,
which can be used to reduce MMIO write occurrences.

Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
2020-01-15 16:45:04 +01:00
Fiona Trahe
026f21c0b9 common/qat: support dual threads for enqueue/dequeue
Remove the limitation whereby enqueue and dequeue must be
done in same thread.
The inflight calculation is reworked to be thread-safe for 2
threads - note this is not general multi-thread support, i.e
all enqueues to a qp must still be done in one thread and
all dequeues must be done in one thread, but enqueues and
dequeues may be in separate threads.
Documentation updated.

Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
2020-01-15 15:20:58 +01:00
Sunila Sahu
40726a9ad5 crypto/octeontx2: support ECPM
Add support asymmetric operation EC Point MUltiplication,
in crypto_octeontx2 PMD.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Balakrishna Bhamidipati <bbhamidipati@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
2020-01-15 15:01:55 +01:00
Sunila Sahu
99faef8325 crypto/octeontx: support ECPM
Add support for asymmetric operation EC Point Multiplication,
in crypto_octeontx PMD.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Balakrishna Bhamidipati <bbhamidipati@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
2020-01-15 15:01:55 +01:00
Balakrishna Bhamidipati
e98dc331e9 cryptodev: support ECPM
Asymmetric crypto library is extended to add ECPM (Elliptic Curve Point
Multiplication). The required xform type and op parameters are
introduced.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Balakrishna Bhamidipati <bbhamidipati@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-01-15 15:01:55 +01:00
Sunila Sahu
2e12bd06fe crypto/octeontx2: support ECDSA
Adding support for ECDSA asymmetric crypto
operations in crypto_octeontx2 PMD.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Balakrishna Bhamidipati <bbhamidipati@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
2020-01-15 15:01:55 +01:00
Sunila Sahu
aa2cbd32e9 crypto/octeontx: support ECDSA
Adding support for ECDSA asymmetric crypto operations
in crypto_octeontx PMD.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Ayuj Verma <ayverma@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
2020-01-15 15:01:55 +01:00
Ayuj Verma
7bb4ea3246 cryptodev: support ECDSA
Asymmetric crypto library is extended to add ECDSA. Elliptic curve
xform and ECDSA op params are introduced.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Ayuj Verma <ayverma@marvell.com>
Signed-off-by: Sunila Sahu <ssahu@marvell.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-01-15 15:01:56 +01:00
Arek Kusztal
6c9f3b347e cryptodev: add Chacha20-Poly1305 AEAD algorithm
This patch adds Chacha20-Poly1305 AEAD algorithm to Cryptodev.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-01-15 13:34:02 +01:00
Amaranath Somalapuram
1151b4ae2d doc: fix l2fwd-crypto usage in CCP guide
Update the CCP doc for fixing description of some parameter,
Changing AES_CBC to aes-cbc, SHA1_HMAC to sha1-hmac.

Fixes: 4433ced9aa ("doc: add AMD CCP guide")
Cc: stable@dpdk.org

Signed-off-by: Amaranath Somalapuram <asomalap@amd.com>
2019-11-25 11:01:36 +01:00