Commit Graph

21556 Commits

Author SHA1 Message Date
Thomas Monjalon
5f1a4a8a12 test: remove meson dependency on /proc file
Meson is detecting the path /proc/sys/vm/nr_hugepages in the call to cat
in app/test/meson.build and then adding it as a build dependency.
This causes build loop if the timestamp of this file keeps changing.

It is fixed by hiding hugepage check in a shell script.

Fixes: 77784ef0fb ("test: allow no-huge mode for fast-tests")

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Tested-by: Lukasz Wojciechowski <l.wojciechow@partner.samsung.com>
Reviewed-by: Lukasz Wojciechowski <l.wojciechow@partner.samsung.com>
Acked-by: Aaron Conole <aconole@redhat.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Acked-by: Bruce Richardson <bruce.richardson@intel.com>
2020-04-15 15:45:24 +02:00
Thomas Monjalon
10d34aa3de doc: fix sphinx compatibility
The function add_stylesheet() is deprecated since sphinx 1.8.
It will be removed in sphinx 4.0.
It is replaced by add_css_file().

Cc: stable@dpdk.org

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
2020-04-15 15:21:06 +02:00
Hemant Agrawal
f34cb24522 maintainers: update for rawdev
Replace rawdev maintainer. Shreyansh is no longer with NXP.

Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Acked-by: Nipun Gupta <nipun.gupta@nxp.com>
2020-04-15 15:03:37 +02:00
Liron Himi
86fdced4d1 maintainers: update for Marvell ARMADA
update MRVL PMDs, Tomasz is no longer with semihalf

Signed-off-by: Liron Himi <lironh@marvell.com>
2020-04-15 14:55:56 +02:00
Pavan Nikhilesh
f97b817ce4 event/octeontx2: use C11 atomics for statistics
Use c11 atomics with RELAXED ordering instead of rte_atomic ops which
enforce unnessary barriers on arm64.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Phil Yang <phil.yang@arm.com>
2020-04-04 18:38:43 +02:00
Pavan Nikhilesh
092454d999 examples/l2fwd-event: add option to configure port pairs
Current l2fwd-event application statically configures adjacent ports as
destination ports for forwarding the traffic.

Add a config option to pass the forwarding port pair mapping which allows
the user to configure forwarding port mapping.

If no config argument is specified, destination port map is not
changed and traffic gets forwarded with existing mapping.

To align port/queue configuration of each lcore with destination port
map, port/queue configuration of each lcore gets modified when config
option is specified.

Ex: ./l2fwd-event -c 0xff -- -p 0x3f -q 2 --config="(0,3)(1,4)(2,5)"

With above config option, traffic received from portid = 0 gets forwarded
to port = 3 and vice versa, similarly traffic gets forwarded on other port
pairs (1,4) and (2,5).

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Andrzej Ostruszka <aostruszka@marvell.com>
2020-04-04 18:09:51 +02:00
Pavan Nikhilesh
9fdc9986cf app/eventdev: validate producer type
Validate the producer type used for pipeline and order test suites.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
2020-04-04 17:11:23 +02:00
Mattias Rönnblom
b97d3a9cbc event/dsw: add port busy cycles xstats
DSW keeps an internal port load estimate, used by the load balancing
mechanism. As a side effect, it keeps track of the total number of
busy cycles since startup. This metric is indirectly exposed in the
form of DSW xstats' "port_<n>_event_proc_latency", which is the total
number of busy cycles divided by the total number of events processed
on a particular port.

An external application can take (event_latency * dequeued) to go back
to busy_cycles. One reason for doing this is to measure the port's
load during a longer time period, without resorting to sampling
"port_<n>_load". However, as the number dequeued events grows, a
rounding error in event_latency renders the application-calculated
busy_cycles inaccurate.

Thus, it makes sense to directly expose the number of busy cycles as a
DSW xstats, even though it might seem redundant.

Signed-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
2020-04-04 16:32:19 +02:00
Mattias Rönnblom
cea7bc6713 event/dsw: remove unnecessary read barrier
Remove unnecessary read barrier (and misleading comment) on control
message dequeue.

Fixes: f6257b22e7 ("event/dsw: add load balancing")
Cc: stable@dpdk.org

Suggested-by: Ola Liljedahl <ola.liljedahl@arm.com>
Signed-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
2020-04-04 16:32:14 +02:00
Mattias Rönnblom
65388325f1 event/dsw: remove redundant control ring poll
On dequeue, polling the control ring once is enough.

Fixes: f6257b22e7 ("event/dsw: add load balancing")
Cc: stable@dpdk.org

Suggested-by: Ola Liljedahl <ola.liljedahl@arm.com>
Signed-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
2020-04-04 16:32:02 +02:00
Mattias Rönnblom
570ac17b8c event/dsw: avoid migration waves in large systems
DSW limits the rate of migrations on a per-port basis. Hence, as the
number of cores grows, so does the total migration capacity.

In high core-count systems, this allows for a situation where flows
are migrated to a lightly loaded port which recently already received
a number of new flows (from other ports). The processing load
generated by these new flows may not yet be reflected in the lightly
loaded port's load estimate. The result is that the previously lightly
loaded port is now overloaded.

This patch adds a rough estimate of the size of the inbound migrations
to a particular port, which can be factored into the migration logic,
avoiding the above problem.

Signed-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
2020-04-04 16:32:02 +02:00
Mattias Rönnblom
1f2b99e8d9 event/dsw: improve migration mechanism
Allowing moving multiple flows in one migration transaction, to
rebalance load more quickly.

Introduce a threshold to avoid migrating flows between ports with very
similar load.

Simplify logic for selecting which flow to migrate. The aim is now to
move flows in such a way that the receiving port is as lightly-loaded
as possible (after receiving the flow), while still migrating enough
flows from the source port to reduce its load. This is essentially how
legacy strategy work as well, but the code is more readable.

Signed-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
2020-04-04 16:32:02 +02:00
Mattias Rönnblom
c4cf44b677 event/dsw: extend xstats
To allow visualization of migrations, track the number flow
immigrations in "port_<N>_immigrations". The "port_<N>_migrations"
retains legacy semantics, but is renamed "port_<N>_emigrations".

Expose the number of events currently undergoing processing
(i.e. pending releases) at a particular port.

Signed-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
2020-04-04 16:25:56 +02:00
Mattias Rönnblom
81db381019 event/dsw: reduce max flows to speed up load balancing
Reduce the maximum number of DSW flows from 32k to 8k, to be able
rebalance load faster.

Signed-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
2020-04-04 15:18:01 +02:00
Mattias Rönnblom
3db0a0984f event/dsw: reduce latency in low-load situations
In DSW, in case a port can't produce any events for the application to
consume, the port is considered idle.

To slightly reduce wall-time latency, flush the port's output buffer
in case of such an empty dequeue.

Signed-off-by: Mattias Rönnblom <mattias.ronnblom@ericsson.com>
2020-04-04 15:10:17 +02:00
Pavan Nikhilesh
aeb2494688 event/octeontx2: remove WFE from dual-slot dequeue
Each workslot is always bound to a specific lcore there is no multi-core
contention to cause cache trashing as a result it is safe to remove the
WFE. Also, in dual workslot dequeue work will mostlikely be available on
the pair workslot making WFE impractical.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
2020-04-04 13:56:52 +02:00
Pavan Nikhilesh
acec04c4b2 build: disable experimental API check internally
Remove setting ALLOW_EXPERIMENTAL_API individually for each Makefile and
meson.build. Instead, enable ALLOW_EXPERIMENTAL_API flag across app, lib
and drivers.
This changes reduces the clutter across the project while still
maintaining the functionality of ALLOW_EXPERIMENTAL_API i.e. warning
external applications about experimental API usage.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com>
Signed-off-by: David Marchand <david.marchand@redhat.com>
2020-04-14 16:22:34 +02:00
Nagadheeraj Rottela
2a41db7589 crypto/nitrox: support 3DES-CBC
This patch adds 3DES CBC mode cipher algorithm.

Signed-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>
2020-04-05 18:40:34 +02:00
Mariusz Drost
053e1f3c13 examples/ipsec-secgw: enable CPU crypto fallback
Added cpu-crypto fallback option parsing as well as tests for it

Signed-off-by: Mariusz Drost <mariuszx.drost@intel.com>
Tested-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
2020-04-05 18:38:51 +02:00
Nagadheeraj Rottela
9614b472a3 crypto/nitrox: fix oversized device name
In nitrox_sym_pmd_create() the name array will overflow if the pci
device name is greater than 57 bytes. To fix this issue subtract pci
device name length from array length while appending substring to the
name.

Coverity issue: 349926
Fixes: 9fdef0cc23 ("crypto/nitrox: create symmetric cryptodev")
Cc: stable@dpdk.org

Signed-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-05 18:36:17 +02:00
Nagadheeraj Rottela
76522b25b1 crypto/nitrox: fix CSR register address generation
If the NPS_PKT ring/port is greater than 8191 the NPS_PKT*() macros will
evaluate to incorrect values due to unintended sign extension from int
to unsigned long. To fix this, add UL suffix to the constants in these
macros. The same problem is with AQMQ_QSZX() macro also.

Coverity issue: 349899, 349905, 349911, 349921, 349923
Fixes: 32e4930d5a ("crypto/nitrox: add hardware queue management")
Fixes: 0a8fc2423b ("crypto/nitrox: introduce Nitrox driver")
Cc: stable@dpdk.org

Signed-off-by: Nagadheeraj Rottela <rnagadheeraj@marvell.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-05 18:35:34 +02:00
Adam Dybkowski
a1598e90f3 crypto/qat: handle mixed hash-cipher on GEN2
This patch adds handling of mixed hash-cipher algorithms
available on GEN2 QAT in particular firmware versions.
Also the documentation is updated to show the mixed crypto
algorithms are supported on QAT GEN2.

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2020-04-05 18:30:00 +02:00
Adam Dybkowski
7444111408 common/qat: get firmware version
This patch adds the function for retrieving QAT firmware
version, required to check the internal capabilities that
depend on the FW version.

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2020-04-05 18:27:42 +02:00
Nicolas Chautru
d793a6f401 app/bbdev: update test vectors
Modification to vectors parameters used for unit test
for coverage and performance test of bbdev drivers
across all devices.
Updating and reducing list for focused coverage on relevant
code blocks for 4G and 5G. Less focus on 4G TB mode as there is
some question how to best support this with mbuf limitations and
if effect are not used.
Removing scenarios with negative LLR assumptions which are not
used with any PMDs and historical only.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-05 18:26:04 +02:00
Nicolas Chautru
6e024c4b91 app/bbdev: support offload test for LDPC
Adding support for the offload latency tests when
using the LDPC encoder and decoder operations.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-05 18:26:04 +02:00
Nicolas Chautru
f162c47533 app/bbdev: support LDPC interrupt test
Adding missing implementation for the interrupt tests
for LDPC encoder and decoders.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-05 18:26:04 +02:00
Nicolas Chautru
f41c6e4d39 app/bbdev: add performance tests
Includes support for BLER (Block Error Rate) wireless
performance test with new arguments for SNR and number
of iterations for 5G. This generates LLRs for a given
SNR level then measures the ratio of code blocks being
successfully decoded or not.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-05 18:26:04 +02:00
Nicolas Chautru
335c11fd27 app/bbdev: support HARQ validation
Adding functionality to validate HARQ for different
devices implementation.
Adding capacity to fetch HARQ data when required as
part of this validation.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-05 18:26:04 +02:00
Nicolas Chautru
9f17582c7c app/bbdev: rename FPGA LTE macros to be more explicit
Self-contained and cosmetic renaming of macro
so that to be more explicit for future extension.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-05 18:26:04 +02:00
Nicolas Chautru
31a7853d1e baseband/turbo_sw: support large size code block
This is to support cases when the input data for
decoding a code block is larger than 64kB and would
not fit as a contiguous block of data into one
mbuf. In that case the length from the operation
supersedes the mbuf default structure.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-05 18:26:04 +02:00
Nicolas Chautru
e9381a822a baseband/turbo_sw: fix exposed LLR decimals assumption
The actual LLR representation was incorrectly assumed to be 2
instead of 4. This would impact wireless performance but is not
critical to be back ported on LTS branches.

Fixes: c769c71175 ("baseband/turbo_sw: extend for 5G")
Cc: stable@dpdk.org

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-05 18:26:04 +02:00
Nicolas Chautru
3d1456895a bbdev: expose device HARQ buffer size at device level
This exposes the HARQ buffer size at the device driver level
instead of using the capability of a specific operation.

This is currently not yet used by a device until
future commit.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-05 18:26:04 +02:00
Nicolas Chautru
aa094a3508 bbdev: add capability for filler bits inclusion in HARQ
Adding capability flag for device variants when HARQ buffer
may or may not include the filler bits.
Minor cosmetic changes in same file.

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-05 18:26:04 +02:00
Arek Kusztal
305de56097 test/crypto: add AES-GCM J0 case
This patch adds crypto J0 test case to AES-GCM

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2020-04-05 18:26:04 +02:00
Arek Kusztal
2165e2e9ea crypto/qat: support AES-GCM J0
This patch adds J0 capability to Intel QuickAssist Technology driver

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2020-04-05 18:26:04 +02:00
Ruifeng Wang
40a49a89d7 test/ipsec: fix crash in session destroy
Segfault was observed when running ipsec unit test:

 + TestCase [10] : test_ipsec_replay_inb_repeat_null_null_wrapper
                   succeeded
 + TestCase [11] : test_ipsec_replay_inb_inside_burst_null_null_wrapper
                   succeeded
 + TestCase [12] : test_ipsec_crypto_inb_burst_2sa_null_null_wrapper
                   succeeded
 + TestCase [13] : test_ipsec_crypto_inb_burst_2sa_4grp_null_null_wrapper
                   succeeded
Segmentation fault

Data corruption happens due to incorrect destroy of session. Security
session needs process different from crypto session.

Destroy corresponding sessions according to different security actions.

Fixes: 05fe65eb66 ("test/ipsec: introduce functional test")
Cc: stable@dpdk.org

Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Reviewed-by: Phil Yang <phil.yang@arm.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Tested-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
2020-04-05 18:26:04 +02:00
Fiona Trahe
dda27cb3c1 common/qat: optimise calculation of cookie index
Avoid costly division, use shift instead.

Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
2020-04-05 18:26:04 +02:00
Fiona Trahe
603ad3ae91 crypto/qat: optimise check for chained mbufs
To detect if sgl, use nb_segs > 1, instead of checking for next pointer,
as nb_segs is in first cache-line while next is in second cache-line.

Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
2020-04-05 18:26:04 +02:00
Fiona Trahe
5390f304b7 crypto/qat: improve out-of-place conditional check
Improve case where application set m_dst to same as m_src
so really an in-place operation, though would have been treated
as out-of-place. No functional change but this path can now benefit
from DMA alignment.

Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
2020-04-05 18:26:04 +02:00
Artur Trybula
5a94e64c37 compressdev: remove unused function pointer prototype
This commit removes unused prototype of the function pointer
compressdev_queue_pair_count_t.

Signed-off-by: Artur Trybula <arturx.trybula@intel.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
2020-04-05 18:26:04 +02:00
Artur Trybula
728aaeffb4 cryptodev: remove unused operation for queue count
This commit removes unused function pointer (queue_pair_count)
from struct rte_cryptodev_ops. Related functions removed as well.

Signed-off-by: Artur Trybula <arturx.trybula@intel.com>
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
2020-04-05 18:26:04 +02:00
Adam Dybkowski
9cd9d3e702 common/qat: fix GEN3 marketing name
This patch fixes the marketing name of the QAT GEN3 to P5xxx.
Updates this name mentioned in the compression PMD as well as
in the documentation.

Fixes: aa983f03ad ("crypto/qat: handle Single Pass Crypto Requests on GEN3")
Fixes: a124830a6f ("compress/qat: enable dynamic huffman encoding")
Fixes: 1f5e4053f9 ("common/qat: support GEN3 devices")
Cc: stable@dpdk.org

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2020-04-05 18:26:04 +02:00
Adam Dybkowski
285b5d1b1f cryptodev: fix missing device id range checking
This patch adds range-checking of the device id passed from
the user app code. It prevents out-of-range array accesses
which in some situations resulted in an
application crash (segfault).

Fixes: 3dd4435cf4 ("cryptodev: fix checks related to device id")
Cc: stable@dpdk.org

Signed-off-by: Adam Dybkowski <adamx.dybkowski@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-05 18:26:04 +02:00
Mairtin o Loingsigh
09e72e8499 test/crypto: add AES-256 DOCSIS test vectors
This patch adds test vectors for AES-256 and sets QAT as the
target PMD.

Signed-off-by: Mairtin o Loingsigh <mairtin.oloingsigh@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2020-04-05 18:26:04 +02:00
Mairtin o Loingsigh
2aab3ff3d8 crypto/qat: support DOCSIS AES-256
This patch adds support for DOCSIS AES-256 when using qat

Signed-off-by: Mairtin o Loingsigh <mairtin.oloingsigh@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>
2020-04-05 18:26:04 +02:00
Lukasz Bartosik
844baa1039 examples/ipsec-secgw: reserve crypto queues in event mode
Reserve minimum number of crypto queues equal to number of ports.
This is to fulfill inline protocol offload requirements.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Lukasz Bartosik <lbartosik@marvell.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-05 18:26:04 +02:00
Lukasz Bartosik
6118acc299 doc: add event mode to ipsec-secgw
Document addition of event mode support
to ipsec-secgw application.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Lukasz Bartosik <lbartosik@marvell.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-05 18:26:04 +02:00
Lukasz Bartosik
7338a34e01 examples/ipsec-secgw: make number of buffers dynamic
Make number of buffers in a pool nb_mbuf_in_pool dependent on number
of ports, cores and crypto queues. Add command line option -s which
when used overrides dynamic calculation of number of buffers in a pool.

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Lukasz Bartosik <lbartosik@marvell.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-05 18:26:04 +02:00
Lukasz Bartosik
9ad50c29d0 examples/ipsec-secgw: add app mode worker
Add application inbound/outbound worker thread and
IPsec application processing code for event mode.

Example ipsec-secgw command in app mode:
ipsec-secgw -w 0002:02:00.0,ipsec_in_max_spi=128
-w 0002:03:00.0,ipsec_in_max_spi=128 -w 0002:0e:00.0 -w 0002:10:00.1
--log-level=8 -c 0x1 -- -P -p 0x3 -u 0x1 -f aes-gcm.cfg
--transfer-mode event --event-schedule-type parallel

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Lukasz Bartosik <lbartosik@marvell.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-05 18:26:04 +02:00
Lukasz Bartosik
4965dda045 examples/ipsec-secgw: add driver mode worker
Add driver inbound and outbound worker thread for ipsec-secgw. In driver
mode application does as little as possible. It simply forwards packets
back to port from which traffic was received instructing HW to apply
inline security processing using first outbound SA configured for
a given port. If a port does not have SA configured outbound traffic
on that port will be silently dropped. The aim of this mode is to
measure HW capabilities. Driver mode is selected with single-sa option.
The single-sa option accepts SA index however in event mode the SA
index is ignored.

Example command to run ipsec-secgw in driver mode:
ipsec-secgw -w 0002:02:00.0,ipsec_in_max_spi=128
-w 0002:03:00.0,ipsec_in_max_spi=128 -w 0002:0e:00.0 -w 0002:10:00.1
--log-level=8 -c 0x1 -- -P -p 0x3 -u 0x1 -f aes-gcm.cfg
--transfer-mode event --event-schedule-type parallel --single-sa 0

Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Lukasz Bartosik <lbartosik@marvell.com>
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
2020-04-05 18:26:04 +02:00