Clarify Intel copyright and update the date to 2020.
Fixes: 547be3f01f55 ("net/i40e/base: replace license text with SPDX tag")
Cc: stable@dpdk.org
Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
Clarify Intel copyright and update the date to 2020.
Fixes: 9db3087f4f77 ("net/ixgbe/base: update the license")
Cc: stable@dpdk.org
Signed-off-by: Xiaoyun Li <xiaoyun.li@intel.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
When set DCB in testpmd, there is a segmentation fault. It is
because the local variable rss_conf in get_eth_dcb_conf()
is not cleared, so that the pointer member variable rss_key has
a random address, which leads to an error in the following
processing. This patch initialized the local variable rss_conf
to avoid this situation.
Fixes: ac7c491c3fec ("app/testpmd: fix DCB config")
Cc: stable@dpdk.org
Signed-off-by: Ting Xu <ting.xu@intel.com>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
After memory optimization, the organization of some resources are
changed from pointer based LIST to the index based ILIST. A lot of
code parts are touched due to such change.
Some static code checking and analysis tool will complain and raise
a false warning on the uninitialized value using. E.g. in the port
action registering function, the stack variable will be used as the
right value with some uninitialized field to initialize variable
allocated from heap. But indeed, it is not an error because all the
fields set with the uninitialized value will be overwritten in the
following code part and the macros. All the fields will be used as
the left value explicitly.
It makes no sense to clear the stack variable to 0 in this case,
and the extra memset will introduce some cycles overhead. It just
needs to ignore the false warning from the tool, if any.
Fixes: f3faf9ea1185 ("net/mlx5: convert port id action to indexed")
Signed-off-by: Bing Zhao <bingz@mellanox.com>
Reviewed-by: Matan Azrad <matan@mellanox.com>
Reviewed-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
After memory optimization, some action object handles are changed to
index to save the overhead. Assertion in debug mode will be helpful
for trouble shooting.
In the current implementation, only one port action is supported in
switchdev mode for one device flow. In debug mode, an assertion will
be used to check the if the port action is none, and it should
locate before the port action resource registration but not after
it. The action index in the handle should be 0 before registration.
Or else it will always cause a failure because the port action is
registered and the index is not 0.
Fixes: f3faf9ea1185 ("net/mlx5: convert port id action to indexed")
Signed-off-by: Bing Zhao <bingz@mellanox.com>
Reviewed-by: Matan Azrad <matan@mellanox.com>
Reviewed-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
The buffer size to receive netlink reply messages is relatively
large (32K), and it is allocated on the stack and it might
break in application is using smaller per-thread stacks.
This patch allocates temporary buffer from heap.
Fixes: ccdcba53a3f4 ("net/mlx5: use Netlink to add/remove MAC addresses")
Cc: stable@dpdk.org
Reported-by: Stephen Hemminger <stephen@networkplumber.org>
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
The MLX5 device supports up to MLX5_MAX_MAC_ADDRESSES (256) MAC
addresses. The code flushes all MAC devices.
If DPDK is compiled with MLX5_DEBUG this would an assert.
PANIC in mlx5_nl_mac_addr_flush():
line 775 assert "(size_t)(i) < sizeof(mac_own) * 8" failed
The root cause is that mac_own is a pointer and is being used as
a bitmap array. The sizeof(mac_own) would therefore be 64 but the
number of entries to be flushed would be 256.
There is a whole set of asserts in MLX5 netlink code with
the same bug; that should just be changed into proper error checks.
Fixes: 8e46d4e18f09 ("common/mlx5: improve assert control")
Cc: stable@dpdk.org
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Currently, the shared counter search uses the wrong nested index which
is used by the pool index. The incorrect nested index using causes the
search go to incorrect counter pool is not existed.
Add the counter index to fix the incorrect nested use case.
Fixes: 4001d7ad26d4 ("net/mlx5: change Direct Verbs counter to indexed")
Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
The doorbell record is organized with page and bitmap. When some new
doorbell needs to be associated with a queue, the bit will be set
in the bitmap to indicate the corresponding doorbell occupied. A
counter is used to record the number of doorbell occupied to speed
up the searching.
If the number reaches the maximal value of a pre-defined number of a
page, a new page will be allocated. If not, then the bitmap will be
checked to find a free one.
The LSHIFT and OR (AND NOT) operations are used to update the bitmap
of a page. But 1 will be treated as a signed integer when compiling.
When the shift number is 31, the shifted value will be considered as
negative. Then a wrong extension will be done when setting it to a
64-bits variable. All the upper 32-bits will be set to 1 by such
extension.
Then a wrong offset value will be calculated because of this. The
next 64 bits will be also treated as the bitmap and get corrupted
through the bit set operation.
The immediate value 1 needs to be used as 64 bits width explicitly.
Fixes: 21cae8580fd0 ("net/mlx5: allocate door-bells via DevX")
Cc: stable@dpdk.org
Signed-off-by: Bing Zhao <bingz@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
When create the Verbs flows with counter, randomly SEGSEV will also
comes. The reason is that the counter pool memory is not allocated
sufficiently and initialized correctly in Verbs case.
As the mlx5_flow_counter array member is moved out of the counter pool
struct, the counter pool memory layout currently contain implicitly
with mlx5_flow_counter, mlx5_age_param(if the pool is an age pool),
mlx5_flow_counter_ext(if the pool is a none batch pool). When allocate
the pool memory, the pool size should be calculated based on the pool
type accordingly.
Currently, for Verbs counter pool, both mlx5_flow_counter and
mlx5_flow_counter_ext need to be taken into account in the pool size.
And the pool type should also be initialized as CNT_POOL_TYPE_EXT.
This patch add the missing size and type for the Verbs counter pool.
Fixes: 8d93c830e450 ("net/mlx5: modify ext-counter memory allocation")
Signed-off-by: Suanming Mou <suanmingm@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
CVL kernel PF configures all reserved queues for VF, including
Rx queue RXDID. The number of reserved queues is the maximum
between Tx and Rx queues. If the number of the enabled Rx queues
is less than that of reserved queues, required RXDID will only
be set for those enabled, but default value (0) is set for others.
However, RXDID 0 (legacy 16byte descriptor) is not supported now,
PF will return error when configuring those disabled VF queues.
In this patch, required RXDID is set for all reserved Rx queues,
no matter enabled or not. In this way, PF will configure Rx
queues correctly without reporting error.
Fixes: b8b4c54ef9b0 ("net/iavf: support flexible Rx descriptor in normal path")
Signed-off-by: Ting Xu <ting.xu@intel.com>
Tested-by: Xiaoxiao Zeng <xiaoxiaox.zeng@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
This patch fixes the issue that the queue region does not
take effect due to incorrectly setting the flow type.
Fixes: ecad87d22383 ("net/i40e: move RSS to flow API")
Cc: stable@dpdk.org
Signed-off-by: Shougang Wang <shougangx.wang@intel.com>
Reviewed-by: Jeff Guo <jia.guo@intel.com>
Tested-by: Hailin Xu <hailinx.xu@intel.com>
Tested-by: Lunyuan Cui <lunyuanx.cui@intel.com>
This patch adds support for FDIR passthrough mode. When FDIR rule
hits, FDIR just forward this packet to the next stage filter.
Fixes: 55daca4e45fc ("net/ice/base: change function to static")
Signed-off-by: Simei Su <simei.su@intel.com>
Tested-by: Xiaoxiao Zeng <xiaoxiaox.zeng@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
Fix to allocate bnxt ulp context when TRUFLOW is enabled.
This patch reduces the size of struct bnxt.
Fixes: 313ac35ac701 ("net/bnxt: support ULP session manager init")
Signed-off-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
We are maintaining MAC address twice which is unnecessary.
This patch removes the copy which helps reduce size of bnxt structure.
Fixes: b7778e8a1c00 ("net/bnxt: refactor to properly allocate resources for PF/VF")
Cc: stable@dpdk.org
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
There is no need to maintain local copy.
This helps reduce the size of the bnxt structure.
Fixes: fcc0aa1edc10 ("net/bnxt: add RSS hash configuration")
Cc: stable@dpdk.org
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Consolidate flow stat related structs for performance improvement.
The intention of this patch is to reduce the size struct bnxt which
had grown because of recent changes and was impacting performance.
Fixes: 02a95625fe9c ("net/bnxt: add flow stats in extended stats")
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Log the command sequence number to aid debug in case of a
FW command timeout.
Fixes: 804e746c7b73 ("net/bnxt: add hardware resource manager init code")
Cc: stable@dpdk.org
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
This patch fixes deallocation of all fastpath resources unconditionally,
when re-configuring the device. When re-allocating resources PMD depends
on application to explicitly setup the Rx/Tx queue.
Deallocation of all the resources is only required if the Rx/Tx queue
configuration changes. For other scenarios like KNI MTU change we'd keep
existing configuration.
Fixes: 8de0c4201926 ("net/qede: fix odd number of queues usage in 100G mode")
Fixes: dd28bc8c6ef4 ("net/qede: fix VF port creation sequence")
Cc: stable@dpdk.org
Signed-off-by: Rasesh Mody <rmody@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Fix to assign dummy Rx/Tx handlers in dev_stop.
For MTU set, assignment of the appropriate Rx/Tx handlers will be
handled by dev_start/dev_stop.
Fixes: 81f8804992c9 ("net/qede: enhance Rx CPU utilization")
Fixes: 8de0c4201926 ("net/qede: fix odd number of queues usage in 100G mode")
Cc: stable@dpdk.org
Signed-off-by: Rasesh Mody <rmody@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Add a separate section for low-resolution generic counter
for ARM64 profiling methods.
Signed-off-by: Dharmik Thakkar <dharmik.thakkar@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Phil Yang <phil.yang@arm.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Change printing of CPU cycles/packet to include fractional part for
accurateness.
Example:
Without patch:
CPU cycles/packet=14
(total cycles=4899533541 / total RX packets=343031966)
With patch:
CPU cycles/packet=14.28
(total cycles=4899533541 / total RX packets=343031966)
Signed-off-by: Dharmik Thakkar <dharmik.thakkar@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Phil Yang <phil.yang@arm.com>
Acked-by: Bernard Iremonger <bernard.iremonger@intel.com>
On aarch64 platforms, the cycles are counted using either a
low-resolution generic counter or a high-resolution PMU cycle counter.
Print the clock frequency along with CPU cycles/packet to identify which
cycle counter is being used.
Signed-off-by: Dharmik Thakkar <dharmik.thakkar@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Phil Yang <phil.yang@arm.com>
Acked-by: Bernard Iremonger <bernard.iremonger@intel.com>
In vhost_blk_bdev_construct: The string buffer may not have
a null terminator if the source string's length is equal to
the buffer size.
Fixes: 91d3e2d42997 ("examples/vhost_blk: refactor to increase readability")
Signed-off-by: Jin Yu <jin.yu@intel.com>
Reviewed-by: Xiaolong Ye <xiaolong.ye@intel.com>
Event notification should be disabled after virtqueue initialization and
enabled by calling rte_eth_dev_rx_intr_enable later. When virtio user
device reconnecting to vhost, virtqueue_disable_intr should be called to
disable event notification.
Fixes: 6ebbf4109f35 ("net/virtio-user: fix packed ring server mode")
Cc: stable@dpdk.org
Signed-off-by: Marvin Liu <yong.liu@intel.com>
Acked-by: Xiao Wang <xiao.w.wang@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Runtime checks for vectorized datapath are organized into device
configuration function. Remove duplicated check in device init
function.
Signed-off-by: Marvin Liu <yong.liu@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
vhost buffer allocation is successful for packets that fit
into a linear buffer. If it fails, vhost library is expected
to drop the current packet and skip to the next.
The patch fixes the error scenario by skipping to next packet.
Note: Drop counters are not currently supported.
Fixes: c3ff0ac70acb ("vhost: improve performance by supporting large buffer")
Cc: stable@dpdk.org
Signed-off-by: Sivaprasad Tummala <sivaprasad.tummala@intel.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
Before updating RSS indirection table, firstly determine whether
rq num in RETA table is legal, if it is invalid(such as exceeding
the maximum rxq num), driver will not update hw indirection
table and return fail.
Signed-off-by: Xiaoyun Wang <cloud.wangxiaoyun@huawei.com>
The patch modifies the comments of structures or functions, and adds
space for comments, removes extra empty lines and adjusts the
print level for VF branches in one sdk interface.
Signed-off-by: Xiaoyun Wang <cloud.wangxiaoyun@huawei.com>
When copy a mbuf to a new dst_mbuf, the pkt_len member of
dst_mbuf needs to be updated.
Fixes: 076221c8fe1d ("net/hinic: add Rx/Tx")
Cc: stable@dpdk.org
Signed-off-by: Xiaoyun Wang <cloud.wangxiaoyun@huawei.com>
Adds tx_queues and rx_queues non-null judgment before free tx or
rx resources, because some app may set tx_queues or rx_queues to
be null before call free resource interfaces, which may cause
a segfault.
Fixes: 64727024d2fd ("net/hinic: add device initialization")
Cc: stable@dpdk.org
Signed-off-by: Xiaoyun Wang <cloud.wangxiaoyun@huawei.com>
The VMXNet3 protocol has a start-of-packet (SOP) and end-of-packet (EOP)
marker. If there was a bug where mbuf arrived without SOP the code that
chains the mbuf would dereference a null pointer.
Also, record any mbuf's dropped in statistics.
Although did the initial code no longer have access to VMware.
Compile tested only!
Coverity issue: 124563
Fixes: 8ee787ce80a8 ("vmxnet3: remove asserts that confuse coverity")
Cc: stable@dpdk.org
Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
Acked-by: Yong Wang <yongwang@vmware.com>
Removing the current limitation for TSO over VM
due to the fact that mlx5 currently support it.
Signed-off-by: Raslan Darawsheh <rasland@mellanox.com>
Acked-by: Asaf Penso <asafp@mellanox.com>
Previous patch added support of VLAN item without VLAN ID value,
i.e. using wildcard VLAN item, to match VLAN with any VLAN ID.
The implication on VLAN actions was not taken into consideration.
VLAN actions (e.g. push vlan) use the VLAN ID value in the VLAN item,
and expect it to be valid.
This patch updates function flow_dev_get_vlan_info_from_items() to
check the VLAN item contents before trying to use it.
Fixes: 92818d839e8e ("net/mlx5: fix match on empty VLAN item in DV mode")
Cc: stable@dpdk.org
Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
The design of counter container resize used double buffer algorithm in
order to synchronize between the query thread to the control thread.
When the control thread detected resize need, it created new bigger
buffer for the counter pools in a new container and change the container
index atomically.
In case the query thread had not detect the previous resize before a new
one need was detected by the control thread, the control thread returned
EAGAIN to the flow creation API used a COUNT action.
The rte_flow API doesn't allow unblocked commands and doesn't expect to
get EAGAIN error type.
So, when a lot of flows were created between 2 different periodic
queries, 2 different resizes might try to be created and caused EAGAIN
error.
This behavior may blame flow creations.
Change the synchronization way to use lock instead of double buffer
algorithm.
The critical section of this lock is very small, so flow insertion
rate should not be decreased.
Fixes: ebbac312e448 ("net/mlx5: resize a full counter container")
Cc: stable@dpdk.org
Signed-off-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
If running DPDK as non-root, some extra capabilities may be required.
The Mellanox devices, using a bifurcated model with Linux drivers,
have some specific requirements summarized in mlx5 PMD guide.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Reviewed-by: Raslan Darawsheh <rasland@mellanox.com>
Move link state enable/disable to dev_start() and dev_stop()
respectively. This will ensure when devices are stopped,
link status will be appropriately shown as down.
Fixes: dd28bc8c6ef4 ("net/qede: fix VF port creation sequence")
Cc: stable@dpdk.org
Signed-off-by: Shahed Shaikh <shshaikh@marvell.com>
Signed-off-by: Rasesh Mody <rmody@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
This patch fixes the issue that failed to create an RSS rule with type
L2-payload.
Fixes: feaae285b342 ("net/i40e: support hash configuration in RSS flow")
Signed-off-by: Shougang Wang <shougangx.wang@intel.com>
Tested-by: Hailin Xu <hailinx.xu@intel.com>
Reviewed-by: Jeff Guo <jia.guo@intel.com>
When configure RSS rule, the etherdev rss hash function type should be
mapped to the corresponding virtchnl rss algorithm type.
Fixes: 7be10c3004be ("net/iavf: add RSS configuration for VF")
Signed-off-by: Jeff Guo <jia.guo@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
A typo need to be fixed for Simple XOR algorithm configuration.
Fixes: 57094d594324 ("common/iavf: support advanced RSS input set change")
Signed-off-by: Jeff Guo <jia.guo@intel.com>
Acked-by: Xiaolong Ye <xiaolong.ye@intel.com>
When the driver is loaded on a 200G NIC, the port speed is not
displayed correctly. Parse the 200G speed before displaying it.
Signed-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Relaxed ordering is a PCI optimization that enables reordering
reads/writes in order to improve performance.
Relaxed ordering was enabled for all processors causing
a degradation in performance in Haswell and Broadwell processors
that don't support this optimization.
In order to avoid that we check if the processor is Haswell
or Broadwell and if so we disable relaxed ordering.
Signed-off-by: Shiri Kuzin <shirik@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
In order to improve performance relaxed ordering was enabled
when creating count object using Devx.
Currently rte enables this optimization by default when using
Devx.
This causes an issue when using firmware that does not have this
capability causing a count object failure.
In order to fix this issue a check of firmware capabilities was
added before enabling relaxed ordering.
Fixes: 53ac93f71ad1 ("net/mlx5: create relaxed ordering memory regions")
Signed-off-by: Shiri Kuzin <shirik@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Relaxed ordering is a PCI optimization that allows reordering
of reads/writes in order to improve performance.
In order to enable this optimization only when relaxed ordering
is supported, it is checked if IBV_ACCESS_RELAXED_ORDERING is
defined in verbs.h.
Since IBV_ACCESS_RELAXED_ORDERING is an enum and not
defined relaxed ordering wasn't enabled even when supported.
This issue is fixed by using AUTOCONF to check if relaxed
ordering is supported and disabling only if it isn't.
Fixes: 53ac93f71ad1 ("net/mlx5: create relaxed ordering memory regions")
Signed-off-by: Shiri Kuzin <shirik@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
This patch fixes the issue that the flow which both source MAC mask
and destination MAC mask are all zeros can not be created.
Fixes: ea0c22fd8227 ("net/i40e: enable MAC address as flow director input set")
Signed-off-by: Shougang Wang <shougangx.wang@intel.com>
Tested-by: Hailin Xu <hailinx.xu@intel.com>
Reviewed-by: Jeff Guo <jia.guo@intel.com>
