The `mp_cb_registered` flag shared between all processes
was used to ensure that for any IB device (MLX5 common device)
mempool event callback was registered only once
and mempools that had been existing before the device start
were traversed only once to register them.
Since mempool callback registrations have become process-private,
callback registration must be done by every process.
The flag can no longer reflect the state for any single process.
Replace it with a registration counter to track
when no more callbacks are registered for the device in any process.
It is sufficient to only register pre-existing mempools
in the primary process because it is the one that starts the device.
Fixes: 690b2a88c2 ("common/mlx5: add mempool registration facilities")
Cc: stable@dpdk.org
Signed-off-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Add fixed point multiplication for EC curve in CNXK.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Signed-off-by: Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>
Acked-by: Anoob Joseph <anoobj@marvell.com>
Enabled the flag pmd_supports_disable_iova_as_pa in cnxk driver build
files as they work with IOVA as VA. Updated cn9k and cn10k soc build
configurations to disable the IOVA as PA build by default.
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Acked-by: Olivier Matz <olivier.matz@6wind.com>
This patch adds new HCA capability related to hairpin RQs. This new
capability, hairpin_data_buffer_locked, indicates whether HCA supports
locking data buffer of hairpin RQ in ICMC (Interconnect Context Memory
Cache).
Struct used to define RQ configuration (RQ context) is extended with
hairpin_data_buffer_type field, which configures data buffer for hairpin
RQ. It can take the following values:
- MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_UNLOCKED_INTERNAL_BUFFER - hairpin
RQ's data buffer is stored in unlocked memory in ICMC.
- MLX5_RQC_HAIRPIN_DATA_BUFFER_TYPE_LOCKED_INTERNAL_BUFFER - hairpin
RQ's data buffer is stored in locked memory in ICMC.
Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
This patch extends HCA_CAP and SQ Context structs available in PRM. This
fields allow checking if NIC supports storing hairpin SQ's WQ buffer in
host memory and configuring such memory placement.
HCA capabilities are extended with the following fields:
- hairpin_sq_wq_in_host_mem - If set, then NIC supports using host
memory as a backing storage for hairpin SQ's WQ buffer.
- hairpin_sq_wqe_bb_size - Indicates the required size of SQ WQE basic
block.
SQ Context is extended with hairpin_wq_buffer_type which informs
NIC where SQ's WQ buffer will be stored. This field can take the
following values:
- MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_INTERNAL_BUFFER - WQ buffer will be
stored in unlocked device memory.
- MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_HOST_MEMORY - WQ buffer will be stored
in host memory. Buffer is provided by PMD.
Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Change cidx and pidx definition to mean used queue and avail
queue index respectively.
Signed-off-by: Abhimanyu Saini <absaini@amd.com>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Pickup new FW interface definitions for avail and used indexes.
Signed-off-by: Abhimanyu Saini <absaini@amd.com>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
The used/avail queue indexes are not bound by queue size,
because HW calculates descriptor entry index by performing
a simple modulo between queue index and queue_size.
So, do not check initial used and avail queue indexes
against queue size because it is possible for these
indexes to be greater than queue size in the
following cases:
1) The queue is created to be migrated into, or
2) The client issues a qstop/qstart after running datapath
Fixes: 4dda72dbde ("common/sfc_efx/base: add base virtio support for vDPA")
Cc: stable@dpdk.org
Signed-off-by: Abhimanyu Saini <absaini@amd.com>
Acked-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Added support for CN10K SoC DMA engine to dmadev.
Signed-off-by: Radha Mohan Chintakuntla <radhac@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
Such information is useful to client drivers which deal with
large Rx pool buffers (16-bit wide data count) and thus need
to avoid overflow when setting EF10's 14-bit wide data count.
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Maximum data count of a Tx descriptor is advertised to users,
however, this value is mistakenly derived from the Rx define.
Use the Tx one instead. The resulting value will be the same.
Fixes: 1e43fe3cb4 ("net/sfc/base: separate limitations on Tx DMA descriptors")
Cc: stable@dpdk.org
Signed-off-by: Ivan Malov <ivan.malov@oktetlabs.ru>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
Added changes to base rule install mechanism.
If action type is IPsec and multi channel is set,
then base rule will not be merged.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
Reviewed-by: Satheesh Paul <psatheesh@marvell.com>
Current PMD logs all DevX errors at error level.
DevX interface can fail queue counters allocation on some hardware
types. That is a known issue.
PMD fallbacks to Verbs API to allocate queue counters
when it detects the fault.
That DevX failure should not be logged as PMD error.
The patch provides DevX with flexible API that selects log level.
Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
VF is able to subscribe a flow from PF by VIRTCHNL_FLOW_SUBSCRIBE.
PF is expected to offload a rule to hardware which will redirect
the packet that matching the required pattern to this VF.
Only a flow with dst mac address as PF's mac address can be subscribed.
VIRTCHNL_VF_OFFLOAD_FSUB_PF is used for Flow subscription capability
negotiation and only a trusted VF can be granted with this capability.
A flow can be unsubscribed by VIRTCHNL_FLOW_UNSUBSCRIBE.
Signed-off-by: Jie Wang <jie1x.wang@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
If cmd_details are defined or async flag is set,
don't copy the desc/buff back to temp.
Fixes: e5b2a9e957 ("net/avf/base: add base code for avf PMD")
Cc: stable@dpdk.org
Signed-off-by: Steven Zou <steven.zou@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
Disable timer resolution estimation, read TIM LF clock registers
to get the current running clock counter as estimating causes
time drift.
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Removed support to limit XAQ from devargs. If XAQ is limited, new add
works could run out of XAQ entries and disable the queue.
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Add support for offloading RTE_CRYPTO_CIPHER_AES_DOCSISBPI and
RTE_CRYPTO_CIPHER_DES_DOCSISBPI algorithms to symmetric crypto session.
Signed-off-by: Volodymyr Fialko <vfialko@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
Errors in crypto adapter datapath can be handled gracefully. So the
error print can be moved under debug.
Signed-off-by: Shijith Thotton <sthotton@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
'struct roc_se_buf_ptr ctx_buf' has fields for a pointer and len.
The field for len was unused.
It is removed and the required pointer is added in the parent struct.
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
This commit fixes answer sent to physical device in
vf2pf communication.
Fixes: b17d16fb47 ("common/qat: add PF to VF communication")
Cc: stable@dpdk.org
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Fan Zhang <roy.fan.zhang@intel.com>
Arm port of ipsec_mb library [1] has different header file name than
the Intel ipsec_mb library. Proper header name is picked according to
the architecture to get the code compile when ipsec_mb is installed on
Arm platform.
And the Arm port currently supports ZUC and SNOW3g. Call to other
algorithms will be blocked.
[1] https://gitlab.arm.com/arm-reference-solutions/ipsec-mb/-/tree/main
Signed-off-by: Ruifeng Wang <ruifeng.wang@arm.com>
Acked-by: Ashwin Sekhar T K <asekhar@marvell.com>
This patch add in libcrypto version check before enable libipsec-mb for
QAT. The intel-ipsec-mb lib for partial hash and AES calculation should
only be enabled when both OpensSSL 3.0 and IPSec_MB 1.2.0 are installed
on the system.
Fixes: 3227bc7138 ("crypto/qat: use intel-ipsec-mb for partial hash and AES")
Cc: stable@dpdk.org
Signed-off-by: Kai Ji <kai.ji@intel.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>
When dumping hardware flow data, print any counter
configured on the flow as well.
Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Reviewed-by: Kiran Kumar K <kirankumark@marvell.com>
Add helper API to complete device info for debug purposes.
This is used by ethdev dump API to dump ethdev's internal info.
Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
Update CQ threshold limit associated with sq.
This is used when we need completions for packets that are
successfully transmitted.
Signed-off-by: Kommula Shiva Shankar <kshankar@marvell.com>
Added mailbox for masking and setting nix_rq_ctx
parameters and enabling rq masking in ipsec_cfg1
so second pass is applied to all RQ's
Signed-off-by: Rakesh Kudurumalla <rkudurumalla@marvell.com>
Updated shaper profile with user configurable RED algorithm.
This helps in configuring a TM node in red drop mode vs
stall mode.
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
This patch set enables aging on CNF105 variant of CN10K platform.
Enables aging statistics while dumping/reset SQ statistics.
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
Use the Full context SA structures and command in IPsec fast path.
For inline outbound, populate CPT instruction as per full context.
Added new macros and functions with respect to full context.
Populate WQE ptr in CPT instruction with proper offset from mbuf.
Also add option to override outbound inline SA IV for debug
Update mbuf length based on IP version in Rx post process purposes
via environment variable.
User can set env variable as:
export ETH_SEC_IV_OVR="0x0, 0x0,..."
Signed-off-by: Vidya Sagar Velumuri <vvelumuri@marvell.com>
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add support to create zero aura for inline inbound meta packets when
platform supports it.
AURA zero will hold as many buffers as all the available
pkt pool with a data to accommodate 384B in best case to store
meta packets coming from Inline IPsec.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Update attributes to pools used by NIX so that we
can later identify which mempools are packet pools
and which are used for Inline IPsec enabled ethdev.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add support to set/get per-aura buf type with refs and
get sum of all aura limits matching given buf type mask
and val.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Reserve AURA id 0 on cn10k and provide mechanism to specifically
allocate it and free it via roc_npa_* API's.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Similar to other RQ's, delay inline device RQ until dev is started
to avoid traffic reception when device is stopped.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Limit meta AURA workaround to CN10K A0.
Also other NIX and Inline related Erratas applicable for CN10K A1.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Updates CPT inbound inline IPsec configuration mailbox
to provide opcode and CPT credit from VF.
This patch also adds mailbox for reading inbound IPsec
configuration.
Signed-off-by: Srujana Challa <schalla@marvell.com>
Updating the logic for getting part and pass value for cn10k family,
as device tree compatible logic does not work in VMs.
Scanning all the PCI device and detect first RVU device, subsystem
device file gives part no and revision file provide pass information.
Fixes: 014a9e222b ("common/cnxk: add model init and IO handling API")
Cc: stable@dpdk.org
Signed-off-by: Harman Kalra <hkalra@marvell.com>
