Commit Graph

657 Commits

Author SHA1 Message Date
Robin Zhang
6fd3889c17 net/ice/base: support E824S and E825 devices
Add support for E824S and E825 family devices.

This will be documented later in release notes since devices are not
mature yet to announce to users.

Signed-off-by: Robin Zhang <robinx.zhang@intel.com>
Acked-by: Ferruh Yigit <ferruh.yigit@intel.com>
2022-02-25 15:06:01 +01:00
Yuying Zhang
a62f095049 net/ice/base: add profile validation on switch filter
Profile type was determined without validation when getting
switch field vector bitmap. It caused error when associating
profile id with given recipe if no lookup elements were given.
Add profile validation to check if the profile is existing
before getting bitmap.

Fixes: 55744222e6 ("net/ice/base: associate recipes by profile type")
Cc: stable@dpdk.org

Signed-off-by: Yuying Zhang <yuying.zhang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2022-02-09 03:16:29 +01:00
Junfeng Guo
b5d753f233 net/ice/base: fix GTPU UL/DL flag
Just fix the wrong defines of GTPU flags between UL and DL. These two
are defined are misplaced to each other.

Fixes: 8ebb93942b ("net/ice/base: add function to set HW profile for raw flow")

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-11-16 01:59:03 +01:00
Ting Xu
0837da2e27 net/ice/base: support add HW profile for RSS raw flow
Based on the parser library, we can directly set HW profile and
associate VSI for RSS raw flows. Add symmetric hash configuration
for raw flow.

Signed-off-by: Ting Xu <ting.xu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-11-04 04:10:43 +01:00
Junfeng Guo
8ebb93942b net/ice/base: add function to set HW profile for raw flow
Based on the parser library, we can directly set HW profile and
associate the main/ctrl vsi.

This patch set also updated the base code BSD release version.

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-11-03 13:00:27 +01:00
Junfeng Guo
dea1ebd374 net/ice/base: add method to disable FDIR swap option
In this patch, we introduced a new parameter to enable/disable the
FDIR SWAP option by setting the swap and inset register set with
certain values.

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-11-03 13:00:06 +01:00
Junfeng Guo
c2450e933f net/ice/base: fix null pointer dereferences for parser
Null-checking "p" suggests that it may be null, but it has already
been dereferenced on all paths leading to the check. Thus correct
the code lines and remove the redundant line.

Fixes: c84f8aa210 ("net/ice/base: add parser runtime skeleton")

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-10-13 12:29:54 +02:00
Junfeng Guo
c99174deba net/ice/base: fix parser runtime reset
Adjust the code line order of the parser runtime reset, since the
struct rt->psr is used in function _rt_flag_set before assignment.

Fixes: c84f8aa210 ("net/ice/base: add parser runtime skeleton")
Cc: stable@dpdk.org

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-10-13 04:10:10 +02:00
Aman Deep Singh
16b809d144 net/ice/base: fix strict-aliasing with GCC
Code changes done for build issue as reported in Bug 817
error: dereferencing type-punned pointer will break strict-aliasing rules.
added union to avoid pointer dereferencing

The build issue has been reported with both gcc 4.8.5 (RHEL 7) and
gcc 5.4.0 (Ubuntu 16.04).

Bugzilla ID: 817
Fixes: 39925373a3 ("net/ice/base: add parser execution main loop")

Signed-off-by: Aman Deep Singh <aman.deep.singh@intel.com>
Tested-by: David Marchand <david.marchand@redhat.com>
Acked-by: Ferruh Yigit <ferruh.yigit@intel.com>
2021-10-05 16:59:06 +02:00
Qi Zhang
d8aaa6d9c2 net/ice/base: add API for parser profile initialization
Add API ice_parser_profile_init to init a parser profile base on
a parser result and a mask buffer. The ice_parser_profile can feed to
low level FXP engine to create HW profile / field vector directly.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 15:17:58 +02:00
Qi Zhang
6065f4cdc3 net/ice/base: support tunnel port for parser
UDP tunnel can be added/deleted for vxlan, geneve, ecpri through
below APIs:
ice_parser_vxlan_tunnel_set
ice_parser_geneve_tunnel_set
ice_parser_ecpri_tunnel_set

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 15:17:58 +02:00
Qi Zhang
cc3f51e466 net/ice/base: support double VLAN mode configure for parser
Add API ice_parser_dvm_set to support turn on/off parser's
double vlan mode.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 15:17:58 +02:00
Qi Zhang
39925373a3 net/ice/base: add parser execution main loop
Implement function ice_parser_rt_execute which perform the main
loop of the parser.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 15:17:58 +02:00
Qi Zhang
70ada0c508 net/ice/base: add helper function to aggregate flags
Add internal helper function ice_xlt_kb_flg_get to aggregate 64 bit
packet flag into 16 bit key builder flags.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 15:17:58 +02:00
Qi Zhang
1c9e61b3a4 net/ice/base: add helper function to redirect flags
Add internal helper function ice_flg_redirect to redirect parser flags
to packet flags.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 15:17:58 +02:00
Qi Zhang
510965b4dc net/ice/base: add helper for ptype markers match
Add internal helper function ice_ptype_mk_tcam_match for ptype markers
matching in tcam table.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 15:17:58 +02:00
Qi Zhang
d490f1ff41 net/ice/base: add helper for parse graph key matching
Add below two internal helper functions for parse graph key matching
in cam table:

ice_pg_cam_match
ice_pg_nm_cam_match

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 15:17:58 +02:00
Qi Zhang
4b20fa1b1d net/ice/base: add helper function for boost TCAM match
Add internal helper function ice_bst_tcam_match to perform ternary
match on boost TCAM.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 15:17:58 +02:00
Qi Zhang
c84f8aa210 net/ice/base: add parser runtime skeleton
Add parser runtime data struct ice_parser_rt.

Add below APIs for parser runtime preparation:
ice_parser_rt_reset
ice_parser_rt_pkt_buf_set

Add below API skeleton for parser runtime execution:
ice_parser_rt_execute

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 15:17:57 +02:00
Qi Zhang
0cbacf60dc net/ice/base: init XLT key builder for parser
Parse below DDP section into struct ice_xlt_kb:
ICE_SID_XLT_KEY_BUILDER_SW
ICE_SID_XLT_KEY_BUILDER_FD
ICE_SID_XLT_KEY_BUILDER_RSS

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 15:17:57 +02:00
Qi Zhang
f787952d13 net/ice/base: init flag redirect table for parser
Parse DDP section ICE_SID_RXPARSER_FLAG_REDIR into an array of
ice_flag_rd_item.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 15:17:57 +02:00
Qi Zhang
7b61be517f net/ice/base: init protocol group table for parser
Parse DDP section ICE_SID_RXPARSER_PROTO_GRP into an array of
ice_proto_grp_item.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 15:17:57 +02:00
Qi Zhang
90bbd7d954 net/ice/base: init marker group table for parser
Parse DDP section ICE_SID_RXPARSER_MARKER_GRP into an array of
ice_mk_grp_item.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 15:17:57 +02:00
Qi Zhang
111871087c net/ice/base: init ptype marker TCAM table for parser
Parse DDP section ICE_SID_RXPARSER_MARKER_PTYPE into an array of
ice_ptype_mk_tcam_item.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 15:17:57 +02:00
Qi Zhang
1792942b2d net/ice/base: init boost TCAM table for parser
Parse DDP section ICE_SID_RXPARSER_CAM into an array of
ice_bst_tcam_item.
Parse DDP section ICE_SID_LBL_RXPARSER_TMEM into an array of
ice_lbl_item.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 15:17:57 +02:00
Qi Zhang
c55b1ba93f net/ice/base: init parse graph CAM table for parser
Parse DDP section ICE_SID_RXPARSER_CAM or ICE_SID_RXPARSER_PG_SPILL
into an array of struct ice_pg_cam_item.
Parse DDP section ICE_SID_RXPARSER_NOMATCH_CAM or
ICE_SID_RXPARSER_NOMATCH_SPILL into an array of struct ice_pg_nm_cam_item.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 15:17:57 +02:00
Qi Zhang
2f7a1864cc net/ice/base: init metainit table for parser
Parse DDP section ICE_SID_RXPARSER_METADATA_INIT into an array of
struct ice_metainit_item.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 15:17:57 +02:00
Qi Zhang
b3e73a812f net/ice/base: init IMEM table for parser
Parse DDP section ICE_SID_RXPARSER_IMEM into an array of
struct ice_imem_item.

The Instruction Memory (IMEM) section contains three VLIW instructions
for the ALUs, a key extraction instruction for the Parse Graph CAM, and
several other fields.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 15:17:55 +02:00
Qi Zhang
7fe2d98070 net/ice/base: add parser create and destroy skeleton
Add new parser module which can parse a packet in binary
and generate information like ptype, protocol/offset pairs
and flags which can be used to feed the FXP profile creation
directly.

The patch added skeleton of the parser instance create and
destroy APIs:
ice_parser_create
ice_parser_destroy

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 14:43:23 +02:00
Qi Zhang
b644b5cf4c net/ice/base: update auto-generated hardware register
Update ice_hw_autogen.h.
Remove duplicated one in ice_nvm.h.
Replace ICE_NVM_ACCESS_GL_HIBA_MAX with GL_HIBA_MAX_INDEX.

Signed-off-by: Scott W Taylor <scott.w.taylor@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 14:33:46 +02:00
Qi Zhang
b3d1ca7d37 net/ice/base: support SMA controller
Add support for controlling SMA (SubMiniature version A) connectors
using GPIO get/set AQs.

Signed-off-by: Maciej Machnikowski <maciej.machnikowski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 14:33:44 +02:00
Qi Zhang
a173a67bf7 net/ice/base: add get/set functions for shared parameters
Add functions used by the driver for setting and getting the shared
driver parameters. These will be used by the driver in order to share
the PTP clock index identifier between PF drivers.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 14:33:42 +02:00
Qi Zhang
c31095a0b2 net/ice/base: add GCO defines and GCO flex descriptor
Added the memory needed for the generic checksum offload (GCO)
feature, including the new flex descriptor ICE_RXDID_GSC.

Signed-off-by: Alice Michael <alice.michael@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 14:33:39 +02:00
Qi Zhang
8e9091f57e net/ice/base: add helper to check for 100M speed support
Add a helper function to check if the underlying part can
support 100M speeds.

Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 14:33:37 +02:00
Qi Zhang
a61ec03d6a net/ice/base: add package segment ID
DDP package format is shared with different devices, for E810 device
we only support SEGMENT_TYPE_ICE_810.

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 14:33:34 +02:00
Qi Zhang
a972972fe0 net/ice/base: allow tool access to manageability register
E810-T supports signed netlists and to support this, the NVM update
tool needs to be able to read the GL_MNG_DEF_DEVID register. Add
said register to the allowlist in ice_validate_nvm_rw_reg.

Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 14:33:32 +02:00
Qi Zhang
ed2ffccdc1 net/ice/base: change address parameter to 16-bit
Change one of the input parameter (addr) in ice_read_cgu_reg_e822 and
ice_write_cgu_reg_e822 functions. This will avoid the shrink down
conversion from addr to cgu_msg.msg_addr_low.

Signed-off-by: Chinh T Cao <chinh.t.cao@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 14:33:30 +02:00
Qi Zhang
2e826e6462 net/ice/base: allow to enable LAN and loopback in switch
Currently shared code API does not allow to set/unset lb_en
and lan_en flags for advanced rules during their creation.
Because of that we have to use a workaround in switchdev
which is to update rule immediately after its creation.
This change will allow us to set/unset those flags right
away.

Signed-off-by: Wojciech Drewek <wojciech.drewek@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 14:33:28 +02:00
Qi Zhang
cb9c171a24 net/ice/base: use macro instead of open-coded division
For some operating systems, 64-bit division requires using specific
implementations. Use the DIV_64BIT macro to replace open-coded division
so that the driver may convert this to the appropriate operating-system
specific implementation when necessary.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 14:33:26 +02:00
Qi Zhang
8d90c55c45 net/ice/base: include more E810T adapters
Expand the ice_is_e810t to include:
- Intel(R) Ethernet Network Adapter E810-C-Q2T
- Intel(R) Ethernet 25G 4P E810-XXV-st

Signed-off-by: Maciej Machnikowski <maciej.machnikowski@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 14:33:24 +02:00
Qi Zhang
3affa0ef2d net/ice/base: calculate logical PF ID
In some devices, the function numbers used are non-contiguous. For
example, some two port devices will report as functions 0 and 2.

When distributing RSS and FDIR masks, which are global resources across
the active devices, it is required to have a contiguous PF id, which can
be described as a logical PF id. In the case above, function 0 would
have a logical PF id of 0, and function 2 would have a logical PF id of
1.

Using logical PF id can properly describe which slice of resources can
be used by a particular PF.

Cc: stable@dpdk.org

Signed-off-by: Dan Nowlin <dan.nowlin@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-09-21 14:33:18 +02:00
Steve Yang
ccf69617ce net/ice/base: support L4 for QinQ switch filter
This patch adds more dummy packet types for QinQ packet,
it enables tcp/udp layer of ipv4/ipv6 for QinQ payload,
so we can use L4 dst/src port as input set for switch
filter.

Signed-off-by: Steve Yang <stevex.yang@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-09-16 09:12:18 +02:00
Dapeng Yu
f979702337 net/ice/base: fix PF ID for DCF
In original implementation, if DCF is created on PF1, the PF ID is
still 0, but not 1. Without the right PF ID, the ACL will not work.

This patch makes VF to get its parent's physical function ID.

Fixes: 0b02c95194 ("net/ice: handle PF initialization by DCF")
Cc: stable@dpdk.org

Signed-off-by: Dapeng Yu <dapengx.yu@intel.com>
Acked-by: Haiyue Wang <haiyue.wang@intel.com>
2021-09-13 04:48:09 +02:00
Wenjun Wu
e4d745abaf net/ice/base: support flow director for IPv6 fragments
Add L2 and L3 FDIR field support for IPv6 fragment packets.

Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
2021-08-29 13:13:52 +02:00
Qi Zhang
2337015643 net/ice/base: increase maximum TCAM/PTG per profile
For GTPoGRE protocol in AVF FDIR/RSS, the number of associated PTGs
of one Profile may exceed the defined ICE_MAX_PTG_PER_PROFILE and
ICE_MAX_TCAM_PER_PROFILE. In those cases, some PTGs may be missed,
and therefore, the related and received packets will not have hash
values. Thus, this patch updated the ICE_MAX_PTG_PER_PROFILE and
ICE_MAX_TCAM_PER_PROFILE to a larger number 64.

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-08-11 04:25:34 +02:00
Qi Zhang
34be38f024 net/ice/base: fix typo in comment
Correct spelling of word data instead of date.

Fixes: 453d087cca ("net/ice/base: add common functions")
Cc: stable@dpdk.org

Signed-off-by: Kevin Scott <kevin.c.scott@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-08-11 04:25:29 +02:00
Qi Zhang
274eb0541e net/ice/base: rename and add setter for unicast MAC flag
Rename ucast_shared to umac_shared, as "umac" is a more widely
used shorthand for "unicast MAC".

Also add a helper function to set this flag. This helper is
expected to be called by core drivers.

Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-08-11 04:25:25 +02:00
Qi Zhang
4081cbd966 net/ice/base: support flow director for GTPU UL/DL with QFI
Enable Flow Director filtering for GTPU UL/DL QFI field matching.

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-08-11 04:25:21 +02:00
Qi Zhang
34a298a50b net/ice/base: enable jumbo frame during HW init
Call ice_aq_set_mac_cfg in ice_hw_init to enable jumbo frame support.

Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-08-11 04:25:17 +02:00
Qi Zhang
63137fa561 net/ice/base: support RSS for IPv4/L4 checksum
The IPv4/TCP/UDP/SCTP header checksum fields are defined in this
patch and can be used as RSS input sets.

Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Junfeng Guo <junfeng.guo@intel.com>
2021-08-11 04:25:13 +02:00